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Mon, 4 Sep 2023 09:52:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A8.mail.protection.outlook.com (10.167.243.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:52:42 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:52:37 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 01/13] KVM: Add KVM_GET_LAPIC_W_EXTAPIC and KVM_SET_LAPIC_W_EXTAPIC for extapic Date: Mon, 4 Sep 2023 09:53:35 +0000 Message-ID: <20230904095347.14994-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A8:EE_|MN2PR12MB4157:EE_ X-MS-Office365-Filtering-Correlation-Id: 98012142-aa3b-40b3-c966-08dbad2caeba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:52:42.3137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98012142-aa3b-40b3-c966-08dbad2caeba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4157 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org There are four additional extended LVT registers available in extended APIC register space which can be used for additional interrupt sources like instruction based sampling and many more. Please refer to AMD programmers's manual Volume 2, Section 16.4.5 for more details on extapic. https://bugzilla.kernel.org/attachment.cgi?id=304653 Adds two new vcpu-based IOCTLs to save and restore the local APIC registers with extended APIC register space for a single vcpu. It works same as KVM_GET_LAPIC and KVM_SET_LAPIC IOCTLs. The only differece is the size of APIC page which is copied/restored by kernel. In case of KVM_GET_LAPIC_W_EXTAPIC and KVM_SET_LAPIC_W_EXTAPIC IOCTLs, kernel copies/restores the APIC page with extended APIC register space located at APIC offsets 400h-530h. KVM_GET_LAPIC_W_EXTAPIC and KVM_SET_LAPIC_W_EXTAPIC IOCTLs are used when extended APIC is enabled in the guest. Document KVM_GET_LAPIC_W_EXTAPIC, KVM_SET_LAPIC_W_EXTAPIC ioctls. Signed-off-by: Manali Shukla --- Documentation/virt/kvm/api.rst | 23 +++++++++++++++++++++++ arch/x86/include/uapi/asm/kvm.h | 5 +++++ arch/x86/kvm/lapic.c | 12 +++++++----- arch/x86/kvm/lapic.h | 6 ++++-- arch/x86/kvm/x86.c | 24 +++++++++++++----------- include/uapi/linux/kvm.h | 10 ++++++++++ 6 files changed, 62 insertions(+), 18 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 73db30cb60fb..7239d4f1ecf3 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -1961,6 +1961,18 @@ error. Reads the Local APIC registers and copies them into the input argument. The data format and layout are the same as documented in the architecture manual. +:: + + #define KVM_APIC_EXT_REG_SIZE 0x540 + struct kvm_lapic_state_w_extapic { + __u8 regs[KVM_APIC_EXT_REG_SIZE]; + }; + +Applications should use KVM_GET_LAPIC_W_EXTAPIC ioctl if extended APIC is +enabled. KVM_GET_LAPIC_W_EXTAPIC reads Local APIC registers with extended +APIC register space located at offsets 500h-530h and copies them into input +argument. + If KVM_X2APIC_API_USE_32BIT_IDS feature of KVM_CAP_X2APIC_API is enabled, then the format of APIC_ID register depends on the APIC mode (reported by MSR_IA32_APICBASE) of its VCPU. x2APIC stores APIC ID in @@ -1992,6 +2004,17 @@ always uses xAPIC format. Copies the input argument into the Local APIC registers. The data format and layout are the same as documented in the architecture manual. +:: + + #define KVM_APIC_EXT_REG_SIZE 0x540 + struct kvm_lapic_state_w_extapic { + __u8 regs[KVM_APIC_EXT_REG_SIZE]; + }; + +Applications should use KVM_SET_LAPIC_W_EXTAPIC ioctl if extended APIC is enabled. +KVM_SET_LAPIC_W_EXTAPIC copies input arguments with extended APIC register into +Local APIC and extended APIC registers. + The format of the APIC ID register (bytes 32-35 of struct kvm_lapic_state's regs field) depends on the state of the KVM_CAP_X2APIC_API capability. See the note in KVM_GET_LAPIC. diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index 1a6a1f987949..d5bed64fd73d 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -123,6 +123,11 @@ struct kvm_lapic_state { char regs[KVM_APIC_REG_SIZE]; }; +#define KVM_APIC_EXT_REG_SIZE 0x540 +struct kvm_lapic_state_w_extapic { + __u8 regs[KVM_APIC_EXT_REG_SIZE]; +}; + struct kvm_segment { __u64 base; __u32 limit; diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index dcd60b39e794..7c1bd8594f1b 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2921,7 +2921,7 @@ int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) } static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, - struct kvm_lapic_state *s, bool set) + struct kvm_lapic_state_w_extapic *s, bool set) { if (apic_x2apic_mode(vcpu->arch.apic)) { u32 *id = (u32 *)(s->regs + APIC_ID); @@ -2958,9 +2958,10 @@ static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu, return 0; } -int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) +int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state_w_extapic *s, + unsigned int size) { - memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); + memcpy(s->regs, vcpu->arch.apic->regs, size); /* * Get calculated timer current count for remaining timer period (if @@ -2972,7 +2973,8 @@ int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) return kvm_apic_state_fixup(vcpu, s, false); } -int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) +int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state_w_extapic *s, + unsigned int size) { struct kvm_lapic *apic = vcpu->arch.apic; int r; @@ -2986,7 +2988,7 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s) kvm_recalculate_apic_map(vcpu->kvm); return r; } - memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); + memcpy(vcpu->arch.apic->regs, s->regs, size); atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); kvm_recalculate_apic_map(vcpu->kvm); diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index 0a0ea4b5dd8c..ad6c48938733 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -121,8 +121,10 @@ void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high); u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); -int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); -int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); +int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state_w_extapic *s, + unsigned int size); +int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state_w_extapic *s, + unsigned int size); enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu); int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ddab7d0bb52b..e80a6d598753 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -4925,19 +4925,19 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) } static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu, - struct kvm_lapic_state *s) + struct kvm_lapic_state_w_extapic *s, unsigned int size) { static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu); - return kvm_apic_get_state(vcpu, s); + return kvm_apic_get_state(vcpu, s, size); } static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu, - struct kvm_lapic_state *s) + struct kvm_lapic_state_w_extapic *s, unsigned int size) { int r; - r = kvm_apic_set_state(vcpu, s); + r = kvm_apic_set_state(vcpu, s, size); if (r) return r; update_cr8_intercept(vcpu); @@ -5636,7 +5636,7 @@ long kvm_arch_vcpu_ioctl(struct file *filp, int r; union { struct kvm_sregs2 *sregs2; - struct kvm_lapic_state *lapic; + struct kvm_lapic_state_w_extapic *lapic; struct kvm_xsave *xsave; struct kvm_xcrs *xcrs; void *buffer; @@ -5646,36 +5646,38 @@ long kvm_arch_vcpu_ioctl(struct file *filp, u.buffer = NULL; switch (ioctl) { + case KVM_GET_LAPIC_W_EXTAPIC: case KVM_GET_LAPIC: { r = -EINVAL; if (!lapic_in_kernel(vcpu)) goto out; - u.lapic = kzalloc(sizeof(struct kvm_lapic_state), - GFP_KERNEL_ACCOUNT); + u.lapic = kzalloc(_IOC_SIZE(ioctl), GFP_KERNEL_ACCOUNT); r = -ENOMEM; if (!u.lapic) goto out; - r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic); + r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic, _IOC_SIZE(ioctl)); if (r) goto out; r = -EFAULT; - if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state))) + if (copy_to_user(argp, u.lapic, _IOC_SIZE(ioctl))) goto out; r = 0; break; } + case KVM_SET_LAPIC_W_EXTAPIC: case KVM_SET_LAPIC: { r = -EINVAL; if (!lapic_in_kernel(vcpu)) goto out; - u.lapic = memdup_user(argp, sizeof(*u.lapic)); + u.lapic = memdup_user(argp, _IOC_SIZE(ioctl)); + if (IS_ERR(u.lapic)) { r = PTR_ERR(u.lapic); goto out_nofree; } - r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic); + r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic, _IOC_SIZE(ioctl)); break; } case KVM_INTERRUPT: { diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 13065dd96132..e1dc04e0bf44 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1591,6 +1591,16 @@ struct kvm_s390_ucas_mapping { #define KVM_SET_FPU _IOW(KVMIO, 0x8d, struct kvm_fpu) #define KVM_GET_LAPIC _IOR(KVMIO, 0x8e, struct kvm_lapic_state) #define KVM_SET_LAPIC _IOW(KVMIO, 0x8f, struct kvm_lapic_state) +/* + * Added to save/restore local APIC registers with extended APIC (extapic) + * register space. + * + * Qemu emulates extapic logic only when KVM enables extapic functionality via + * KVM capability. In the condition where Qemu sets extapic registers, but KVM doesn't + * set extapic capability, Qemu ends up using KVM_GET_LAPIC and KVM_SET_LAPIC. + */ +#define KVM_GET_LAPIC_W_EXTAPIC _IOR(KVMIO, 0x8e, struct kvm_lapic_state_w_extapic) +#define KVM_SET_LAPIC_W_EXTAPIC _IOW(KVMIO, 0x8f, struct kvm_lapic_state_w_extapic) #define KVM_SET_CPUID2 _IOW(KVMIO, 0x90, struct kvm_cpuid2) #define KVM_GET_CPUID2 _IOWR(KVMIO, 0x91, struct kvm_cpuid2) /* Available with KVM_CAP_VAPIC */ From patchwork Mon Sep 4 09:53:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373664 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9FCECA0FF7 for ; Mon, 4 Sep 2023 09:52:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352709AbjIDJxA (ORCPT ); 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Mon, 4 Sep 2023 04:52:41 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 02/13] x86/cpufeatures: Add CPUID feature bit for Extended LVT Date: Mon, 4 Sep 2023 09:53:36 +0000 Message-ID: <20230904095347.14994-3-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|DM6PR12MB4418:EE_ X-MS-Office365-Filtering-Correlation-Id: 63e5f8ce-f26b-48e0-41a4-08dbad2cb134 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0AH+0GwY8cepTTeS1bDgmaSLbCogdHXWsiaDjuerwzAJlnhqPo/7I1C50K72kQzE3QdcnQNXNo+eB0fQkhA9C+yb7k8W5jK9KphzJjJuFmdmlPobKSzcvTOtPa3XhbBmlI7NZMCk88CJMaP8JT22vLcE+HosY7kddTwjK/MzqacQkspjgn5LBy4+FTTTMXwfuFs26RlkNmju1gJrs9JpgbDLYD2PijIgOfHZx7/Zdk8bUoIVjwoWMGQeoUuN5tAJxNUUKSdRzMnUIb33C61aCnaenBrbSFN3D8mzooK2ckR/6M+Yi8+XVDfXOA3xl6ThUXT3OJOBfU3+bmkYW0F2S+tXKwBq4h6R2v3/ZKlrKlF+1nres9sattQ/r3/2jluNxZXVq+zT85TQ3/sK4mArTG4ZeK23eQTLrzDupULamsr6oSA28wiHVrpNWsbu53h9I9fYiiNLGMOiRZsM16FA1V/9tNQ2Pf5gg335vr+ky6XsBHIiT5fBtu3MKVIe3JcBEa06BAh/WOUo8nQUCimgdcyQopkjfbRc3pzA0rEfL42I6ioZfDiPZvfuMQhF5Y1OGARFv8aj7wurbJIsL1duiodcsc5lqB2w0slqRou51R5WYHA0C3BXgL3S3NZMBtcFdYsJH0fDAw6UyCB9OnzD8K0nfGfNjXxMLot7NcUt1negpVF2qNmF+zdZJ9iEEb5XCUolIFs5X2aF4uhlozlUDw5Kq+58w2duvH5BA8oevFBNiEDxTDm2XrtT7zB1X0b7U0ABcIMMagrYIz4QqUuiRA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(376002)(396003)(1800799009)(186009)(82310400011)(451199024)(40470700004)(36840700001)(46966006)(7696005)(40460700003)(41300700001)(54906003)(81166007)(82740400003)(356005)(966005)(2906002)(36756003)(86362001)(316002)(110136005)(70586007)(478600001)(70206006)(6666004)(40480700001)(4326008)(8676002)(8936002)(16526019)(44832011)(426003)(336012)(26005)(83380400001)(2616005)(5660300002)(1076003)(36860700001)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:52:46.4652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63e5f8ce-f26b-48e0-41a4-08dbad2cb134 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4418 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Santosh Shukla Local interrupts can be extended to include more LVT registers in order to allow additional interrupt sources, like Instruction Based Sampling (IBS). The Extended APIC feature register indicates the number of extended Local Vector Table(LVT) registers in the local APIC. Currently, there are 4 extended LVT registers available which are located at APIC offsets (500h-530h). The EXTLVT feature bit changes the behavior associated with reading and writing an extended LVT register. When the EXTLVT feature is enabled, a write to an extended LVT register changes from a fault style #VMEXIT to a trap style #VMEXIT and a read of an extended LVT register no longer triggers a #VMEXIT. Please refer to Section 16.4.5 in AMD Programmer's Manual Volume 2 for more details on EXTLVT. https://bugzilla.kernel.org/attachment.cgi?id=304653 Presence of the EXTLVT feature is indicated via CPUID function 0x8000000A_EDX[27]. Signed-off-by: Santosh Shukla Signed-off-by: Manali Shukla --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 7b4ecbf78d8b..2e4624fa6e4e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -374,6 +374,7 @@ #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */ +#define X86_FEATURE_EXTLVT (15*32+27) /* "" EXTLVT */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */ From patchwork Mon Sep 4 09:53:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2CFEC83F2C for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042AE.mail.protection.outlook.com (10.167.243.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:54:00 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:52:45 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 03/13] KVM: x86: Add emulation support for Extented LVT registers Date: Mon, 4 Sep 2023 09:53:37 +0000 Message-ID: <20230904095347.14994-4-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AE:EE_|MN2PR12MB4285:EE_ X-MS-Office365-Filtering-Correlation-Id: bb36c809-7e20-4228-cef4-08dbad2cdd3d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:54:00.3163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb36c809-7e20-4228-cef4-08dbad2cdd3d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4285 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Santosh Shukla The local interrupts are extended to include more LVT registers in order to allow additional interrupt sources, like Instruction Based Sampling (IBS) and many more. Currently there are four additional LVT registers defined and they are located at APIC offsets 500h-530h. AMD IBS driver is designed to use EXTLVT (Extended interrupt local vector table) by default for driver initialization. Extended LVT registers are required to be emulated to initialize the guest IBS driver successfully. Please refer to Section 16.4.5 in AMD Programmer's Manual Volume 2 at https://bugzilla.kernel.org/attachment.cgi?id=304653 for more details on EXTLVT. Signed-off-by: Santosh Shukla Co-developed-by: Manali Shukla Signed-off-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 14 ++++++++ arch/x86/kvm/lapic.c | 66 ++++++++++++++++++++++++++++++++-- arch/x86/kvm/lapic.h | 1 + arch/x86/kvm/svm/avic.c | 4 +++ 4 files changed, 83 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 4b125e5b3187..ac50919d10be 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -139,6 +139,20 @@ #define APIC_EILVT_MSG_EXT 0x7 #define APIC_EILVT_MASKED (1 << 16) +/* + * Initialize extended APIC registers to the default value when guest is started + * and EXTAPIC feature is enabled on the guest. + * + * APIC_EFEAT is a read only Extended APIC feature register, whose default value + * is 0x00040007. + * + * APIC_ECTRL is a read-write Extended APIC control register, whose default value + * is 0x0. + */ + +#define APIC_EFEAT_DEFAULT 0x00040007 +#define APIC_ECTRL_DEFAULT 0x0 + #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 #define APIC_X2APIC_ID_MSR 0x802 diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 7c1bd8594f1b..88985c481fe8 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1599,9 +1599,13 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) } #define APIC_REG_MASK(reg) (1ull << ((reg) >> 4)) +#define APIC_REG_EXT_MASK(reg) (1ull << (((reg) >> 4) - 0x40)) #define APIC_REGS_MASK(first, count) \ (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) +#define APIC_LAST_REG_OFFSET 0x3f0 +#define APIC_EXT_LAST_REG_OFFSET 0x530 + u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic) { /* Leave bits '0' for reserved and write-only registers. */ @@ -1643,6 +1647,8 @@ EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask); static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, void *data) { + u64 valid_reg_ext_mask = 0; + unsigned int last_reg = APIC_LAST_REG_OFFSET; unsigned char alignment = offset & 0xf; u32 result; @@ -1652,13 +1658,44 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, */ WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR); + /* + * The local interrupts are extended to include LVT registers to allow + * additional interrupt sources when the EXTAPIC feature bit is enabled. + * The Extended Interrupt LVT registers are located at APIC offsets 400-530h. + */ + if (guest_cpuid_has(apic->vcpu, X86_FEATURE_EXTAPIC)) { + valid_reg_ext_mask = + APIC_REG_EXT_MASK(APIC_EFEAT) | + APIC_REG_EXT_MASK(APIC_ECTRL) | + APIC_REG_EXT_MASK(APIC_EILVTn(0)) | + APIC_REG_EXT_MASK(APIC_EILVTn(1)) | + APIC_REG_EXT_MASK(APIC_EILVTn(2)) | + APIC_REG_EXT_MASK(APIC_EILVTn(3)); + last_reg = APIC_EXT_LAST_REG_OFFSET; + } + if (alignment + len > 4) return 1; - if (offset > 0x3f0 || - !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) + if (offset > last_reg) return 1; + switch (offset) { + /* + * Section 16.3.2 in the AMD Programmer's Manual Volume 2 states: + * "APIC registers are aligned to 16-byte offsets and must be accessed + * using naturally-aligned DWORD size read and writes." + */ + case KVM_APIC_REG_SIZE ... KVM_APIC_EXT_REG_SIZE - 16: + if (!(valid_reg_ext_mask & APIC_REG_EXT_MASK(offset))) + return 1; + break; + default: + if (!(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) + return 1; + + } + result = __apic_read(apic, offset & ~0xf); trace_kvm_apic_read(offset, result); @@ -2386,6 +2423,12 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) else kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); break; + case APIC_EILVTn(0): + case APIC_EILVTn(1): + case APIC_EILVTn(2): + case APIC_EILVTn(3): + kvm_lapic_set_reg(apic, reg, val); + break; default: ret = 1; break; @@ -2664,6 +2707,25 @@ void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu) kvm_vcpu_srcu_read_lock(vcpu); } +/* + * Initialize extended APIC registers to the default value when guest is + * started. The extended APIC registers should only be initialized when the + * EXTAPIC feature is enabled on the guest. + */ +void kvm_apic_init_eilvt_regs(struct kvm_vcpu *vcpu) +{ + struct kvm_lapic *apic = vcpu->arch.apic; + int i; + + if (guest_cpuid_has(vcpu, X86_FEATURE_EXTAPIC)) { + kvm_lapic_set_reg(apic, APIC_EFEAT, APIC_EFEAT_DEFAULT); + kvm_lapic_set_reg(apic, APIC_ECTRL, APIC_ECTRL_DEFAULT); + for (i = 0; i < APIC_EILVT_NR_MAX; i++) + kvm_lapic_set_reg(apic, APIC_EILVTn(i), APIC_EILVT_MASKED); + } +} +EXPORT_SYMBOL_GPL(kvm_apic_init_eilvt_regs); + void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) { struct kvm_lapic *apic = vcpu->arch.apic; diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h index ad6c48938733..b0c7393cd6af 100644 --- a/arch/x86/kvm/lapic.h +++ b/arch/x86/kvm/lapic.h @@ -93,6 +93,7 @@ int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); int kvm_apic_accept_events(struct kvm_vcpu *vcpu); void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); +void kvm_apic_init_eilvt_regs(struct kvm_vcpu *vcpu); u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index cfc8ab773025..081075674b1d 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -679,6 +679,10 @@ static bool is_avic_unaccelerated_access_trap(u32 offset) case APIC_LVTERR: case APIC_TMICT: case APIC_TDCR: + case APIC_EILVTn(0): + case APIC_EILVTn(1): + case APIC_EILVTn(2): + case APIC_EILVTn(3): ret = true; break; default: From patchwork Mon Sep 4 09:53:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2AF9C83F3F for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000042A9.mail.protection.outlook.com (10.167.243.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:54:01 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:53:24 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 04/13] x86/cpufeatures: Add CPUID feature bit for virtualized IBS Date: Mon, 4 Sep 2023 09:53:38 +0000 Message-ID: <20230904095347.14994-5-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A9:EE_|SN7PR12MB7855:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f0afed9-9949-4c5e-db51-08dbad2cde2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:54:01.9208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f0afed9-9949-4c5e-db51-08dbad2cde2d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7855 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Santosh Shukla The virtualized IBS (VIBS) feature allows the guest to collect IBS samples without exiting the guest. Presence of the VIBS feature is indicated via CPUID function 0x8000000A_EDX[26]. Signed-off-by: Santosh Shukla Signed-off-by: Manali Shukla --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2e4624fa6e4e..8f92fa6d8319 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -374,6 +374,7 @@ #define X86_FEATURE_X2AVIC (15*32+18) /* Virtual x2apic */ #define X86_FEATURE_V_SPEC_CTRL (15*32+20) /* Virtual SPEC_CTRL */ #define X86_FEATURE_VNMI (15*32+25) /* Virtual NMI */ +#define X86_FEATURE_VIBS (15*32+26) /* "" Virtual IBS */ #define X86_FEATURE_EXTLVT (15*32+27) /* "" EXTLVT */ #define X86_FEATURE_SVME_ADDR_CHK (15*32+28) /* "" SVME addr check */ From patchwork Mon Sep 4 09:53:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CB8ECA0FFB for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:54:05.1424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28d0db8b-0d4f-4fc0-6f80-08dbad2ce019 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5947 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a KVM-only leaf for AMD's Instruction Based Sampling capabilities. There are 10 capabilities which are added to KVM-only leaf, so that KVM can set these capabilities for the guest, when IBS feature bit is enabled on the guest. Signed-off-by: Manali Shukla --- arch/x86/kvm/reverse_cpuid.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index b81650678375..c6386c431fa6 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -15,6 +15,7 @@ enum kvm_only_cpuid_leafs { CPUID_12_EAX = NCAPINTS, CPUID_7_1_EDX, CPUID_8000_0007_EDX, + CPUID_8000_001B_EAX, CPUID_8000_0022_EAX, NR_KVM_CPU_CAPS, @@ -52,6 +53,19 @@ enum kvm_only_cpuid_leafs { /* CPUID level 0x80000022 (EAX) */ #define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0) +/* AMD defined Instruction-base Sampling capabilities. CPUID level 0x8000001B (EAX). */ +#define X86_FEATURE_IBS_AVAIL KVM_X86_FEATURE(CPUID_8000_001B_EAX, 0) +#define X86_FEATURE_IBS_FETCHSAM KVM_X86_FEATURE(CPUID_8000_001B_EAX, 1) +#define X86_FEATURE_IBS_OPSAM KVM_X86_FEATURE(CPUID_8000_001B_EAX, 2) +#define X86_FEATURE_IBS_RDWROPCNT KVM_X86_FEATURE(CPUID_8000_001B_EAX, 3) +#define X86_FEATURE_IBS_OPCNT KVM_X86_FEATURE(CPUID_8000_001B_EAX, 4) +#define X86_FEATURE_IBS_BRNTRGT KVM_X86_FEATURE(CPUID_8000_001B_EAX, 5) +#define X86_FEATURE_IBS_OPCNTEXT KVM_X86_FEATURE(CPUID_8000_001B_EAX, 6) +#define X86_FEATURE_IBS_RIPINVALIDCHK KVM_X86_FEATURE(CPUID_8000_001B_EAX, 7) +#define X86_FEATURE_IBS_OPBRNFUSE KVM_X86_FEATURE(CPUID_8000_001B_EAX, 8) +#define X86_FEATURE_IBS_FETCHCTLEXTD KVM_X86_FEATURE(CPUID_8000_001B_EAX, 9) +#define X86_FEATURE_IBS_ZEN4_EXT KVM_X86_FEATURE(CPUID_8000_001B_EAX, 11) + struct cpuid_reg { u32 function; u32 index; @@ -80,6 +94,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, + [CPUID_8000_001B_EAX] = {0x8000001b, 0, CPUID_EAX}, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:54:45.7763 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 64b2caca-44b6-4d67-c1d9-08dbad2cf845 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org CPUID leaf 0x8000001b (EAX) provides information about Instruction-Based sampling capabilities on AMD Platforms. Complete description about 0x8000001b CPUID leaf is available in AMD Programmer's Manual volume 3, Appendix E, section E.4.13. https://bugzilla.kernel.org/attachment.cgi?id=304655 Signed-off-by: Manali Shukla --- arch/x86/kvm/cpuid.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 0544e30b4946..1f4d505fb69d 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -771,6 +771,12 @@ void kvm_set_cpu_caps(void) F(PERFMON_V2) ); + /* + * Hide all IBS related features by default, it will be enabled + * automatically when IBS virtualization is enabled + */ + kvm_cpu_cap_init_kvm_defined(CPUID_8000_001B_EAX, 0); + /* * Synthesize "LFENCE is serializing" into the AMD-defined entry in * KVM's supported CPUID if the feature is reported as supported by the @@ -1252,6 +1258,11 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->eax = entry->ebx = entry->ecx = 0; entry->edx = 0; /* reserved */ break; + /* AMD IBS capability */ + case 0x8000001B: + entry->eax = entry->ebx = entry->ecx = entry->edx = 0; + cpuid_entry_override(entry, CPUID_8000_001B_EAX); + break; case 0x8000001F: if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { entry->eax = entry->ebx = entry->ecx = entry->edx = 0; From patchwork Mon Sep 4 09:53:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD3E2C83F3F for ; Mon, 4 Sep 2023 09:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238304AbjIDJ5Q (ORCPT ); Mon, 4 Sep 2023 05:57:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231599AbjIDJ5P (ORCPT ); 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Mon, 4 Sep 2023 04:54:45 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 07/13] KVM: SVM: Extend VMCB area for virtualized IBS registers Date: Mon, 4 Sep 2023 09:53:41 +0000 Message-ID: <20230904095347.14994-8-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529F:EE_|SJ0PR12MB5609:EE_ X-MS-Office365-Filtering-Correlation-Id: 7317ebde-fd99-4047-8cac-08dbad2cfa7a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UchAzi/p6bMtupLV2Kc6hPf/tsiE/B7oQ/08+FUUh7YSKw8hEl53K02mKfJR5vWfiXZYb2gyXMnGyAYa1cEXvvHyPqQy8/iwgUUK934ISobQHtpia6URRX28CJvaxVkeExVw6zGIFcknAyGp3OzW8ouaGQ9cEf69M/ev/nYSXo32IrSjskrqfWao/UX0MN6rvBu5LNBH6vD7x37cvHqDTcKiyDc0w4JRCmT99uWhDvX3XJgjTfIa5qNkM1HGFNGeMXtljA80TC398L5yXPv1l7/eYt+NNO1ilQ79RF5OWEZrZJ8hMTClS8oBZZBnrbpJuuqyW8I8yrKLyRrhD0P/lR4LmyCEylM9QaXFWr/pqumB/xnCBerKXxALtycfoAyDsafY9juxVa4EB63aN5YQFxFGdFkHl1c8D3SL5QxQFLdwh8Yb4PvHJPmLjs0xe++dcJDt9uoLUljXjgLpHyyxY50twty9eD+Qty9+6Rgr+9Y5/M9vbnXRxQIgIeCY33eorpm+2aPz0Gv/2lO2PHLCqxo034SuKvi6WSmRIBNXgHD4cytAk8A89KRX4BXjSkTqoYWdV8JQFrNwiUXTAQ+MrvoC0Tv/qXP2HHbTpDp+iHQlt0AGX6LNVWFgGMr2zmMb6omeT8THfnrKKh7gPHswA6Ss4v+sKO02mhM08IMz4qh3P5HUc18U8fMrYkzC5LBHJWuaF4s/y+qrfhNCtYpMEVGLspbx2L8RwCYbwLqEON+xi71YMn2J5vkc4QNmCoRPmxxE5KVONMMLrxlaH6hs3g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(346002)(39860400002)(396003)(376002)(186009)(1800799009)(82310400011)(451199024)(40470700004)(36840700001)(46966006)(40460700003)(41300700001)(478600001)(356005)(82740400003)(81166007)(6666004)(86362001)(2616005)(83380400001)(336012)(26005)(16526019)(1076003)(7696005)(36860700001)(40480700001)(426003)(47076005)(70206006)(70586007)(54906003)(2906002)(110136005)(36756003)(316002)(8936002)(5660300002)(8676002)(44832011)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:54:49.4933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7317ebde-fd99-4047-8cac-08dbad2cfa7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5609 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Santosh Shukla VMCB state save is extended to hold guest values of the fetch and op IBS registers. Signed-off-by: Santosh Shukla Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index dee9fa91120b..4096d2f68770 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -346,6 +346,19 @@ struct vmcb_save_area { u64 last_excp_to; u8 reserved_0x298[72]; u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */ + u8 reserved_0x2e8[904]; + u8 lbr_stack_from_to[256]; + u64 lbr_select; + u64 ibs_fetch_ctl; + u64 ibs_fetch_linear_addr; + u64 ibs_op_ctl; + u64 ibs_op_rip; + u64 ibs_op_data; + u64 ibs_op_data2; + u64 ibs_op_data3; + u64 ibs_dc_linear_addr; + u64 ibs_br_target; + u64 ibs_fetch_extd_ctl; } __packed; /* Save area definition for SEV-ES and SEV-SNP guests */ @@ -512,7 +525,7 @@ struct ghcb { } __packed; -#define EXPECTED_VMCB_SAVE_AREA_SIZE 744 +#define EXPECTED_VMCB_SAVE_AREA_SIZE 1992 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 @@ -537,6 +550,7 @@ static inline void __unused_size_checks(void) BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180); BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248); BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298); + BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x2e8); BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8); BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc); From patchwork Mon Sep 4 09:53:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DC13C83F33 for ; Mon, 4 Sep 2023 09:56:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236158AbjIDJ46 (ORCPT ); Mon, 4 Sep 2023 05:56:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233977AbjIDJ45 (ORCPT ); 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Mon, 4 Sep 2023 04:54:49 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 08/13] perf/x86/amd: Add framework to save/restore host IBS state Date: Mon, 4 Sep 2023 09:53:42 +0000 Message-ID: <20230904095347.14994-9-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|CY8PR12MB8364:EE_ X-MS-Office365-Filtering-Correlation-Id: 343c5311-4d66-4868-9544-08dbad2d1928 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gQ+VWFPFXdOeWYcdsY6P8uwkO8ZIJVIoQZtEqE/2W1WCl+TO22xYD/CYXZl751Nn5kpndw5vZf/HK7nzsuqEfW4Y0tsoPc3VI4VbSsidKIsa/TTjUQm4d8G1TYqIcy1VB+pcvqYirf1dGDy9Ma+9rDCjvjI2puCsR3skm1YYgkW/ihZz1ig5Ifpv8yHR/fEy4muwFxL7MS59DNYwXGwmncLDhKz/BBk+xxpa85VXGIC5hjlPWIZ3YA/qaPvFmZ+aWxN8IvDaQNoHuotUO/QiiPXtGLRDjyijcbqJJOcewijeFES8OeQFljoF1AqBDcA0nYYC01jZVoxz0KtXc2SOtp7VgKR8ppbqprw3lnd8eJEfckjSUZO12Kr6cqD2ixGZoDwGvkTB0K8JAVh5Ldq6WbI2ruBqeuzRCe2XBzaa0zQg2dxQyJVgdtDl+M5gpVhbYJINMj1WxiMQ43eApPtmDLJwnJy328sCWRKDRlHULAV8xstbOCQ23ZL5Wg+eimgXB88BS3at871nYr+PBr02vI7ImUZZ8NNOO2i1+LWGX0lgGoq6TRTghHiiDoGSfgKHkw+uU0uUGygCMKnsuQCyV43W3qbnMrgATBgEG+E4AWCv3Xlc8g0C/d7ZjqdP/CsjvoDznmdsw0fkp2CXDrWX7xUaxOPgf+tBm522+kvi46CdnBDlbbSLvOVVPiLeq2EVmcBwZ2r0sEANe0kgC+RKyXE+YjF+vk8Kvy9nNWDpuHts3ywmaLx1BzWB8JGfQfnZnSH0xqUuCT1PiGzo2PH4NA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199024)(1800799009)(186009)(82310400011)(40470700004)(36840700001)(46966006)(316002)(110136005)(36756003)(54906003)(2906002)(86362001)(70206006)(70586007)(40480700001)(8936002)(5660300002)(44832011)(4326008)(8676002)(41300700001)(40460700003)(36860700001)(426003)(2616005)(83380400001)(336012)(1076003)(26005)(16526019)(47076005)(966005)(478600001)(81166007)(356005)(82740400003)(7696005)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:55:40.9499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 343c5311-4d66-4868-9544-08dbad2d1928 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8364 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since IBS registers falls under swap type C [1], only the guest state is saved and restored automatically by the hardware. Host state needs to be saved and restored manually by the hypervisor. Note that, saving and restoring of host IBS state happens only when IBS is active on host to avoid unnecessary rdmsrs/wrmsrs. Also, hypervisor needs to disable host IBS before VMRUN and re-enable it after VMEXIT [2]. However, disabling and enabling of IBS leads to subtle races between software and hardware since IBS_*_CTL registers contain both control and result bits in the same MSR. Consider the following scenario, hypervisor reads IBS control MSR and finds enable=1 (control bit) and valid=0 (result bit). While kernel is clearing enable bit in its local copy, IBS hardware sets valid bit to 1 in the MSR. Software, who is unaware of the change done by IBS hardware, overwrites IBS MSR with enable=0 and valid=0. Note that, this situation occurs while NMIs are disabled. So CPU will receive IBS NMI only after STGI. However, the IBS driver won't handle NMI because of the valid bit being 0. Since the real source of NMI was IBS, nobody else will also handle it which will result in the unknown NMIs. Handle the above mentioned race by keeping track of different actions performed by KVM on IBS: WINDOW_START: After CLGI and before VMRUN. KVM informs IBS driver about its intention to enable IBS for the guest. Thus IBS should be disabled on host and IBS host register state should be saved. WINDOW_STOPPING: After VMEXIT and before STGI. KVM informs IBS driver that it's done using IBS inside the guest and thus host IBS state should be restored followed by re-enabling IBS for host. WINDOW_STOPPED: After STGI. CPU will receive any pending NMI if it was raised between CLGI and STGI. NMI will be marked as handled by IBS driver if WINDOW_STOPPED action is _not performed, valid bit is _not_ set and a valid IBS event exists. However, IBS sample won't be generated. [1]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Appendix B Layout of VMCB, Table B-3 Swap Types. [2]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Section 15.38 Instruction-Based Sampling Virtualization. Signed-off-by: Manali Shukla --- arch/x86/events/amd/Makefile | 2 +- arch/x86/events/amd/ibs.c | 23 +++++++ arch/x86/events/amd/vibs.c | 101 ++++++++++++++++++++++++++++++ arch/x86/include/asm/perf_event.h | 27 ++++++++ 4 files changed, 152 insertions(+), 1 deletion(-) create mode 100644 arch/x86/events/amd/vibs.c diff --git a/arch/x86/events/amd/Makefile b/arch/x86/events/amd/Makefile index 527d947eb76b..13c2980db9a7 100644 --- a/arch/x86/events/amd/Makefile +++ b/arch/x86/events/amd/Makefile @@ -2,7 +2,7 @@ obj-$(CONFIG_CPU_SUP_AMD) += core.o lbr.o obj-$(CONFIG_PERF_EVENTS_AMD_BRS) += brs.o obj-$(CONFIG_PERF_EVENTS_AMD_POWER) += power.o -obj-$(CONFIG_X86_LOCAL_APIC) += ibs.o +obj-$(CONFIG_X86_LOCAL_APIC) += ibs.o vibs.o obj-$(CONFIG_PERF_EVENTS_AMD_UNCORE) += amd-uncore.o amd-uncore-objs := uncore.o ifdef CONFIG_AMD_IOMMU diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 6911c5399d02..359464f2910d 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1039,6 +1039,16 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) */ if (test_and_clear_bit(IBS_STOPPED, pcpu->state)) return 1; + /* + * Catch NMIs generated in an active IBS window: Incoming NMIs + * from an active IBS window might have the VALID bit cleared + * when it is supposed to be set due to a race. The reason for + * the race is ENABLE and VALID bits for MSR_AMD64_IBSFETCHCTL + * and MSR_AMD64_IBSOPCTL being in their same respective MSRs. + * Ignore all such NMIs and treat them as handled. + */ + if (amd_vibs_ignore_nmi()) + return 1; return 0; } @@ -1542,3 +1552,16 @@ static __init int amd_ibs_init(void) /* Since we need the pci subsystem to init ibs we can't do this earlier: */ device_initcall(amd_ibs_init); + +static inline bool get_ibs_state(struct perf_ibs *perf_ibs) +{ + struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu); + + return test_bit(IBS_STARTED, pcpu->state); +} + +bool is_amd_ibs_started(void) +{ + return get_ibs_state(&perf_ibs_fetch) || get_ibs_state(&perf_ibs_op); +} +EXPORT_SYMBOL_GPL(is_amd_ibs_started); diff --git a/arch/x86/events/amd/vibs.c b/arch/x86/events/amd/vibs.c new file mode 100644 index 000000000000..273a60f1cb7f --- /dev/null +++ b/arch/x86/events/amd/vibs.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Virtualized Performance events - AMD VIBS + * + * Copyright (C) 2023 Advanced Micro Devices, Inc., Manali Shukla + * + * For licencing details see kernel-base/COPYING + */ + +#include + +DEFINE_PER_CPU(bool, vibs_window_active); + +static bool amd_disable_ibs_fetch(u64 *ibs_fetch_ctl) +{ + *ibs_fetch_ctl = __rdmsr(MSR_AMD64_IBSFETCHCTL); + if (!(*ibs_fetch_ctl & IBS_FETCH_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, *ibs_fetch_ctl & ~IBS_FETCH_ENABLE); + + return true; +} + +static u64 amd_disable_ibs_op(u64 *ibs_op_ctl) +{ + *ibs_op_ctl = __rdmsr(MSR_AMD64_IBSOPCTL); + if (!(*ibs_op_ctl & IBS_OP_ENABLE)) + return false; + + native_wrmsrl(MSR_AMD64_IBSOPCTL, *ibs_op_ctl & ~IBS_OP_ENABLE); + + return true; +} + +static void amd_restore_ibs_fetch(u64 ibs_fetch_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSFETCHCTL, ibs_fetch_ctl); +} + +static void amd_restore_ibs_op(u64 ibs_op_ctl) +{ + native_wrmsrl(MSR_AMD64_IBSOPCTL, ibs_op_ctl); +} + +bool amd_vibs_ignore_nmi(void) +{ + return __this_cpu_read(vibs_window_active); +} +EXPORT_SYMBOL_GPL(amd_vibs_ignore_nmi); + +bool amd_vibs_window(enum amd_vibs_window_state state, u64 *f_ctl, + u64 *o_ctl) +{ + bool f_active, o_active; + + switch (state) { + case WINDOW_START: + if (!f_ctl || !o_ctl) + return false; + + if (!is_amd_ibs_started()) + return false; + + f_active = amd_disable_ibs_fetch(f_ctl); + o_active = amd_disable_ibs_op(o_ctl); + __this_cpu_write(vibs_window_active, (f_active || o_active)); + break; + + case WINDOW_STOPPING: + if (!f_ctl || !o_ctl) + return false; + + if (__this_cpu_read(vibs_window_active)) + return false; + + if (*f_ctl & IBS_FETCH_ENABLE) + amd_restore_ibs_fetch(*f_ctl); + if (*o_ctl & IBS_OP_ENABLE) + amd_restore_ibs_op(*o_ctl); + + break; + + case WINDOW_STOPPED: + /* + * This state is executed right after STGI (which is executed + * after VMEXIT). By this time, host IBS states are already + * restored in WINDOW_STOPPING state, so f_ctl and o_ctl will + * be passed as NULL for this state. + */ + if (__this_cpu_read(vibs_window_active)) + __this_cpu_write(vibs_window_active, false); + break; + + default: + return false; + } + + return __this_cpu_read(vibs_window_active); +} +EXPORT_SYMBOL_GPL(amd_vibs_window); diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 85a9fd5a3ec3..b87c235e0e1e 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -486,6 +486,12 @@ struct pebs_xmm { #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */ #define IBS_RIP_INVALID (1ULL<<38) +enum amd_vibs_window_state { + WINDOW_START = 0, + WINDOW_STOPPING, + WINDOW_STOPPED, +}; + #ifdef CONFIG_X86_LOCAL_APIC extern u32 get_ibs_caps(void); extern int forward_event_to_ibs(struct perf_event *event); @@ -584,6 +590,27 @@ static inline void intel_pt_handle_vmx(int on) } #endif +#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_CPU_SUP_AMD) +extern bool amd_vibs_window(enum amd_vibs_window_state state, u64 *vibs_fetch_ctl, + u64 *vibs_op_ctl); +extern bool is_amd_ibs_started(void); +extern bool amd_vibs_ignore_nmi(void); +#else +static inline bool amd_vibs_window(enum amd_vibs_window_state state, u64 *vibs_fetch_ctl, + u64 *vibs_op_ctl) +{ + return false; +} +static inline bool is_amd_ibs_started(void) +{ + return false; +} +static inline bool amd_vibs_ignore_nmi(void) +{ + return false; +} +#endif + #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) extern void amd_pmu_enable_virt(void); extern void amd_pmu_disable_virt(void); From patchwork Mon Sep 4 09:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDDFFC83F3F for ; Mon, 4 Sep 2023 09:57:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237573AbjIDJ5d (ORCPT ); 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Mon, 4 Sep 2023 04:55:40 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 09/13] KVM: SVM: add support for IBS virtualization for non SEV-ES guests Date: Mon, 4 Sep 2023 09:53:43 +0000 Message-ID: <20230904095347.14994-10-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343B:EE_|SJ0PR12MB7459:EE_ X-MS-Office365-Filtering-Correlation-Id: 433bc5f8-1cf0-448b-8687-08dbad2d4c9b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UXrD4SCMBCh+ob3lgwVyrqok/6cNSecOZYVMfq9XoSdW68EZWFXkuoY1U8SuISMX9faEjC68REiWqGJHLz13wqJt+6O7vXHvrMBh+Ad/CQ5IZs9wiIyrZnNkTmxS4RDQut5DAZV4/kzBrILbv+igxyVp5Io5G2v8RCACdkV3AoxnxIaTgDM4aOkaT6PzV2j+IIafVuZnN1DXox65+nLtvjWlK81WK0YAjEeCdZQG4KdwPy4MDBZAIIZZCBRYnqmnuZ8QuoX0QoMVygzC8azjG699e82nL7TNDgRYjLB5F4B6/18MzIX+ZGLAkNSewWRPqLBaFVeTiT0IlB3AQ/H343jvQCsaT0/czpBEv97yIH3lmfxcv9LfI1jljkQRkUF948dAKyv5/uPvSPErbEdgr5/o/LZhp6rOC1TfVuLau004Kk6wSk229Rt3QyPeEfg2E+NLAwrEK27k3liNNiTKNg65zcAOHF24R5OXZPIZNsMEAYfjwROETF1iDPRk7V7qjpjmHvs+JCBU1sFBViMwlwyJby8zZLKlaZsPUzkn5hU3FZpvLzPFeRPTtn6ps+mLSHe3ULdZ73UUs4uZ1Dg9vZwLApigtuyPmgEHdkup+hCmqMHh0h2kE4rN6CzW55wU0GxM6A1U6vXoOYzEofxDebq79XNhCVYVJogpUc7RZCByvDmOqBw15XvsNuP4NrKOVshZMvRSVEWm/bcXswQ69klU+hLkclphnOXpmBDEyDVtXYqmDCmKCrAINBMNYlkd X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(346002)(39860400002)(451199024)(186009)(1800799009)(82310400011)(36840700001)(40470700004)(46966006)(26005)(44832011)(426003)(336012)(16526019)(40480700001)(8936002)(8676002)(4326008)(36860700001)(47076005)(83380400001)(5660300002)(2616005)(1076003)(54906003)(7696005)(40460700003)(41300700001)(110136005)(478600001)(70206006)(70586007)(86362001)(316002)(356005)(36756003)(2906002)(966005)(81166007)(82740400003)(30864003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:07.2670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 433bc5f8-1cf0-448b-8687-08dbad2d4c9b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7459 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Santosh Shukla IBS virtualization (VIBS) [1] feature allows the guest to collect IBS samples without exiting the guest. There are 2 parts to this feature - Virtualizing the IBS register state. - Ensuring the IBS interrupt is handled in the guest without exiting to the hypervisor. IBS virtualization requires the use of AVIC or NMI virtualization for delivery of a virtualized interrupt from IBS hardware in the guest. Without the virtualized interrupt delivery, the IBS interrupt occurring in the guest will not be delivered to either the guest or the hypervisor. When AVIC is enabled, IBS LVT entry (Extended Interrupt 0 LVT) message type should be programmed to INTR or NMI. So, when the sampled interval for the data collection for IBS fetch/op block is over, VIBS hardware is going to generate a Virtual NMI, but the source of Virtual NMI is different in both AVIC enabled/disabled case. 1) when AVIC is enabled, Virtual NMI is generated via AVIC using extended LVT (EXTLVT). 2) When AVIC is disabled, Virtual NMI is directly generated from hardware. Since IBS registers falls under swap type C [2], only the guest state is saved and restored automatically by the hardware. Host state needs to be saved and restored manually by the hypervisor. Note that, saving and restoring of host IBS state happens only when IBS is active on host. to avoid unnecessary rdmsrs/wrmsrs. Hypervisor needs to disable host IBS before VMRUN and re-enable it after VMEXIT [1]. The IBS virtualization feature for non SEV-ES guests is not enabled in this patch. Later patches enable VIBS for non SEV-ES guests. [1]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Section 15.38 Instruction-Based Sampling Virtualization. [2]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Appendix B Layout of VMCB, Table B-3 Swap Types. Signed-off-by: Santosh Shukla Co-developed-by: Manali Shukla Signed-off-by: Manali Shukla --- arch/x86/kvm/svm/svm.c | 172 ++++++++++++++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 4 +- 2 files changed, 173 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 20fe83eb32ee..6f566ed93f4c 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -139,6 +139,22 @@ static const struct svm_direct_access_msrs { { .index = X2APIC_MSR(APIC_TMICT), .always = false }, { .index = X2APIC_MSR(APIC_TMCCT), .always = false }, { .index = X2APIC_MSR(APIC_TDCR), .always = false }, + { .index = MSR_AMD64_IBSFETCHCTL, .always = false }, + { .index = MSR_AMD64_IBSFETCHLINAD, .always = false }, + { .index = MSR_AMD64_IBSOPCTL, .always = false }, + { .index = MSR_AMD64_IBSOPRIP, .always = false }, + { .index = MSR_AMD64_IBSOPDATA, .always = false }, + { .index = MSR_AMD64_IBSOPDATA2, .always = false }, + { .index = MSR_AMD64_IBSOPDATA3, .always = false }, + { .index = MSR_AMD64_IBSDCLINAD, .always = false }, + { .index = MSR_AMD64_IBSBRTARGET, .always = false }, + { .index = MSR_AMD64_ICIBSEXTDCTL, .always = false }, + { .index = X2APIC_MSR(APIC_EFEAT), .always = false }, + { .index = X2APIC_MSR(APIC_ECTRL), .always = false }, + { .index = X2APIC_MSR(APIC_EILVTn(0)), .always = false }, + { .index = X2APIC_MSR(APIC_EILVTn(1)), .always = false }, + { .index = X2APIC_MSR(APIC_EILVTn(2)), .always = false }, + { .index = X2APIC_MSR(APIC_EILVTn(3)), .always = false }, { .index = MSR_INVALID, .always = false }, }; @@ -217,6 +233,10 @@ module_param(vgif, int, 0444); static int lbrv = true; module_param(lbrv, int, 0444); +/* enable/disable IBS virtualization */ +static int vibs; +module_param(vibs, int, 0444); + static int tsc_scaling = true; module_param(tsc_scaling, int, 0444); @@ -1050,6 +1070,20 @@ void disable_nmi_singlestep(struct vcpu_svm *svm) } } +void svm_ibs_msr_interception(struct vcpu_svm *svm, bool intercept) +{ + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSFETCHCTL, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSFETCHLINAD, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSOPCTL, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSOPRIP, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSOPDATA, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSOPDATA2, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSOPDATA3, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSDCLINAD, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_IBSBRTARGET, !intercept, !intercept); + set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_ICIBSEXTDCTL, !intercept, !intercept); +} + static void grow_ple_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); @@ -1207,6 +1241,29 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) /* No need to intercept these MSRs */ set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); + + /* + * If hardware supports VIBS then no need to intercept IBS MSRS + * when VIBS is enabled in guest. + */ + if (vibs) { + if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_IBS)) { + svm_ibs_msr_interception(svm, false); + svm->ibs_enabled = true; + + /* + * In order to enable VIBS, AVIC/VNMI must be enabled to handle the + * interrupt generated by IBS driver. When AVIC is enabled, once + * data collection for IBS fetch/op block for sampled interval + * provided is done, hardware signals VNMI which is generated via + * AVIC which uses extended LVT registers. That is why extended LVT + * registers are initialized at guest startup. + */ + kvm_apic_init_eilvt_regs(vcpu); + } else { + svm->ibs_enabled = false; + } + } } } @@ -2888,6 +2945,11 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_AMD64_DE_CFG: msr_info->data = svm->msr_decfg; break; + + case MSR_AMD64_IBSCTL: + rdmsrl(MSR_AMD64_IBSCTL, msr_info->data); + break; + default: return kvm_get_msr_common(vcpu, msr_info); } @@ -4038,19 +4100,111 @@ static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu) return EXIT_FASTPATH_NONE; } +/* + * Since the IBS state is swap type C, the hypervisor is responsible for saving + * its own IBS state before VMRUN. + */ +static void svm_save_host_ibs_msrs(struct vmcb_save_area *hostsa) +{ + rdmsrl(MSR_AMD64_IBSFETCHLINAD, hostsa->ibs_fetch_linear_addr); + rdmsrl(MSR_AMD64_IBSOPRIP, hostsa->ibs_op_rip); + rdmsrl(MSR_AMD64_IBSOPDATA, hostsa->ibs_op_data); + rdmsrl(MSR_AMD64_IBSOPDATA2, hostsa->ibs_op_data2); + rdmsrl(MSR_AMD64_IBSOPDATA3, hostsa->ibs_op_data3); + rdmsrl(MSR_AMD64_IBSDCLINAD, hostsa->ibs_dc_linear_addr); + rdmsrl(MSR_AMD64_IBSBRTARGET, hostsa->ibs_br_target); + rdmsrl(MSR_AMD64_ICIBSEXTDCTL, hostsa->ibs_fetch_extd_ctl); +} + +/* + * Since the IBS state is swap type C, the hypervisor is responsible for + * restoring its own IBS state after VMEXIT. + */ +static void svm_restore_host_ibs_msrs(struct vmcb_save_area *hostsa) +{ + wrmsrl(MSR_AMD64_IBSFETCHLINAD, hostsa->ibs_fetch_linear_addr); + wrmsrl(MSR_AMD64_IBSOPRIP, hostsa->ibs_op_rip); + wrmsrl(MSR_AMD64_IBSOPDATA, hostsa->ibs_op_data); + wrmsrl(MSR_AMD64_IBSOPDATA2, hostsa->ibs_op_data2); + wrmsrl(MSR_AMD64_IBSOPDATA3, hostsa->ibs_op_data3); + wrmsrl(MSR_AMD64_IBSDCLINAD, hostsa->ibs_dc_linear_addr); + wrmsrl(MSR_AMD64_IBSBRTARGET, hostsa->ibs_br_target); + wrmsrl(MSR_AMD64_ICIBSEXTDCTL, hostsa->ibs_fetch_extd_ctl); +} + +/* + * Host states are categorized into three swap types based on how it is + * handled by hardware during a switch. + * Below enum represent host states which are categorized as Swap type C + * + * C: VMRUN: Host state _NOT_ saved in host save area + * VMEXIT: Host state initializard to default values. + * + * Swap type C state is not loaded by VMEXIT and is not saved by VMRUN. + * It needs to be saved/restored manually. + */ +enum { + SWAP_TYPE_C_IBS = 0, + SWAP_TYPE_C_MAX +}; + +/* + * Since IBS state is swap type C, hypervisor needs to disable IBS, then save + * IBS MSRs before VMRUN and re-enable it, then restore IBS MSRs after VMEXIT. + * This order is important, if not followed, software ends up reading inaccurate + * IBS registers. + */ +static noinstr u32 svm_save_swap_type_c(struct kvm_vcpu *vcpu) +{ + struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu); + struct vmcb_save_area *hostsa; + u32 restore_mask = 0; + + hostsa = (struct vmcb_save_area *)(page_address(sd->save_area) + 0x400); + + if (to_svm(vcpu)->ibs_enabled) { + bool en = amd_vibs_window(WINDOW_START, &hostsa->ibs_fetch_ctl, &hostsa->ibs_op_ctl); + + if (en) { + svm_save_host_ibs_msrs(hostsa); + restore_mask |= 1 << SWAP_TYPE_C_IBS; + } + } + return restore_mask; +} + +static noinstr void svm_restore_swap_type_c(struct kvm_vcpu *vcpu, u32 restore_mask) +{ + struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu); + struct vmcb_save_area *hostsa; + + hostsa = (struct vmcb_save_area *)(page_address(sd->save_area) + 0x400); + + if (restore_mask & (1 << SWAP_TYPE_C_IBS)) { + svm_restore_host_ibs_msrs(hostsa); + amd_vibs_window(WINDOW_STOPPING, &hostsa->ibs_fetch_ctl, &hostsa->ibs_op_ctl); + } +} + static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted) { struct vcpu_svm *svm = to_svm(vcpu); + u32 restore_mask; guest_state_enter_irqoff(); amd_clear_divider(); - if (sev_es_guest(vcpu->kvm)) + if (sev_es_guest(vcpu->kvm)) { __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted); - else + } else { + restore_mask = svm_save_swap_type_c(vcpu); __svm_vcpu_run(svm, spec_ctrl_intercepted); + if (restore_mask) + svm_restore_swap_type_c(vcpu, restore_mask); + } + guest_state_exit_irqoff(); } @@ -4137,6 +4291,13 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) /* Any pending NMI will happen here */ + /* + * Disable the IBS window since any pending IBS NMIs will have been + * handled. + */ + if (svm->ibs_enabled) + amd_vibs_window(WINDOW_STOPPED, NULL, NULL); + if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI)) kvm_after_interrupt(vcpu); @@ -5225,6 +5386,13 @@ static __init int svm_hardware_setup(void) pr_info("LBR virtualization supported\n"); } + if (vibs) { + if ((vnmi || avic) && boot_cpu_has(X86_FEATURE_VIBS)) + pr_info("IBS virtualization supported\n"); + else + vibs = false; + } + if (!enable_pmu) pr_info("PMU virtualization is disabled\n"); diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index c7eb82a78127..c2a02629a1d1 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -30,7 +30,7 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 46 +#define MAX_DIRECT_ACCESS_MSRS 62 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; @@ -260,6 +260,7 @@ struct vcpu_svm { unsigned long soft_int_old_rip; unsigned long soft_int_next_rip; bool soft_int_injected; + bool ibs_enabled; u32 ldr_reg; u32 dfr_reg; @@ -732,6 +733,7 @@ void sev_es_vcpu_reset(struct vcpu_svm *svm); void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); void sev_es_prepare_switch_to_guest(struct sev_es_save_area *hostsa); void sev_es_unmap_ghcb(struct vcpu_svm *svm); +void svm_ibs_msr_interception(struct vcpu_svm *svm, bool intercept); /* vmenter.S */ From patchwork Mon Sep 4 09:53:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D245CA0FF6 for ; Mon, 4 Sep 2023 09:57:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238554AbjIDJ5g (ORCPT ); Mon, 4 Sep 2023 05:57:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238846AbjIDJ5e (ORCPT ); Mon, 4 Sep 2023 05:57:34 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on20621.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5b::621]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41747126; 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Presence of the VIBS feature for SEV-ES guests is indicated via CPUID function 0x8000001F_EAX[19]. Signed-off-by: Manali Shukla --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 8f92fa6d8319..022ccee197e2 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -439,6 +439,7 @@ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +#define X86_FEATURE_SEV_ES_VIBS (19*32+19) /* "" IBS virtualization for SEV-ES guests */ /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */ From patchwork Mon Sep 4 09:53:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F8CEC83F3F for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:14.5795 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87fea6c2-763e-4e6d-ef1e-08dbad2d50f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5182 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since the IBS state is swap type C, the hypervisor is responsible for saving its own IBS state before VMRUN and restoring it after VMEXIT. It is also responsible for disabling IBS before VMRUN and re-enabling it after VMEXIT. For a SEV-ES guest with IBS virtualization enabled, a VMEXIT_INVALID will happen if IBS is found to be enabled on VMRUN [1]. The IBS virtualization feature for SEV-ES guests is not enabled in this patch. Later patches enable IBS virtualization for SEV-ES guests. [1]: https://bugzilla.kernel.org/attachment.cgi?id=304653 AMD64 Architecture Programmer’s Manual, Vol 2, Section 15.38 Instruction-Based Sampling Virtualization. Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 14 +++++++++++++- arch/x86/kvm/svm/sev.c | 7 +++++++ arch/x86/kvm/svm/svm.c | 11 +++++------ 3 files changed, 25 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 4096d2f68770..58b60842a3b7 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -469,6 +469,18 @@ struct sev_es_save_area { u8 fpreg_x87[80]; u8 fpreg_xmm[256]; u8 fpreg_ymm[256]; + u8 lbr_stack_from_to[256]; + u64 lbr_select; + u64 ibs_fetch_ctl; + u64 ibs_fetch_linear_addr; + u64 ibs_op_ctl; + u64 ibs_op_rip; + u64 ibs_op_data; + u64 ibs_op_data2; + u64 ibs_op_data3; + u64 ibs_dc_linear_addr; + u64 ibs_br_target; + u64 ibs_fetch_extd_ctl; } __packed; struct ghcb_save_area { @@ -527,7 +539,7 @@ struct ghcb { #define EXPECTED_VMCB_SAVE_AREA_SIZE 1992 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 -#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648 +#define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1992 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024 #define EXPECTED_GHCB_SIZE PAGE_SIZE diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index d3aec1f2cad2..41706335cedd 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -59,6 +59,7 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ +static bool sev_es_vibs_enabled; static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -2256,6 +2257,9 @@ void __init sev_hardware_setup(void) sev_enabled = sev_supported; sev_es_enabled = sev_es_supported; + + if (!sev_es_enabled || !cpu_feature_enabled(X86_FEATURE_SEV_ES_VIBS)) + sev_es_vibs_enabled = false; #endif } @@ -2993,6 +2997,9 @@ static void sev_es_init_vmcb(struct vcpu_svm *svm) if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_RDTSCP)) svm_clr_intercept(svm, INTERCEPT_RDTSCP); } + + if (sev_es_vibs_enabled && svm->ibs_enabled) + svm_ibs_msr_interception(svm, false); } void sev_init_vmcb(struct vcpu_svm *svm) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 6f566ed93f4c..0cfe23bb144a 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4194,16 +4194,15 @@ static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_in guest_state_enter_irqoff(); amd_clear_divider(); + restore_mask = svm_save_swap_type_c(vcpu); - if (sev_es_guest(vcpu->kvm)) { + if (sev_es_guest(vcpu->kvm)) __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted); - } else { - restore_mask = svm_save_swap_type_c(vcpu); + else __svm_vcpu_run(svm, spec_ctrl_intercepted); - if (restore_mask) - svm_restore_swap_type_c(vcpu, restore_mask); - } + if (restore_mask) + svm_restore_swap_type_c(vcpu, restore_mask); guest_state_exit_irqoff(); } From patchwork Mon Sep 4 09:53:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21967CA0FE3 for ; Mon, 4 Sep 2023 09:57:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240573AbjIDJ5n (ORCPT ); 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Mon, 4 Sep 2023 04:57:14 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 12/13] KVM: SVM: Enable IBS virtualization on non SEV-ES and SEV-ES guests Date: Mon, 4 Sep 2023 09:53:46 +0000 Message-ID: <20230904095347.14994-13-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|CY8PR12MB7241:EE_ X-MS-Office365-Filtering-Correlation-Id: e1a08aed-07f1-447c-03a1-08dbad2d56f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2sU+ZX3KEd8Gpt7SlJ9mN5DMnV91QAuI7Ll+JofA7tZzmnmrS3IhpUu8DOoA+tEneAac/8wuaYYb9zA4irynCna6yK4ebVM7a6KGBmRLqdr0PMqlsGX/4wZ9U0ReXUbepInX99NCy+MR2a7k8az4G11ODobiaGlyVxkAGuX84sFypoUv2E8JXs1i38iv++gxT0ddiOjvyWLtkmBj/XRTZBMLlQf548LgFe7J5S2M2ZFnON4pVPM3+kWMLuAQTmxFB9Iay/9h0HyfHXUWCcU6NNP7CuGjgtG4PwpM7zlvbJxpHX7wrmM6Fp5efZephHtCPAvBM/XklWMk8dbcOU8EMlcvwroJ2cqS4D8OZesXmj8zQQYIXNE/i8+julfNQInoXBxJSQdAhV+Xg/5uc1SylftayLILXOXok9jEo7/PSLnCe1IWEDfvKXRmygG4bj/Bv9pZVtumZHIJ+bNgrNlhnQZGGjDryt1EloSQa9JRepTY+qBMPj+k7334x1DB9VzbGavQbBog4rrpPhgrEq18LhnELwJNorh0E3CmZrKpMuh15nrmf5NZBHFRljsR6ENABXB+0aoZoCdVc8HqfNCGS0D6HKsxSRGHfs/v+SBJ6IgrGotKiIcnrqcKiaChnpnlKmkRMjuFSvOJ7pIgXJ0vthZRQu0eglMFYmD/qhqYpq5UeuR0wvrtunr9ZxYIIk2loIj6+YeaxSc0e+MtrCsD/WDSBMuiIh1WuoVM9GHUylbCnrPys/i8GJcyQ7121gx1zTex++JwYPtXIGS2UBK66A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(136003)(39860400002)(346002)(451199024)(1800799009)(186009)(82310400011)(36840700001)(46966006)(40470700004)(16526019)(26005)(44832011)(426003)(336012)(40480700001)(6666004)(8936002)(8676002)(4326008)(36860700001)(47076005)(2616005)(83380400001)(5660300002)(1076003)(7696005)(41300700001)(40460700003)(110136005)(478600001)(70586007)(70206006)(86362001)(316002)(54906003)(356005)(82740400003)(36756003)(2906002)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:24.6503 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1a08aed-07f1-447c-03a1-08dbad2d56f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7241 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To enable IBS virtualization capability on non SEV-ES guests, bit 2 at offset 0xb8 in VMCB is set to 1 for non SEV-ES guests. To enable IBS virtualization capability on SEV-ES guests, bit 12 in SEV_FEATURES in VMSA is set to 1 for SEV-ES guests. Signed-off-by: Manali Shukla --- arch/x86/include/asm/svm.h | 4 ++++ arch/x86/kvm/svm/sev.c | 5 ++++- arch/x86/kvm/svm/svm.c | 26 +++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 58b60842a3b7..a31bf803b993 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -215,6 +215,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define LBR_CTL_ENABLE_MASK BIT_ULL(0) #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1) +#define VIRTUAL_IBS_ENABLE_MASK BIT_ULL(2) + #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0) #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1) @@ -259,6 +261,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL +#define SVM_SEV_ES_FEAT_VIBS BIT(12) + #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 41706335cedd..e0ef3a2323d6 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -59,7 +59,7 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ -static bool sev_es_vibs_enabled; +static bool sev_es_vibs_enabled = true; static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -607,6 +607,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->xss = svm->vcpu.arch.ia32_xss; save->dr6 = svm->vcpu.arch.dr6; + if (svm->ibs_enabled && sev_es_vibs_enabled) + save->sev_features |= SVM_SEV_ES_FEAT_VIBS; + pr_debug("Virtual Machine Save Area (VMSA):\n"); print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, save, sizeof(*save), false); diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 0cfe23bb144a..b85120f0d3ac 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -234,7 +234,7 @@ static int lbrv = true; module_param(lbrv, int, 0444); /* enable/disable IBS virtualization */ -static int vibs; +static int vibs = true; module_param(vibs, int, 0444); static int tsc_scaling = true; @@ -1245,10 +1245,13 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) /* * If hardware supports VIBS then no need to intercept IBS MSRS * when VIBS is enabled in guest. + * + * Enable VIBS by setting bit 2 at offset 0xb8 in VMCB. */ if (vibs) { if (guest_cpuid_has(&svm->vcpu, X86_FEATURE_IBS)) { svm_ibs_msr_interception(svm, false); + svm->vmcb->control.virt_ext |= VIRTUAL_IBS_ENABLE_MASK; svm->ibs_enabled = true; /* @@ -5166,6 +5169,24 @@ static __init void svm_adjust_mmio_mask(void) kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK); } +static void svm_ibs_set_cpu_caps(void) +{ + kvm_cpu_cap_set(X86_FEATURE_IBS); + kvm_cpu_cap_set(X86_FEATURE_EXTLVT); + kvm_cpu_cap_set(X86_FEATURE_EXTAPIC); + kvm_cpu_cap_set(X86_FEATURE_IBS_AVAIL); + kvm_cpu_cap_set(X86_FEATURE_IBS_FETCHSAM); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPSAM); + kvm_cpu_cap_set(X86_FEATURE_IBS_RDWROPCNT); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPCNT); + kvm_cpu_cap_set(X86_FEATURE_IBS_BRNTRGT); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPCNTEXT); + kvm_cpu_cap_set(X86_FEATURE_IBS_RIPINVALIDCHK); + kvm_cpu_cap_set(X86_FEATURE_IBS_OPBRNFUSE); + kvm_cpu_cap_set(X86_FEATURE_IBS_FETCHCTLEXTD); + kvm_cpu_cap_set(X86_FEATURE_IBS_ZEN4_EXT); +} + static __init void svm_set_cpu_caps(void) { kvm_set_cpu_caps(); @@ -5208,6 +5229,9 @@ static __init void svm_set_cpu_caps(void) kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK); } + if (vibs) + svm_ibs_set_cpu_caps(); + /* CPUID 0x80000008 */ if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) || boot_cpu_has(X86_FEATURE_AMD_SSBD)) From patchwork Mon Sep 4 09:53:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13373690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5447CA0FF3 for ; Mon, 4 Sep 2023 09:57:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345328AbjIDJ5w (ORCPT ); Mon, 4 Sep 2023 05:57:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243886AbjIDJ5u (ORCPT ); Mon, 4 Sep 2023 05:57:50 -0400 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2088.outbound.protection.outlook.com [40.107.92.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B436CDD; 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Mon, 4 Sep 2023 09:57:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343C.mail.protection.outlook.com (10.167.18.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Mon, 4 Sep 2023 09:57:33 +0000 Received: from brahmaputra.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 4 Sep 2023 04:57:24 -0500 From: Manali Shukla To: , CC: , , , , , , , , , , Subject: [PATCH 13/13] KVM: x86: nSVM: Implement support for nested IBS virtualization Date: Mon, 4 Sep 2023 09:53:47 +0000 Message-ID: <20230904095347.14994-14-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230904095347.14994-1-manali.shukla@amd.com> References: <20230904095347.14994-1-manali.shukla@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|CH2PR12MB4135:EE_ X-MS-Office365-Filtering-Correlation-Id: 3edf4798-f9f6-483a-041c-08dbad2d5c3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2023 09:57:33.4846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3edf4798-f9f6-483a-041c-08dbad2d5c3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4135 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org To handle the case where IBS is enabled for L1 and L2, IBS MSRs are copied from vmcb12 to vmcb02 during vmentry and vice-versa during vmexit. To handle the case where IBS is enabled for L1 but _not_ for L2, IBS MSRs are copied from vmcb01 to vmcb02 during vmentry and vice-versa during vmexit. Signed-off-by: Manali Shukla --- arch/x86/kvm/governed_features.h | 1 + arch/x86/kvm/svm/nested.c | 23 +++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 18 ++++++++++++++++++ arch/x86/kvm/svm/svm.h | 1 + 4 files changed, 43 insertions(+) diff --git a/arch/x86/kvm/governed_features.h b/arch/x86/kvm/governed_features.h index 423a73395c10..101c819f3876 100644 --- a/arch/x86/kvm/governed_features.h +++ b/arch/x86/kvm/governed_features.h @@ -16,6 +16,7 @@ KVM_GOVERNED_X86_FEATURE(PAUSEFILTER) KVM_GOVERNED_X86_FEATURE(PFTHRESHOLD) KVM_GOVERNED_X86_FEATURE(VGIF) KVM_GOVERNED_X86_FEATURE(VNMI) +KVM_GOVERNED_X86_FEATURE(VIBS) #undef KVM_GOVERNED_X86_FEATURE #undef KVM_GOVERNED_FEATURE diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index dd496c9e5f91..a1bb32779b3e 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -616,6 +616,16 @@ static void nested_vmcb02_prepare_save(struct vcpu_svm *svm, struct vmcb *vmcb12 } else if (unlikely(vmcb01->control.virt_ext & LBR_CTL_ENABLE_MASK)) { svm_copy_lbrs(vmcb02, vmcb01); } + + if (guest_can_use(vcpu, X86_FEATURE_VIBS) && + !(vmcb12->control.virt_ext & VIRTUAL_IBS_ENABLE_MASK)) + vmcb02->control.virt_ext = vmcb12->control.virt_ext & ~VIRTUAL_IBS_ENABLE_MASK; + + if (unlikely(guest_can_use(vcpu, X86_FEATURE_VIBS) && + (svm->nested.ctl.virt_ext & VIRTUAL_IBS_ENABLE_MASK))) + svm_copy_ibs(vmcb02, vmcb12); + else if (unlikely(vmcb01->control.virt_ext & VIRTUAL_IBS_ENABLE_MASK)) + svm_copy_ibs(vmcb02, vmcb01); } static inline bool is_evtinj_soft(u32 evtinj) @@ -741,6 +751,13 @@ static void nested_vmcb02_prepare_control(struct vcpu_svm *svm, vmcb02->control.virt_ext |= (svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK); + vmcb02->control.virt_ext = vmcb01->control.virt_ext & VIRTUAL_IBS_ENABLE_MASK; + + if (guest_can_use(vcpu, X86_FEATURE_VIBS)) + vmcb02->control.virt_ext |= (svm->nested.ctl.virt_ext & VIRTUAL_IBS_ENABLE_MASK); + else + vmcb02->control.virt_ext &= ~VIRTUAL_IBS_ENABLE_MASK; + if (!nested_vmcb_needs_vls_intercept(svm)) vmcb02->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK; @@ -1083,6 +1100,12 @@ int nested_svm_vmexit(struct vcpu_svm *svm) svm_update_lbrv(vcpu); } + if (unlikely(guest_can_use(vcpu, X86_FEATURE_VIBS) && + (svm->nested.ctl.virt_ext & VIRTUAL_IBS_ENABLE_MASK))) + svm_copy_ibs(vmcb12, vmcb02); + else if (unlikely(vmcb01->control.virt_ext & VIRTUAL_IBS_ENABLE_MASK)) + svm_copy_ibs(vmcb01, vmcb02); + if (vnmi) { if (vmcb02->control.int_ctl & V_NMI_BLOCKING_MASK) vmcb01->control.int_ctl |= V_NMI_BLOCKING_MASK; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index b85120f0d3ac..7925bfa0b4ce 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1084,6 +1084,20 @@ void svm_ibs_msr_interception(struct vcpu_svm *svm, bool intercept) set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_ICIBSEXTDCTL, !intercept, !intercept); } +void svm_copy_ibs(struct vmcb *to_vmcb, struct vmcb *from_vmcb) +{ + to_vmcb->save.ibs_fetch_ctl = from_vmcb->save.ibs_fetch_ctl; + to_vmcb->save.ibs_fetch_linear_addr = from_vmcb->save.ibs_fetch_linear_addr; + to_vmcb->save.ibs_op_ctl = from_vmcb->save.ibs_op_ctl; + to_vmcb->save.ibs_op_rip = from_vmcb->save.ibs_op_rip; + to_vmcb->save.ibs_op_data = from_vmcb->save.ibs_op_data; + to_vmcb->save.ibs_op_data2 = from_vmcb->save.ibs_op_data2; + to_vmcb->save.ibs_op_data3 = from_vmcb->save.ibs_op_data3; + to_vmcb->save.ibs_dc_linear_addr = from_vmcb->save.ibs_dc_linear_addr; + to_vmcb->save.ibs_br_target = from_vmcb->save.ibs_br_target; + to_vmcb->save.ibs_fetch_extd_ctl = from_vmcb->save.ibs_fetch_extd_ctl; +} + static void grow_ple_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm = to_svm(vcpu); @@ -4441,6 +4455,7 @@ static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_PFTHRESHOLD); kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VGIF); kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VNMI); + kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VIBS); svm_recalc_instruction_intercepts(vcpu, svm); @@ -5225,6 +5240,9 @@ static __init void svm_set_cpu_caps(void) if (vnmi) kvm_cpu_cap_set(X86_FEATURE_VNMI); + if (vibs) + kvm_cpu_cap_set(X86_FEATURE_VIBS); + /* Nested VM can receive #VMEXIT instead of triggering #GP */ kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK); } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index c2a02629a1d1..f607dc690d94 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -584,6 +584,7 @@ void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm); void svm_vcpu_free_msrpm(u32 *msrpm); void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); void svm_update_lbrv(struct kvm_vcpu *vcpu); +void svm_copy_ibs(struct vmcb *to_vmcb, struct vmcb *from_vmcb); int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);