From patchwork Tue Sep 5 10:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13374424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E690C83F33 for ; Tue, 5 Sep 2023 10:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jMe331K6daOOJd+96RPU8unvMOd7MebtuGmyYBLvHs8=; b=vabx+GStMa2TKZ LC4lj/z+kxgeWb7YgqGt/M9i9Dtdun9dt6OeUhUuW3YiVjPhy9MexNSXF83mp+waLQoLQHm01gVgS C+viUOTM7n1QSMX6cwBTCqWY6G5GOkrEK+gkqebreNZuW+cQWoKFuYkM98WKiWpeUnvRI1V6jR3fs qm6x0c27vJpozloSl1fxJu679ZVgQj4Dtff+V51YfUG0Wa1iniuTDXmq2zkoTOhqvf9SRD+KFJuhc vhvw8zc9zkm+dCqEsew4QndvATkB2r5CPGEGs73cduHfocCnTXoBhrjVN8FerSI51L/Lb5suAxb2c p8z7LH6eBtWufduaZ77w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdTap-005qxc-2F; Tue, 05 Sep 2023 10:47:35 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qdTan-005qwq-0H for linux-arm-kernel@lists.infradead.org; Tue, 05 Sep 2023 10:47:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9D2796068A; Tue, 5 Sep 2023 10:47:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9F996C433C8; Tue, 5 Sep 2023 10:47:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910852; bh=rwu/ICLddZviRmw2ibPmYNuYJYieVb9gj5s0F4BZk2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PrektR0OvmkeZ5I62+XN2ZIEywqRUsADhv8DRXcKFRY3TThydbyXNpJNtEQTDhLR6 7cTVGugCfDArcKjy3J27sspy6ipEILeBNKTHDJBBXyl+vfB2ET+qnVdZgfXJKjtj5d rr5/JKUI2zujSKXAXAGp+sYXMqZT78CuCGItBfb2S5i8U+XT9OpAv3Tz7GvKvy9+0f wFEVU+/eX7FWDAMZE+0pmvcMm4NRagPiMcyilymVkbgUjm24ithPCw+zh9ppw59ZrR gcpUbwIDD55dqVJJ7vonbA9mDBrQZsz3VR1N8ba1JPe6Jm1vsk/Sa0ZNUsHzxXBEDI 2E7i3zzRy1y4A== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Robin Murphy , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property Date: Tue, 5 Sep 2023 12:47:20 +0200 Message-Id: <20230905104721.52199-2-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_034733_164875_B8FEDF6F X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent. Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU. Signed-off-by: Lorenzo Pieralisi Cc: Rob Herring --- .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 39e64c7f6360..0a81ae4519a6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -106,6 +106,10 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 4096 + dma-noncoherent: + description: | + Present if the GIC redistributors are not cache coherent with the CPU. + msi-controller: description: Only present if the Message Based Interrupt functionality is @@ -193,6 +197,10 @@ patternProperties: compatible: const: arm,gic-v3-its + dma-noncoherent: + description: | + Present if the GIC ITS is not cache coherent with the CPU. + msi-controller: true "#msi-cells": From patchwork Tue Sep 5 10:47:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13374425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC52CC83F33 for ; Tue, 5 Sep 2023 10:48:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2IOLoxzcHqfZ6V7oW9n2IgPjzV/BGQhD/zNCtUh4mI0=; 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Tue, 5 Sep 2023 10:47:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AA8C433A9; Tue, 5 Sep 2023 10:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910855; bh=be3LTeFm799ZIVXUkbKCDmqLg5EZsxWtrrfYzGafTQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kn2eZZwyL2WrmDC9u1LV85D4PdFEhtw9KkxYls2VcOJ2Yo5YjFuIJlGgulxVuvPra wUc6CkhPD1ZV7DFJe348R2JAET0zkHfPX6h3CS/rx2IC54DEuvPd1Q5wHPFgF3rNo9 hC7IQr88u5L6Cz5LXpYaTnvBueqMQTWjTFPrtEEElSUmNeTdF8cP72MVF8ddZoPBo4 mvYv8Yor76j11jo4Jb13UrqWUyHpfvFSX3Ew5YJu/ryRtvi9X9z+SXOCJfzDrLFfvY 98WKpVK0lpoX6BgwGDci2DWb2UkybEtadDt8A21tDQnvYxmzyjGQeAFTqv20f0fwe1 whP6SGZ3DfxDA== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Robin Murphy , Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Fang Xiang Subject: [PATCH 2/2] irqchip/gic-v3: Enable non-coherent redistributors/ITSes probing Date: Tue, 5 Sep 2023 12:47:21 +0200 Message-Id: <20230905104721.52199-3-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_034737_660735_2ED4FBDF X-CRM114-Status: GOOD ( 20.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The GIC architecture specification defines a set of registers for redistributors and ITSes that control the sharebility and cacheability attributes of redistributors/ITSes initiator ports on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER, GITS_BASER). Architecturally the GIC provides a means to drive shareability and cacheability attributes signals and related IWB/OWB/ISH barriers but it is not mandatory for designs to wire up the corresponding interconnect signals that control the cacheability/shareability of transactions. Redistributors and ITSes interconnect ports can be connected to non-coherent interconnects that are not able to manage the shareability/cacheability attributes; this implicitly makes the redistributors and ITSes non-coherent observers. So far, the GIC driver on probe executes a write to "probe" for the redistributors and ITSes registers shareability bitfields by writing a value (ie InnerShareable - the shareability domain the CPUs are in) and check it back to detect whether the value sticks or not; this hinges on a GIC programming model behaviour that predates the current specifications, that just define shareability bits as writeable but do not guarantee that writing certain shareability values enable the expected behaviour for the redistributors/ITSes memory interconnect ports. To enable non-coherent GIC designs, introduce the "dma-noncoherent" device tree property to allow firmware to describe redistributors and ITSes as non-coherent observers on the memory interconnect and use the property to force the shareability attributes to be programmed into the redistributors and ITSes registers. Signed-off-by: Lorenzo Pieralisi Cc: Robin Murphy Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e0c2b10d154d..758ea3092305 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -5056,7 +5056,8 @@ static int __init its_compute_its_list_map(struct resource *res, } static int __init its_probe_one(struct resource *res, - struct fwnode_handle *handle, int numa_node) + struct fwnode_handle *handle, int numa_node, + bool non_coherent) { struct its_node *its; void __iomem *its_base; @@ -5148,7 +5149,7 @@ static int __init its_probe_one(struct resource *res, gits_write_cbaser(baser, its->base + GITS_CBASER); tmp = gits_read_cbaser(its->base + GITS_CBASER); - if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE || non_coherent) tmp &= ~GITS_CBASER_SHAREABILITY_MASK; if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { @@ -5356,11 +5357,19 @@ static const struct of_device_id its_device_id[] = { {}, }; +static void of_check_rdists_coherent(struct device_node *node) +{ + if (of_property_read_bool(node, "dma-noncoherent")) + gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; +} + static int __init its_of_probe(struct device_node *node) { struct device_node *np; struct resource res; + of_check_rdists_coherent(node); + /* * Make sure *all* the ITS are reset before we probe any, as * they may be sharing memory. If any of the ITS fails to @@ -5396,7 +5405,8 @@ static int __init its_of_probe(struct device_node *node) continue; } - its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); + its_probe_one(&res, &np->fwnode, of_node_to_nid(np), + of_property_read_bool(np, "dma-noncoherent")); } return 0; } @@ -5533,7 +5543,8 @@ static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, } err = its_probe_one(&res, dom_handle, - acpi_get_its_numa_node(its_entry->translation_id)); + acpi_get_its_numa_node(its_entry->translation_id), + false); if (!err) return 0; From patchwork Fri Oct 6 12:59:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 13411459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A477E81DF7 for ; Fri, 6 Oct 2023 13:00:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zDSwsPby5/d/4xEKYM0ZvDkokmmddr/XUgBCJnnND4g=; b=s/DC0EGnPs6Anf w9ESrR5z9+6t90WxYT7/85W7LUBDm7UWOVYnXaYIH0Gqq3vuAZrzL4ib7TLZkF/i2At/zzcuiXQox ibwNBQaxNGKvOMY8ECCk4qW2+tV2sJHNzY01IAdDbic14MhxJUlSyEOAP7boyDTos0wGehGNeHHLi i1k4zbC6nJXKLttPN72OTfpi/rxT4MScdf9I908tVJ4WpIhe6fLPwE9uhK+95Wh/8qSvvhgtePHRy T/OVPQqEoMftAOBHn3eq1RGTQRRWE0fpW7tFK4t9sAIfkBHCkdTyziDp5XDjlNrhLql2yUn7cxegz FyqH8VQBkP+Audol7zEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qokQt-005po7-2n; Fri, 06 Oct 2023 12:59:55 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qokQq-005pmH-1j for linux-arm-kernel@lists.infradead.org; Fri, 06 Oct 2023 12:59:54 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 1F1C9B82944; Fri, 6 Oct 2023 12:59:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED31BC43395; Fri, 6 Oct 2023 12:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696597190; bh=1a0WYm/JOuoSloUtHO8rcUYP3nlPMtWwDXeoC9j17ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cxuu05QZS2zUIu3FMQpOk4GTxl5etLU3bdmcRa3X9ASqNJV8AQNtb+4cuNWzOCliJ J2kW9cevvgvHxvm2JEB1uR6HDj9cA+D79ZTTMcgylFpaflS9XKt6xPHUksQQphUpP0 YeHTCWvV3aju5DnJZ2jNvxYEYgOaD2jdZ9W+3V2X/HAD7oPblNqmPPCb7BGc2Nq2u4 ba7IrcEIp9aWoA5984O5Nc/ztL1bY609fWg0t+ncvT2vx/dDSQSxyw8E4xW0A3me35 U1zkddfi/3nPuZ/8AKxXknVUuYFpbKzZwt3shyb3JEomgv03yPXktZQ5NywNA5Ef9H vmENa5OnxIeIg== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, Mark Rutland , Robin Murphy , "Rafael J. Wysocki" , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH v3 4/5] ACPICA: Add new MADT GICC/GICR/ITS flags handling [code first] Date: Fri, 6 Oct 2023 14:59:28 +0200 Message-Id: <20231006125929.48591-5-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231006125929.48591-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> <20231006125929.48591-1-lpieralisi@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231006_055952_721545_4A94EE10 X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add new flags and related fields to the MADT GICC/GICR/ITS structures according to the code first ECR: https://bugzilla.tianocore.org/show_bug.cgi?id=4557 Temporary code waiting for ECR approval, for testing purpose only - eventually ACPICA changes will trickle into the kernel from the ACPICA project repos. Signed-off-by: Lorenzo Pieralisi --- include/acpi/actbl2.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 3751ae69432f..dd44915efd6b 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1046,6 +1046,7 @@ struct acpi_madt_generic_interrupt { /* ACPI_MADT_ENABLED (1) Processor is usable if set */ #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ +#define ACPI_MADT_GICC_NON_COHERENT (1<<4) /* 04: GIC redistributor is not coherent */ /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */ @@ -1090,21 +1091,27 @@ struct acpi_madt_generic_msi_frame { struct acpi_madt_generic_redistributor { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u64 base_address; u32 length; }; +#define ACPI_MADT_GICR_NON_COHERENT (1) + /* 15: Generic Translator (ACPI 6.0) */ struct acpi_madt_generic_translator { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u32 translation_id; u64 base_address; u32 reserved2; }; +#define ACPI_MADT_ITS_NON_COHERENT (1) + /* 16: Multiprocessor wakeup (ACPI 6.4) */ struct acpi_madt_multiproc_wakeup {