From patchwork Wed Sep 6 04:56:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C858DEB8FB6 for ; Wed, 6 Sep 2023 04:56:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236143AbjIFE46 (ORCPT ); Wed, 6 Sep 2023 00:56:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbjIFE45 (ORCPT ); Wed, 6 Sep 2023 00:56:57 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D50ACF0; Tue, 5 Sep 2023 21:56:54 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3864hEZf020480; Wed, 6 Sep 2023 04:56:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=5n78TaTJXbkfJXLsE5b9vdcW/bufP7nkgOT8yyBSnHE=; b=iDJV2xWREZGeF7mY0qFJB9m4F1GJ+NsEnoGDXdar4Tc6Ee2mgKqwklm4n02OC4oLQeCh iMvY4E1H5q6eeqQAq/lJSY+cFaNoMLhPhrZaJLQDHqtrbxYn9ViwosJCL9D52FmUjOtN zyyF9dJ1zkwfeKpmPwpAcjasVR+J2r/eUt8LzijutXrGIkwgcr/G+gXBuYDBBaZtLJnB gStetUPR4N49NwG5K9zSuVHR9GYVX+yFU6zA5jXplyWPZNsOOxXc810uXh9GvefnsURh wk7mPnC0DJc2Ck7vyl31BLP+OzPmx7lwYPu0odWKDWVYML00HyzQtmqa4aSgUQvVW1cB ZQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3sxhbhg5bd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Sep 2023 04:56:41 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3864uetC028344 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Sep 2023 04:56:40 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 5 Sep 2023 21:56:35 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:20 +0530 Subject: [PATCH RESEND 1/7] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-1-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=2148; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=qvuYyxdgwV2e5dg+1E6zI3CEXOMdRXBeCrT9bL9F1Gc=; b=84wky6jD8MqptiQeo/8qh/nf4Kq0N16Hi/oHxVaqE/ttiRsw3naRab/DSdTDo3zM0Rzsda1Uq GHDjH0E6xAaDjbnCvffVLOsR6dTqQqvHTU4WRGkDiBb2iYAhSGZ8syR X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ytNHjedIAe3rZng8FuPvgr3CFh3_g3SG X-Proofpoint-ORIG-GUID: ytNHjedIAe3rZng8FuPvgr3CFh3_g3SG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-05_13,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=938 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309060044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GPLL, UBI32 PLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq8074.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 63ac2ced76bb..cfe2f2606cfe 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -75,7 +75,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -121,7 +120,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -154,7 +152,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -188,7 +185,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -201,7 +197,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -234,7 +229,6 @@ static struct clk_alpha_pll_postdiv ubi32_pll = { &ubi32_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -266,7 +260,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Wed Sep 6 04:56:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E4ABEB8FB5 for ; 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Tue, 5 Sep 2023 21:56:40 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:21 +0530 Subject: [PATCH RESEND 2/7] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-2-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=2158; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=HVjEqzCxHlgD0fXslB0uy/S3ENoNzNcmNC724Whk4mM=; b=1vX+cnkV5VpYAkdPhvurtQ7cRw67isA44GDXxcKhFJX4LO6uWUhw0NZbLemyAYaZ6C6oFIIye vKA48rPvyqhBUrtNhjdB9LPxNtHnu9qQbbujB+hl362dq8+0Q06oZnS X-Developer-Key: i=quic_kathirav@quicinc.com; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq6018.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 6120fbbc5de0..d6be70538566 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -130,7 +128,6 @@ static struct clk_alpha_pll_postdiv ubi32_pll = { &ubi32_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -161,7 +158,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -192,7 +188,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -243,7 +238,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -274,7 +268,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Wed Sep 6 04:56:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52688EB8FBB for ; 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Tue, 5 Sep 2023 21:56:45 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:22 +0530 Subject: [PATCH RESEND 3/7] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-3-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=1483; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=b42j23cvzaYQJVjmla5gdsmq0HAmSms0iFKcG3hVa8s=; b=BqXviAN68GZscSRPXRGshYEwAK2zzAe3J2O4IiGyY3o8rc3hK4Abu/TSPygT1pWJ2OEWEVazX Pj4o69QM3zjDSCtxpie5oxPYfLMKi7CQkPCnJxiTM4YuVJVDsqBdawo X-Developer-Key: i=quic_kathirav@quicinc.com; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq9574.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 8f430367299e..e8190108e1ae 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, }, }; @@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; @@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; @@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; From patchwork Wed Sep 6 04:56:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 349CAEB8FB3 for ; Wed, 6 Sep 2023 04:57:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239290AbjIFE5Q (ORCPT ); Wed, 6 Sep 2023 00:57:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239361AbjIFE5Q (ORCPT ); Wed, 6 Sep 2023 00:57:16 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76D3DE5D; Tue, 5 Sep 2023 21:57:09 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3864eK4i016042; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5332.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index b02026f8549b..6c74a117ef0b 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -114,7 +114,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -154,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Wed Sep 6 04:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0A6EEB8FAD for ; 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Tue, 5 Sep 2023 21:56:55 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:24 +0530 Subject: [PATCH RESEND 5/7] dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-5-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=1019; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=cAkbsEB56Chic7kbQsVFXNcpAy3AXkFiFcYnXKfyUak=; b=4rJCJxOshwmrJUH1HvQH4HFYIBgluxewrsWD+cqFwkQkq2y/G88YT+VlpZ+Jnt2GMOfjnlTK4 Wl6gvl4NMnGD4dF0bEcLKEBqb8FR894qxkOn4seELJkqh+YweMVlPTM X-Developer-Key: i=quic_kathirav@quicinc.com; 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Document the same. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index d2e25ff6db7f..a38413f8d132 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -125,10 +125,12 @@ allOf: items: - description: primary pll parent of the clock driver - description: XO clock + - description: GCC GPLL0 clock source clock-names: items: - const: pll - const: xo + - const: gpll0 - if: properties: From patchwork Wed Sep 6 04:56:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FA5CEB8FA5 for ; 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Tue, 5 Sep 2023 21:57:00 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:25 +0530 Subject: [PATCH RESEND 6/7] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-6-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=1100; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=rzyPZph7HIrhgxkcI3wZuDYmLF+kwvjjidrlw0worEA=; b=s7Q+hj57eJoczR9xNtO/A9LBcaf3bcBhHHtlmsFX2jTgGr5CR8qcYQ4OFsByZVFKA17WMp92K Inh4phkRvAhDxZh5vq37UZOQxk40lKdeWvYuhzPihAGiZB/8AU02wE3 X-Developer-Key: i=quic_kathirav@quicinc.com; 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Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Signed-off-by: Kathiravan Thirumoorthy Tested-by: Robert Marko Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/apss-ipq6018.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c index f2f502e2d5a4..4e13a085a857 100644 --- a/drivers/clk/qcom/apss-ipq6018.c +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -20,16 +20,19 @@ enum { P_XO, + P_GPLL0, P_APSS_PLL_EARLY, }; static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { { .fw_name = "xo" }, + { .fw_name = "gpll0" }, { .fw_name = "pll" }, }; static const struct parent_map parents_apcs_alias0_clk_src_map[] = { { P_XO, 0 }, + { P_GPLL0, 4 }, { P_APSS_PLL_EARLY, 5 }, }; From patchwork Wed Sep 6 04:56:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13375264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A69F2EB8FB3 for ; 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Tue, 5 Sep 2023 21:57:04 -0700 From: Kathiravan Thirumoorthy Date: Wed, 6 Sep 2023 10:26:26 +0530 Subject: [PATCH RESEND 7/7] arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox MIME-Version: 1.0 Message-ID: <20230904-gpll_cleanup-v1-7-de2c448f1188@quicinc.com> References: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> In-Reply-To: <20230904-gpll_cleanup-v1-0-de2c448f1188@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Jassi Brar , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Michael Turquette , "Stephen Boyd" , Sricharan Ramabadhran , Anusha Rao , Devi Priya , , , , CC: Kathiravan Thirumoorthy X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1693976190; l=3211; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=shym5TfdS8PDN/wjdg2Pbcgcv3yNaESO9SmPeEzEq/A=; b=J5q+8afVvBB3JGjv+EJBTH3MaXWI8tDcTQt3W1Y5OFxip+HFUACekJqEI2ipQkfC3C8JJ4Y/o /ImJ7D6GVPMByZ+qcb05UZdGUIYBo2mJQmXqneDPilxM/wlLfQJ6Flq X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MddWxxAkFxaVRra3J-tXDj3YRlERdWy0 X-Proofpoint-GUID: MddWxxAkFxaVRra3J-tXDj3YRlERdWy0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-05_13,2023-09-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 mlxlogscore=902 impostorscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 suspectscore=0 adultscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309060044 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch between the frequencies we need to park the APSS PLL in safe source, here it is GPLL0 and then shutdown and bring up the APSS PLL in the desired rate. So this patch is preparatory one to enable the CPUFreq on IPQ5332. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..82761ae199a9 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -335,8 +335,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo_board>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 47b8b1d6730a..a30a5b893762 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -619,8 +619,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq6018-apcs-apps-global"; reg = <0x0 0x0b111000 0x0 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 00ed71936b47..0be19267bdcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -719,8 +719,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #clock-cells = <1>; #mbox-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 51aba071c1eb..89edb4b852df 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -652,8 +652,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a73pll>, <&xo_board_clk>; - clock-names = "pll", "xo"; + clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; };