From patchwork Fri Sep 8 09:53:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C3BBEE57EC for ; Fri, 8 Sep 2023 09:53:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238614AbjIHJxq (ORCPT ); Fri, 8 Sep 2023 05:53:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230475AbjIHJxp (ORCPT ); Fri, 8 Sep 2023 05:53:45 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 248171BD3; Fri, 8 Sep 2023 02:53:41 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-573d52030fbso1387183a12.0; Fri, 08 Sep 2023 02:53:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166820; x=1694771620; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qUyhKz0IZnGv/kDPhh0zvtC7NPuBSxGKLGuzvFl9j+w=; b=YaSWqxNhK2FEU7nErELA6h8mRu+WQrNa7ogsIdaoKb7FQI4mCzYRATkT5hDgYnhBZX SXCSadvmyex2KFjhLNOyh67YrTVgVxNN4e1K3Q7ps+dTGscvg53N8tH6K4953v8UKhPv FZSORH5k8q9vxSdIB4gXjZ5WXyi1rPW0RqjHwaWCUbNhHpc8DXH+sNF96PV6qaDQqEPM LiqK5Gsi+o2i4hrUvIvaClsKOy97Opc2oOtoJpQ+jwS87ZjtjyPiSnktwSjYvh0gJeAC ulZBYD50VrbvL6PioyXA6IFFvO/8Yc2skjMVb1h29Gu01YasbgsuqRA8Sj80Ri79C8vt yDzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166820; x=1694771620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qUyhKz0IZnGv/kDPhh0zvtC7NPuBSxGKLGuzvFl9j+w=; b=U5fUM9+h2z+Lw/GCL7UHM5IsU8O+3K0DM2DgALtHsAFZMaQ1Xr86Fk3rxYRk8naBD5 sNa/7gKTTfj+OnXcsyI0WZD1NqZcwP4d31jqTyN8tXgQaMk1CR/wHGMexxidlXqpmiTD scFS/D+S9zBIwcynQm9hL5JzEg2RroMmudF7zD39Oi5sMcTrTDPFFMo9Zln8SWyv3Dbs MmBhgVRnAMcgA+6AcJaxizWTma0xLvM9/e+EsFTc5iWzIDPIqy32rHekZVNzNOe875Vx lJAkeRixyGvsMt8EdREgYNhl5xgkLiq+Lw/YcPHmWM4ANrR1zMUqb37xd0bI0oWY31LA 4DxA== X-Gm-Message-State: AOJu0Yx0lvUwbhwmG0mKlYxvTEoyK+9Z5hjg82Vb8p5FwhMgiQ2jcsWO sf5Qqvu4MiXqnHcXqOX5LB0= X-Google-Smtp-Source: AGHT+IFKwp2MtaQyqprNbgxb33hojVJsHkCXZPF8d/OrgMwYIqXhWvd68rx7PIJRUw0kvXRq5Bkj7A== X-Received: by 2002:a05:6a20:7490:b0:13b:a2c9:922e with SMTP id p16-20020a056a20749000b0013ba2c9922emr2164193pzd.27.1694166820500; Fri, 08 Sep 2023 02:53:40 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:40 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V11 01/23] mmc: core: Cleanup printing of speed mode at card insertion Date: Fri, 8 Sep 2023 17:53:08 +0800 Message-Id: <20230908095330.12075-2-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ulf Hansson The current print of the bus speed mode in mmc_add_card() has grown over the years and is now difficult to parse. Let's clean up the code and also take the opportunity to properly announce "DDR" for eMMCs as "high speed DDR", which is according to the eMMC spec. Signed-off-by: Ulf Hansson --- drivers/mmc/core/bus.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index 0af96548e7da..bd761e2858f1 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -299,6 +299,7 @@ int mmc_add_card(struct mmc_card *card) { int ret; const char *type; + const char *speed_mode = ""; const char *uhs_bus_speed_mode = ""; static const char *const uhs_speeds[] = { [UHS_SDR12_BUS_SPEED] = "SDR12 ", @@ -340,27 +341,30 @@ int mmc_add_card(struct mmc_card *card) break; } + if (mmc_card_hs(card)) + speed_mode = "high speed "; + else if (mmc_card_uhs(card)) + speed_mode = "ultra high speed "; + else if (mmc_card_ddr52(card)) + speed_mode = "high speed DDR "; + else if (mmc_card_hs200(card)) + speed_mode = "HS200 "; + else if (mmc_card_hs400es(card)) + speed_mode = "HS400 Enhanced strobe "; + else if (mmc_card_hs400(card)) + speed_mode = "HS400 "; + if (mmc_card_uhs(card) && (card->sd_bus_speed < ARRAY_SIZE(uhs_speeds))) uhs_bus_speed_mode = uhs_speeds[card->sd_bus_speed]; - if (mmc_host_is_spi(card->host)) { - pr_info("%s: new %s%s%s card on SPI\n", - mmc_hostname(card->host), - mmc_card_hs(card) ? "high speed " : "", - mmc_card_ddr52(card) ? "DDR " : "", - type); - } else { - pr_info("%s: new %s%s%s%s%s%s card at address %04x\n", - mmc_hostname(card->host), - mmc_card_uhs(card) ? "ultra high speed " : - (mmc_card_hs(card) ? "high speed " : ""), - mmc_card_hs400(card) ? "HS400 " : - (mmc_card_hs200(card) ? "HS200 " : ""), - mmc_card_hs400es(card) ? "Enhanced strobe " : "", - mmc_card_ddr52(card) ? "DDR " : "", + if (mmc_host_is_spi(card->host)) + pr_info("%s: new %s%s card on SPI\n", + mmc_hostname(card->host), speed_mode, type); + else + pr_info("%s: new %s%s%s card at address %04x\n", + mmc_hostname(card->host), speed_mode, uhs_bus_speed_mode, type, card->rca); - } mmc_add_card_debugfs(card); card->dev.of_node = mmc_of_find_child_device(card->host, 0); From patchwork Fri Sep 8 09:53:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1E1FEE57EC for ; Fri, 8 Sep 2023 09:53:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242277AbjIHJxt (ORCPT ); Fri, 8 Sep 2023 05:53:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232395AbjIHJxs (ORCPT ); Fri, 8 Sep 2023 05:53:48 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07D211BD3; Fri, 8 Sep 2023 02:53:44 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-56b2e689968so1434294a12.0; Fri, 08 Sep 2023 02:53:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166823; x=1694771623; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d5smvUVRxiERvKl00R2+3TcSbZ/6CYftHFrCOmhiGBE=; b=DIMMtmq6o+Xw28xQEBteVq6HvrepDz3U7k7tKZQMFJuxPnP5ZTNfv1m3nCvE9zTGZ2 n+CJpBD/hUNiFyC0FDFsUMguar4lrn4aFMIRsFqQb6xtmK/QgwXhNigUdnFT1vCGoMON 6Ak6E1t+ayqCCMQN00FzW5V2kFVkn8WInj36B6vZ04ubHfRZ36Q70RMWWX/wo7LpEGEj 4p4WmR+aFRGODSdM4irp/s0cTQwKYcJksrZxjrgTwrVQjtkMchHlseWg2yY0MFNqKep3 +7d+i2ViJY+dhFmLMVwh/PBKqy9HZnpPFrzmcGvCo/kzM6bSrSzjJHOUMpXjOf0C6Oql /YjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166823; x=1694771623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d5smvUVRxiERvKl00R2+3TcSbZ/6CYftHFrCOmhiGBE=; b=nrQCp/7xdV2om3T5n5yHoaGiGrMLIfCT+lLNc7X7eQuxwdJ20MTbjI8qpCJv87zmNN ju31baNk+Jq2xOnA3uc6tu+UtFtQ8U/JLQ27Zli5J6leywC98EW0QB9qo5k2PYgNkSII mT8auFSu5ItAV1E7LbgRHs4Tsr+Lhfyla5WRiaoLGGoHwXCoC3dMPkJiqvBMAdEW2OWl cO/WntLt10WobqGcGaCFhEPnwuw+Gc6BDYCeuoRPE5348yX1hA7mTG6pnnrn1qcVgKj+ 967nsJgKer3+SecaddeKkU/woAxZwl3EYa2kMZ53hiF+emeXW749dg45ESncaG9KdY7N a0Kw== X-Gm-Message-State: AOJu0YyB1pAZSILklp3OYT9K96terSvPINiD8mIosHltrMeIa/khMt7H iPnvrWeGfvJzLrK7Ygycp2LshAAF2Sw= X-Google-Smtp-Source: AGHT+IFNy+opXItoNQxlcbhDvCCcuefTNZZxY2yNQSn4Oo16ROovFDcdx7ixLRjtC85Z2DiIGmYL8A== X-Received: by 2002:a05:6a20:7f81:b0:13a:ccb9:d5b7 with SMTP id d1-20020a056a207f8100b0013accb9d5b7mr2498116pzj.41.1694166823401; Fri, 08 Sep 2023 02:53:43 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:43 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V11 02/23] mmc: core: Prepare to support SD UHS-II cards Date: Fri, 8 Sep 2023 17:53:09 +0800 Message-Id: <20230908095330.12075-3-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ulf Hansson The SD UHS-II interface was introduced to the SD spec v4.00 several years ago. The interface is fundamentally different from an electrical and a protocol point of view, comparing to the legacy SD interface. However, the legacy SD protocol is supported through a specific transport layer (SD-TRAN) defined in the UHS-II addendum of the spec. This allows the SD card to be managed in a very similar way as a legacy SD card, hence a lot of code can be re-used to support these new types of cards through the mmc subsystem. Moreover, an SD card that supports the UHS-II interface shall also be backwards compatible with the legacy SD interface, which allows a UHS-II card to be inserted into a legacy slot. As a matter of fact, this is already supported by mmc subsystem as of today. To prepare to add support for UHS-II, this change puts the basic foundation in the mmc core in place, allowing it to be more easily reviewed before subsequent changes implements the actual support. Basically, the approach here adds a new UHS-II bus_ops type and adds a separate initialization path for the UHS-II card. The intent is to avoid us from sprinkling the legacy initialization path, but also to simplify implementation of the UHS-II specific bits. At this point, there is only one new host ops added to manage the various ios settings needed for UHS-II. Additional host ops that are needed, are being added from subsequent changes. Signed-off-by: Ulf Hansson --- Updates in V10: - Drop unnecessary definitions and code. Updates in V9: - move sd_uhs2_operation definition of PatchV8[05/23] to PatchV9[02/23] for avoid compilation errors. - move uhs2_control definition of PatchV8[05/23] to PatchV9[02/23] for avoid compilation errors. - move mmc_host flags definition of PatchV8[05/23] to PatchV9[02/23] for avoid compilation errors. - move mmc_host flags MMC_UHS2_SUPPORT definition of PatchV8[05/23] to PatchV9[02/23] for avoid compilation errors. - move mmc_host flags MMC_UHS2_SD_TRAN definition of PatchV8[05/23] to PatchV9[02/23] for avoid compilation errors. Updates in V7: - Drop sd_uhs2_set_ios function. - Used ->uhs2_control() callback for uhs2_set_ios in sd_uhs2_power_up(). - Used ->uhs2_control() callback for uhs2_set_ios in sd_uhs2_power_off(). - Drop MMC_TIMING_SD_UHS2 in favor of MMC_TIMING_UHS2_SPEED_A. - Modify sd_uhs2_legacy_init to avoid sd_uhs2_reinit cycle issue. Updates in V4: - Re-based, updated a comment and removed white-space. - Moved MMC_VQMMC2_VOLTAGE_180 into a later patch in the series. --- drivers/mmc/core/Makefile | 2 +- drivers/mmc/core/core.c | 17 ++- drivers/mmc/core/core.h | 1 + drivers/mmc/core/sd_uhs2.c | 292 +++++++++++++++++++++++++++++++++++++ include/linux/mmc/card.h | 7 + include/linux/mmc/host.h | 23 +++ 6 files changed, 340 insertions(+), 2 deletions(-) create mode 100644 drivers/mmc/core/sd_uhs2.c diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile index 6a907736cd7a..15b067e8b0d1 100644 --- a/drivers/mmc/core/Makefile +++ b/drivers/mmc/core/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_MMC) += mmc_core.o mmc_core-y := core.o bus.o host.o \ mmc.o mmc_ops.o sd.o sd_ops.o \ sdio.o sdio_ops.o sdio_bus.o \ - sdio_cis.o sdio_io.o sdio_irq.o \ + sdio_cis.o sdio_io.o sdio_irq.o sd_uhs2.o\ slot-gpio.o regulator.o mmc_core-$(CONFIG_OF) += pwrseq.o obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 3d3e0ca52614..ba8808cd9318 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2244,6 +2244,18 @@ void mmc_rescan(struct work_struct *work) goto out; } + /* + * Ideally we should favor initialization of legacy SD cards and defer + * UHS-II enumeration. However, it seems like cards doesn't reliably + * announce their support for UHS-II in the response to the ACMD41, + * while initializing the legacy SD interface. Therefore, let's start + * with UHS-II for now. + */ + if (!mmc_attach_sd_uhs2(host)) { + mmc_release_host(host); + goto out; + } + for (i = 0; i < ARRAY_SIZE(freqs); i++) { unsigned int freq = freqs[i]; if (freq > host->f_max) { @@ -2276,10 +2288,13 @@ void mmc_rescan(struct work_struct *work) void mmc_start_host(struct mmc_host *host) { + bool power_up = !(host->caps2 & + (MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_SD_UHS2)); + host->f_init = max(min(freqs[0], host->f_max), host->f_min); host->rescan_disable = 0; - if (!(host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)) { + if (power_up) { mmc_claim_host(host); mmc_power_up(host, host->ocr_avail); mmc_release_host(host); diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h index 37091a6589ed..920323faa834 100644 --- a/drivers/mmc/core/core.h +++ b/drivers/mmc/core/core.h @@ -81,6 +81,7 @@ int mmc_detect_card_removed(struct mmc_host *host); int mmc_attach_mmc(struct mmc_host *host); int mmc_attach_sd(struct mmc_host *host); int mmc_attach_sdio(struct mmc_host *host); +int mmc_attach_sd_uhs2(struct mmc_host *host); /* Module parameters */ extern bool use_spi_crc; diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c new file mode 100644 index 000000000000..beb2541338ff --- /dev/null +++ b/drivers/mmc/core/sd_uhs2.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Linaro Ltd + * + * Author: Ulf Hansson + * + * Support for SD UHS-II cards + */ +#include + +#include +#include + +#include "core.h" +#include "bus.h" +#include "sd.h" +#include "mmc_ops.h" + +static const unsigned int sd_uhs2_freqs[] = { 52000000, 26000000 }; + +static int sd_uhs2_power_up(struct mmc_host *host) +{ + int err; + + if (host->ios.power_mode == MMC_POWER_ON) + return 0; + + host->ios.vdd = fls(host->ocr_avail) - 1; + host->ios.clock = host->f_init; + host->ios.timing = MMC_TIMING_UHS2_SPEED_A; + host->ios.power_mode = MMC_POWER_ON; + + err = host->ops->uhs2_control(host, UHS2_SET_IOS); + + return err; +} + +static int sd_uhs2_power_off(struct mmc_host *host) +{ + if (host->ios.power_mode == MMC_POWER_OFF) + return 0; + + host->ios.vdd = 0; + host->ios.clock = 0; + host->ios.timing = MMC_TIMING_LEGACY; + host->ios.power_mode = MMC_POWER_OFF; + + return host->ops->uhs2_control(host, UHS2_SET_IOS); +} + +/* + * Run the phy initialization sequence, which mainly relies on the UHS-II host + * to check that we reach the expected electrical state, between the host and + * the card. + */ +static int sd_uhs2_phy_init(struct mmc_host *host) +{ + return 0; +} + +/* + * Do the early initialization of the card, by sending the device init broadcast + * command and wait for the process to be completed. + */ +static int sd_uhs2_dev_init(struct mmc_host *host) +{ + return 0; +} + +/* + * Run the enumeration process by sending the enumerate command to the card. + * Note that, we currently support only the point to point connection, which + * means only one card can be attached per host/slot. + */ +static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) +{ + return 0; +} + +/* + * Read the UHS-II configuration registers (CFG_REG) of the card, by sending it + * commands and by parsing the responses. Store a copy of the relevant data in + * card->uhs2_config. + */ +static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Based on the card's and host's UHS-II capabilities, let's update the + * configuration of the card and the host. This may also include to move to a + * greater speed range/mode. Depending on the updated configuration, we may need + * to do a soft reset of the card via sending it a GO_DORMANT_STATE command. + * + * In the final step, let's check if the card signals "config completion", which + * indicates that the card has moved from config state into active state. + */ +static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Initialize the UHS-II card through the SD-TRAN transport layer. This enables + * commands/requests to be backwards compatible through the legacy SD protocol. + * UHS-II cards has a specific power limit specified for VDD1/VDD2, that should + * be set through a legacy CMD6. Note that, the power limit that becomes set, + * survives a soft reset through the GO_DORMANT_STATE command. + */ +static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card) +{ + return 0; +} + +/* + * Allocate the data structure for the mmc_card and run the UHS-II specific + * initialization sequence. + */ +static int sd_uhs2_init_card(struct mmc_host *host) +{ + struct mmc_card *card; + u32 node_id; + int err; + + err = sd_uhs2_dev_init(host); + if (err) + return err; + + err = sd_uhs2_enum(host, &node_id); + if (err) + return err; + + card = mmc_alloc_card(host, &sd_type); + if (IS_ERR(card)) + return PTR_ERR(card); + + card->uhs2_config.node_id = node_id; + card->type = MMC_TYPE_SD; + + err = sd_uhs2_config_read(host, card); + if (err) + goto err; + + err = sd_uhs2_config_write(host, card); + if (err) + goto err; + + host->card = card; + return 0; + +err: + mmc_remove_card(card); + return err; +} + +static void sd_uhs2_remove(struct mmc_host *host) +{ + mmc_remove_card(host->card); + host->card = NULL; +} + +static int sd_uhs2_alive(struct mmc_host *host) +{ + return mmc_send_status(host->card, NULL); +} + +static void sd_uhs2_detect(struct mmc_host *host) +{ + int err; + + mmc_get_card(host->card, NULL); + err = _mmc_detect_card_removed(host); + mmc_put_card(host->card, NULL); + + if (err) { + sd_uhs2_remove(host); + + mmc_claim_host(host); + mmc_detach_bus(host); + sd_uhs2_power_off(host); + mmc_release_host(host); + } +} + +static int sd_uhs2_suspend(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_resume(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_runtime_suspend(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_runtime_resume(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_shutdown(struct mmc_host *host) +{ + return 0; +} + +static int sd_uhs2_hw_reset(struct mmc_host *host) +{ + return 0; +} + +static const struct mmc_bus_ops sd_uhs2_ops = { + .remove = sd_uhs2_remove, + .alive = sd_uhs2_alive, + .detect = sd_uhs2_detect, + .suspend = sd_uhs2_suspend, + .resume = sd_uhs2_resume, + .runtime_suspend = sd_uhs2_runtime_suspend, + .runtime_resume = sd_uhs2_runtime_resume, + .shutdown = sd_uhs2_shutdown, + .hw_reset = sd_uhs2_hw_reset, +}; + +static int sd_uhs2_attach(struct mmc_host *host) +{ + int err; + + err = sd_uhs2_power_up(host); + if (err) + goto err; + + err = sd_uhs2_phy_init(host); + if (err) + goto err; + + err = sd_uhs2_init_card(host); + if (err) + goto err; + + err = sd_uhs2_legacy_init(host, host->card); + if (err) + goto err; + + mmc_attach_bus(host, &sd_uhs2_ops); + + mmc_release_host(host); + + err = mmc_add_card(host->card); + if (err) + goto remove_card; + + mmc_claim_host(host); + return 0; + +remove_card: + mmc_remove_card(host->card); + host->card = NULL; + mmc_claim_host(host); + mmc_detach_bus(host); +err: + sd_uhs2_power_off(host); + return err; +} + +int mmc_attach_sd_uhs2(struct mmc_host *host) +{ + int i, err = 0; + + if (!(host->caps2 & MMC_CAP2_SD_UHS2)) + return -EOPNOTSUPP; + + /* Turn off the legacy SD interface before trying with UHS-II. */ + mmc_power_off(host); + + /* + * Start UHS-II initialization at 52MHz and possibly make a retry at + * 26MHz according to the spec. It's required that the host driver + * validates ios->clock, to set a rate within the correct range. + */ + for (i = 0; i < ARRAY_SIZE(sd_uhs2_freqs); i++) { + host->f_init = sd_uhs2_freqs[i]; + err = sd_uhs2_attach(host); + if (!err) + break; + } + + return err; +} diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index daa2f40d9ce6..469fd68f854f 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -211,6 +211,11 @@ struct sd_ext_reg { #define SD_EXT_PERF_CMD_QUEUE (1<<4) }; +struct sd_uhs2_config { + u32 node_id; + /* TODO: Extend with more register configs. */ +}; + struct sdio_cccr { unsigned int sdio_vsn; unsigned int sd_vsn; @@ -318,6 +323,8 @@ struct mmc_card { struct sd_ext_reg ext_power; /* SD extension reg for PM */ struct sd_ext_reg ext_perf; /* SD extension reg for PERF */ + struct sd_uhs2_config uhs2_config; /* SD UHS-II config */ + unsigned int sdio_funcs; /* number of SDIO functions */ atomic_t sdio_funcs_probed; /* number of probed SDIO funcs */ struct sdio_cccr cccr; /* common card info */ diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 62a6847a3b6f..505b30935f48 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -63,6 +63,10 @@ struct mmc_ios { #define MMC_TIMING_MMC_HS400 10 #define MMC_TIMING_SD_EXP 11 #define MMC_TIMING_SD_EXP_1_2V 12 +#define MMC_TIMING_UHS2_SPEED_A 13 +#define MMC_TIMING_UHS2_SPEED_A_HD 14 +#define MMC_TIMING_UHS2_SPEED_B 15 +#define MMC_TIMING_UHS2_SPEED_B_HD 16 unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */ @@ -91,6 +95,14 @@ struct mmc_clk_phase_map { struct mmc_clk_phase phase[MMC_NUM_CLK_PHASES]; }; +struct sd_uhs2_caps { + /* TODO: Add UHS-II capabilities for the host. */ +}; + +enum sd_uhs2_operation { + UHS2_SET_IOS, +}; + struct mmc_host; enum mmc_err_stat { @@ -218,6 +230,14 @@ struct mmc_host_ops { /* Initialize an SD express card, mandatory for MMC_CAP2_SD_EXP. */ int (*init_sd_express)(struct mmc_host *host, struct mmc_ios *ios); + + /* + * The uhs2_control callback is used to execute SD UHS-II specific + * operations. It's mandatory to implement for hosts that supports the + * SD UHS-II interface (MMC_CAP2_SD_UHS2). Expected return values are a + * negative errno in case of a failure or zero for success. + */ + int (*uhs2_control)(struct mmc_host *host, enum sd_uhs2_operation op); }; struct mmc_cqe_ops { @@ -402,6 +422,7 @@ struct mmc_host { MMC_CAP2_HS200_1_2V_SDR) #define MMC_CAP2_SD_EXP (1 << 7) /* SD express via PCIe */ #define MMC_CAP2_SD_EXP_1_2V (1 << 8) /* SD express 1.2V */ +#define MMC_CAP2_SD_UHS2 (1 << 9) /* SD UHS-II support */ #define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */ #define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */ #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */ @@ -428,6 +449,8 @@ struct mmc_host { #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ + struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ + int fixed_drv_type; /* fixed driver type for non-removable media */ mmc_pm_flag_t pm_caps; /* supported pm features */ From patchwork Fri Sep 8 09:53:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B873EE57EF for ; Fri, 8 Sep 2023 09:53:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232395AbjIHJxv (ORCPT ); Fri, 8 Sep 2023 05:53:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242370AbjIHJxu (ORCPT ); Fri, 8 Sep 2023 05:53:50 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F11A1BCD; Fri, 8 Sep 2023 02:53:46 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-565334377d0so1560933a12.2; Fri, 08 Sep 2023 02:53:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166826; x=1694771626; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1KWK94KLa+RXOTyZSYZJIvaS/n+OcRc5XJNe1k7WdNQ=; b=IOjXN/65vl/jTfjTl7kzwwYPJogMRO8XJ/M14vN9KSF+9GYecnK8FxdICWi2usAEwF uY8wqOP/VvrDya3T1LCsv9MT2clhxAHhWxU1euFR9qTRLbOV3dUhNaZ8LRrcA5z7pOY6 IaTjcUEpd0o7Qt8LbHEgVGatSiBli+gr5IUtr12sNhDTkqvBrOUTVSx7QeRR2zjh28bH 67yEfIG3oCCY3rUHKXv+Y/27f/SF+GgDEiQ6ZJ3wXnCMUXHk5fVyazh0kmd9Z2+yTWtW 662cY8u/tpXe3zjQ53FNSovUx86vNs3NfbWWi2PPriuzU93I17BMxtT+eYYSW9h2KYHR 6zog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166826; x=1694771626; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1KWK94KLa+RXOTyZSYZJIvaS/n+OcRc5XJNe1k7WdNQ=; b=BYQAkgBwMJ2LlHqEDKt/QNSblFCZV53ECWftFdeVTfsljSUTOJQqF9GqypAxaCgZG4 ds1miU6LEpevx7+AVCW5EzZ/dkzfHvJmsdaFyYMgwDnb4f54DY4Vx2XI+HTHxpDE+VAw gUnl+jbGMyiIiL74fXlXquJh2r0+9JfuFu5aO9sL1klGi24stauvOBuVdfqU982/HYZN X8AFqI3wLtikMVMAgsmJMy0J3SGOuz04jJer7qPA9Ok7g8lYVpxUinXaCMjvcFYBtxC5 86eOFS3mgQtirguaGfv4bNYjzoouhy5IC3XWMomdPszZWWTSc+wojOHv/JsvEGWv47sp M5sg== X-Gm-Message-State: AOJu0YyHnrnF6eQSjTVfnjlyzy+eeDEVOXguF7WA5fi00t7U4g6Ua3Xk tzJux1yf1OgJGmHClQPtQ31YeOXjV4g= X-Google-Smtp-Source: AGHT+IFjQoYJLO1SA3+SCAYVDhgbkldx6i/jM1eYYWJRO0Xl2lTc4pmywQg3jMY9nnXxg3p7IrCbyg== X-Received: by 2002:a05:6a21:194:b0:13e:7d3:61d1 with SMTP id le20-20020a056a21019400b0013e07d361d1mr2666187pzb.12.1694166826018; Fri, 08 Sep 2023 02:53:46 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:45 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V11 03/23] mmc: core: Announce successful insertion of an SD UHS-II card Date: Fri, 8 Sep 2023 17:53:10 +0800 Message-Id: <20230908095330.12075-4-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ulf Hansson To inform the users about SD UHS-II cards, let's extend the print at card insertion with a "UHS-II" substring. Within this change, it seems reasonable to convert from using "ultra high speed" into "UHS-I speed", for the UHS-I type, as it should makes it more clear. Note that, the new print for UHS-II cards doesn't include the actual selected speed mode. Instead, this is going to be added from subsequent change. Signed-off-by: Ulf Hansson --- Updates in V10: - Modify the commit message. Updates in V7: - Drop MMC_TIMING_SD_UHS2 in favor of MMC_TIMING_UHS2_SPEED_A in mmc_card_uhs2 function. Updates in V4: - Make mmc_card_uhs2() take struct mmc_host* as in-param. --- drivers/mmc/core/bus.c | 4 +++- drivers/mmc/core/host.h | 7 +++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c index bd761e2858f1..e1760fc66d1e 100644 --- a/drivers/mmc/core/bus.c +++ b/drivers/mmc/core/bus.c @@ -344,7 +344,9 @@ int mmc_add_card(struct mmc_card *card) if (mmc_card_hs(card)) speed_mode = "high speed "; else if (mmc_card_uhs(card)) - speed_mode = "ultra high speed "; + speed_mode = "UHS-I speed "; + else if (mmc_card_uhs2(card->host)) + speed_mode = "UHS-II speed "; else if (mmc_card_ddr52(card)) speed_mode = "high speed DDR "; else if (mmc_card_hs200(card)) diff --git a/drivers/mmc/core/host.h b/drivers/mmc/core/host.h index 48c4952512a5..9f6e5e31dfea 100644 --- a/drivers/mmc/core/host.h +++ b/drivers/mmc/core/host.h @@ -89,5 +89,12 @@ static inline bool mmc_card_sd_express(struct mmc_host *host) host->ios.timing == MMC_TIMING_SD_EXP_1_2V; } +static inline bool mmc_card_uhs2(struct mmc_host *host) +{ + return host->ios.timing == MMC_TIMING_UHS2_SPEED_A || + host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD || + host->ios.timing == MMC_TIMING_UHS2_SPEED_B || + host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD; +} #endif From patchwork Fri Sep 8 09:53:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377304 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEA7BEE57EC for ; Fri, 8 Sep 2023 09:53:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231779AbjIHJx5 (ORCPT ); Fri, 8 Sep 2023 05:53:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242521AbjIHJxy (ORCPT ); Fri, 8 Sep 2023 05:53:54 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6747C1BF1; Fri, 8 Sep 2023 02:53:49 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-26fb8225268so1348455a91.1; Fri, 08 Sep 2023 02:53:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166829; x=1694771629; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8neypDPalnwcRyMDJSfFLCSaijYuZSqHnClQI/QiH6o=; b=BV1rrVSfP3g2rLJZ2TANCH+k+40hYjj/C4hVS7BfH5Sq/P4byRwZT42nBMUCtL1pHH VlzN+nAwGrVjnmbmUxJ2T67WmLlB3oEvwf6/snyMtuHMHMFaMl/y/no3m8f/D10J0YOk tiR6TsVlCp+Hd5UrIEKmG9NVreMl+K94CsQuK6i3n0Vzj12xZjUvcRGWXGJsxkGf21F2 xebKHJjxwM74SzzPuoQIkWezwp8cTaHcI9nG4gIRUw48m8dqcLi8tS5pmF5smrxMthQd ptvNDWAHgkVcms2ATEF/I2Z2cFPUS0OmzGE+DDF6wzAPFm3lSdaQoWJCFfH7a89zjBn3 uJTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166829; x=1694771629; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8neypDPalnwcRyMDJSfFLCSaijYuZSqHnClQI/QiH6o=; b=tx2KpNzyVfOoMftlQEzMxepAIc/goTKVk91w8va9VznKe2huheVNQ1ktL9AdJjlFow 6TTL9x1Mi3CCMxQle3AEVLWYjx+/E7BBmfScMwDHWbUHZthVXnD20x4Ir+wIEF19D1Jf SekDBjsxJBKFW/rc5kn4W7O8tCEHW4LMz45tNaEALvVNodSLJCB00omv2Kar41L6o33d reFmOOMf4o5EBrLXIRQHF93TOaHlVxN+yo8a2Rfiyz6/JVPg5ua6Uofrme/KSwC6DZ5I b+eZnIci+Y62Y5C7CHcUael6f/T6JTWGsLUTralfhy97VC55XtDVV7PY4jDNmqmUBdlM oUuw== X-Gm-Message-State: AOJu0Yz+MzFiG7svreE8QYA59JEOS6i2fyo0FPPZRNOhpK9K1dm6FWXv X1+Bof0SrOWErU22zcmIGUs= X-Google-Smtp-Source: AGHT+IEjJzR7RiDLLuAjd9P1nRIhmKosFqWJVcpnfn0K6v/mfFbl9lG1RWzQsS7zYd5rbKsRmT2qbw== X-Received: by 2002:a17:90a:8508:b0:273:e0b6:661 with SMTP id l8-20020a17090a850800b00273e0b60661mr628206pjn.46.1694166828821; Fri, 08 Sep 2023 02:53:48 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:48 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih Subject: [PATCH V11 04/23] mmc: core: Extend support for mmc regulators with a vqmmc2 Date: Fri, 8 Sep 2023 17:53:11 +0800 Message-Id: <20230908095330.12075-5-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ulf Hansson To allow an additional external regulator to be controlled by an mmc host driver, let's add support for a vqmmc2 regulator to the mmc core. For an SD UHS-II interface the vqmmc2 regulator may correspond to the so called vdd2 supply, as described by the SD spec. Initially, only 1.8V is needed, hence limit the new helper function, mmc_regulator_set_vqmmc2() to this too. Note that, to allow for flexibility mmc host drivers need to manage the enable/disable of the vqmmc2 regulator themselves, while the regulator is looked up through the common mmc_regulator_get_supply(). Signed-off-by: Ulf Hansson --- Updates in V10: - Modify the commit message. Updates in V4: - Moved the voltage defines into this patch. --- drivers/mmc/core/regulator.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/mmc/host.h | 11 +++++++++++ 2 files changed, 45 insertions(+) diff --git a/drivers/mmc/core/regulator.c b/drivers/mmc/core/regulator.c index 005247a49e51..208c27cfa505 100644 --- a/drivers/mmc/core/regulator.c +++ b/drivers/mmc/core/regulator.c @@ -226,6 +226,33 @@ int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios) } EXPORT_SYMBOL_GPL(mmc_regulator_set_vqmmc); +/** + * mmc_regulator_set_vqmmc2 - Set vqmmc2 as per the ios->vqmmc2_voltage + * @mmc: The mmc host to regulate + * @ios: The io bus settings + * + * Sets a new voltage level for the vqmmc2 regulator, which may correspond to + * the vdd2 regulator for an SD UHS-II interface. This function is expected to + * be called by mmc host drivers. + * + * Returns a negative error code on failure, zero if the voltage level was + * changed successfully or a positive value if the level didn't need to change. + */ +int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios) +{ + if (IS_ERR(mmc->supply.vqmmc2)) + return -EINVAL; + + switch (ios->vqmmc2_voltage) { + case MMC_VQMMC2_VOLTAGE_180: + return mmc_regulator_set_voltage_if_supported( + mmc->supply.vqmmc2, 1700000, 1800000, 1950000); + default: + return -EINVAL; + } +} +EXPORT_SYMBOL_GPL(mmc_regulator_set_vqmmc2); + #else static inline int mmc_regulator_get_ocrmask(struct regulator *supply) @@ -252,6 +279,7 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) mmc->supply.vmmc = devm_regulator_get_optional(dev, "vmmc"); mmc->supply.vqmmc = devm_regulator_get_optional(dev, "vqmmc"); + mmc->supply.vqmmc2 = devm_regulator_get_optional(dev, "vqmmc2"); if (IS_ERR(mmc->supply.vmmc)) { if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) @@ -271,6 +299,12 @@ int mmc_regulator_get_supply(struct mmc_host *mmc) dev_dbg(dev, "No vqmmc regulator found\n"); } + if (IS_ERR(mmc->supply.vqmmc2)) { + if (PTR_ERR(mmc->supply.vqmmc2) == -EPROBE_DEFER) + return -EPROBE_DEFER; + dev_dbg(dev, "No vqmmc2 regulator found\n"); + } + return 0; } EXPORT_SYMBOL_GPL(mmc_regulator_get_supply); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 505b30935f48..5dbc4f23797a 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -74,6 +74,9 @@ struct mmc_ios { #define MMC_SIGNAL_VOLTAGE_180 1 #define MMC_SIGNAL_VOLTAGE_120 2 + unsigned char vqmmc2_voltage; +#define MMC_VQMMC2_VOLTAGE_180 0 + unsigned char drv_type; /* driver type (A, B, C, D) */ #define MMC_SET_DRIVER_TYPE_B 0 @@ -331,6 +334,7 @@ struct mmc_pwrseq; struct mmc_supply { struct regulator *vmmc; /* Card power supply */ struct regulator *vqmmc; /* Optional Vccq supply */ + struct regulator *vqmmc2; /* Optional supply for phy */ }; struct mmc_ctx { @@ -612,6 +616,7 @@ int mmc_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, unsigned short vdd_bit); int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios); +int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, struct mmc_ios *ios); #else static inline int mmc_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, @@ -625,6 +630,12 @@ static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc, { return -EINVAL; } + +static inline int mmc_regulator_set_vqmmc2(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + return -EINVAL; +} #endif int mmc_regulator_get_supply(struct mmc_host *mmc); From patchwork Fri Sep 8 09:53:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6BA6EE57EC for ; Fri, 8 Sep 2023 09:54:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237015AbjIHJyG (ORCPT ); Fri, 8 Sep 2023 05:54:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242521AbjIHJyF (ORCPT ); Fri, 8 Sep 2023 05:54:05 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 410871BEA; Fri, 8 Sep 2023 02:53:53 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bd9b4f8e0eso13917965ad.1; Fri, 08 Sep 2023 02:53:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166832; x=1694771632; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lzoYhln+pmEVOy6NzZ5cliudm8kVo96bPzh5+KjZSw0=; b=cw3hh0r78xfsbdMcJnkQgwV+cC13Y3njtt9c8DYSkSscpivpUwzdtSB4Az0ql5JBqY BWUhFxf8UtzAqKwUVmK9TX+y4+2A5p5SvPckcR3rEECdZfm7jsijkHxA5XAQD0VSCBV+ HYL4Hca6+wnRzw6cDYBp/IvpBbz0S7D/iyRfnzy9kHOz/QInu3kppzOEUPtHwi8MU86L CBitkFRmegDNP3nNJDneTk9KT6eLRMstrgpQpsgiO6q8oV1WLssZgcwWpfbrIRbIN1tK LuoQTQSD3bFMta/yzmEf5knv7bt5RsJXSZGLyMKBFq5vfGfL9KgCHOgxz4lC67vFt4dV FNdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166832; x=1694771632; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lzoYhln+pmEVOy6NzZ5cliudm8kVo96bPzh5+KjZSw0=; b=T9jbfjoTUBP61OOZKMNGIVbfNqTtsMWU5sg2gBRqOUBNGDycbuS5eMHacwmiQuzo2t pYfrTc3LQvWJcFBmV9fttOYrUJP/uIMwWdEI3ycNFfNjy34qgtkTDIJPRKhRbmRilrgN 5UBGMjilNVzXYVPY4yTDstsJdS+jv/ZRGygIh0YKeyoy7ncQFyj12uHbPfi/xjMSbQQb L54a/cybKxCDAJYoJpOTXEmAp8gTQ0SCS6F2KhQU7WkFl9P4Clq7f2RqlSk1VSvE0Hxc /dnh1lIc2o0My87PPPlMrpwNBepdf+B2tWGCmnyZ7RikIqLiReQgelQx5d+zVKYScNMB 4XsA== X-Gm-Message-State: AOJu0YxZAlM4DQU4TogMV+8hN10YmrDwXng/kZczlzefYhd+xQ5WzD/4 lG8FgRlI1zGgVP2mCYwgejItEmOx6rE= X-Google-Smtp-Source: AGHT+IFNokF0ViMsyrpjM1/FmIdnzhIb0IS2Bx+jKiJ7QF1r+JlXS5g/N/ScwSQv/vEomPXzzR1jKA== X-Received: by 2002:a17:903:1c7:b0:1b6:b445:36d4 with SMTP id e7-20020a17090301c700b001b6b44536d4mr2258511plh.43.1694166831729; Fri, 08 Sep 2023 02:53:51 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:51 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Jason Lai , Victor Shih Subject: [PATCH V11 05/23] mmc: core: Add definitions for SD UHS-II cards Date: Fri, 8 Sep 2023 17:53:12 +0800 Message-Id: <20230908095330.12075-6-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Add UHS-II specific data structures for commands and defines for registers, as described in Part 1 UHS-II Addendum Version 1.01. UHS-II related definitions are listed below: 1. UHS-II card capability: sd_uhs2_caps{} 2. UHS-II configuration: sd_uhs2_config{} 3. UHS-II register I/O address and register field definitions: sd_uhs2.h Signed-off-by: Ulf Hansson Signed-off-by: Jason Lai Signed-off-by: Victor Shih --- Updates in V10: - Drop unnecessary definitions. Updates in V7: - Remove unnecessary definitions. Updates in V6: - Remove unnecessary definitions and functions. --- include/linux/mmc/card.h | 31 ++++- include/linux/mmc/host.h | 26 +++- include/linux/mmc/sd_uhs2.h | 240 ++++++++++++++++++++++++++++++++++++ 3 files changed, 295 insertions(+), 2 deletions(-) create mode 100644 include/linux/mmc/sd_uhs2.h diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h index 469fd68f854f..5cfc94b778f4 100644 --- a/include/linux/mmc/card.h +++ b/include/linux/mmc/card.h @@ -190,6 +190,12 @@ struct sd_switch_caps { #define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) #define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) #define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) + +#define SD4_SET_POWER_LIMIT_0_72W 0 +#define SD4_SET_POWER_LIMIT_1_44W 1 +#define SD4_SET_POWER_LIMIT_2_16W 2 +#define SD4_SET_POWER_LIMIT_2_88W 3 +#define SD4_SET_POWER_LIMIT_1_80W 4 }; struct sd_ext_reg { @@ -213,7 +219,30 @@ struct sd_ext_reg { struct sd_uhs2_config { u32 node_id; - /* TODO: Extend with more register configs. */ + + u32 n_fcu; + u32 maxblk_len; + u8 n_lanes; + u8 dadr_len; + u8 app_type; + u8 phy_minor_rev; + u8 phy_major_rev; + u8 can_hibernate; + u8 n_lss_sync; + u8 n_lss_dir; + u8 link_minor_rev; + u8 link_major_rev; + u8 dev_type; + u8 n_data_gap; + + u32 n_fcu_set; + u32 maxblk_len_set; + u8 n_lanes_set; + u8 speed_range_set; + u8 n_lss_sync_set; + u8 n_lss_dir_set; + u8 n_data_gap_set; + u8 max_retry_set; }; struct sdio_cccr { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 5dbc4f23797a..240397f1e11d 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -16,6 +16,7 @@ #include #include #include +#include struct mmc_ios { unsigned int clock; /* clock rate */ @@ -99,7 +100,29 @@ struct mmc_clk_phase_map { }; struct sd_uhs2_caps { - /* TODO: Add UHS-II capabilities for the host. */ + u32 dap; + u32 gap; + u32 group_desc; + u32 maxblk_len; + u32 n_fcu; + u8 n_lanes; + u8 addr64; + u8 card_type; + u8 phy_rev; + u8 speed_range; + u8 n_lss_sync; + u8 n_lss_dir; + u8 link_rev; + u8 host_type; + u8 n_data_gap; + + u32 maxblk_len_set; + u32 n_fcu_set; + u8 n_lanes_set; + u8 n_lss_sync_set; + u8 n_lss_dir_set; + u8 n_data_gap_set; + u8 max_retry_set; }; enum sd_uhs2_operation { @@ -358,6 +381,7 @@ struct mmc_host { u32 max_current_330; u32 max_current_300; u32 max_current_180; + u32 max_current_180_vdd2; /* UHS2 vdd2 max curt. */ #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ diff --git a/include/linux/mmc/sd_uhs2.h b/include/linux/mmc/sd_uhs2.h new file mode 100644 index 000000000000..7abe9bd870c7 --- /dev/null +++ b/include/linux/mmc/sd_uhs2.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Header file for UHS-II packets, Host Controller registers and I/O + * accessors. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef LINUX_MMC_UHS2_H +#define LINUX_MMC_UHS2_H + +/* LINK Layer definition */ +/* + * UHS2 Header: + * Refer to UHS-II Addendum Version 1.02 Figure 5-2, the format of CCMD Header is described below: + * bit [3:0] : DID(Destination ID = Node ID of UHS2 card) + * bit [6:4] : TYP(Packet Type) + * 000b: CCMD(Control command packet) + * 001b: DCMD(Data command packet) + * 010b: RES(Response packet) + * 011b: DATA(Data payload packet) + * 111b: MSG(Message packet) + * Others: Reserved + * bit [7] : NP(Native Packet) + * bit [10:8] : TID(Transaction ID) + * bit [11] : Reserved + * bit [15:12]: SID(Source ID 0: Node ID of Host) + * + * Broadcast CCMD issued by Host is represented as DID=SID=0. + */ +/* + * UHS2 Argument: + * Refer to UHS-II Addendum Version 1.02 Figure 6-5, the format of CCMD Argument is described below: + * bit [3:0] : MSB of IOADR + * bit [5:4] : PLEN(Payload Length) + * 00b: 0 byte + * 01b: 4 bytes + * 10b: 8 bytes + * 11b: 16 bytes + * bit [6] : Reserved + * bit [7] : R/W(Read/Write) + * 0: Control read command + * 1: Control write command + * bit [15:8] : LSB of IOADR + * + * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. + * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. + */ +#define UHS2_NATIVE_PACKET_POS 7 +#define UHS2_NATIVE_PACKET (1 << UHS2_NATIVE_PACKET_POS) + +#define UHS2_PACKET_TYPE_POS 4 +#define UHS2_PACKET_TYPE_CCMD (0 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_DCMD (1 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_RES (2 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_DATA (3 << UHS2_PACKET_TYPE_POS) +#define UHS2_PACKET_TYPE_MSG (7 << UHS2_PACKET_TYPE_POS) + +#define UHS2_DEST_ID_MASK 0x0F +#define UHS2_DEST_ID 0x1 + +#define UHS2_SRC_ID_POS 12 +#define UHS2_SRC_ID_MASK 0xF000 + +#define UHS2_TRANS_ID_POS 8 +#define UHS2_TRANS_ID_MASK 0x0700 + +/* UHS2 MSG */ +#define UHS2_MSG_CTG_POS 5 +#define UHS2_MSG_CTG_LMSG 0x00 +#define UHS2_MSG_CTG_INT 0x60 +#define UHS2_MSG_CTG_AMSG 0x80 + +#define UHS2_MSG_CTG_FCREQ 0x00 +#define UHS2_MSG_CTG_FCRDY 0x01 +#define UHS2_MSG_CTG_STAT 0x02 + +#define UHS2_MSG_CODE_POS 8 +#define UHS2_MSG_CODE_FC_UNRECOVER_ERR 0x8 +#define UHS2_MSG_CODE_STAT_UNRECOVER_ERR 0x8 +#define UHS2_MSG_CODE_STAT_RECOVER_ERR 0x1 + +/* TRANS Layer definition */ + +/* Native packets*/ +#define UHS2_NATIVE_CMD_RW_POS 7 +#define UHS2_NATIVE_CMD_WRITE (1 << UHS2_NATIVE_CMD_RW_POS) +#define UHS2_NATIVE_CMD_READ (0 << UHS2_NATIVE_CMD_RW_POS) + +#define UHS2_NATIVE_CMD_PLEN_POS 4 +#define UHS2_NATIVE_CMD_PLEN_4B (1 << UHS2_NATIVE_CMD_PLEN_POS) +#define UHS2_NATIVE_CMD_PLEN_8B (2 << UHS2_NATIVE_CMD_PLEN_POS) +#define UHS2_NATIVE_CMD_PLEN_16B (3 << UHS2_NATIVE_CMD_PLEN_POS) + +#define UHS2_NATIVE_CCMD_GET_MIOADR_MASK 0xF00 +#define UHS2_NATIVE_CCMD_MIOADR_MASK 0x0F + +#define UHS2_NATIVE_CCMD_LIOADR_POS 8 +#define UHS2_NATIVE_CCMD_GET_LIOADR_MASK 0x0FF + +#define UHS2_CCMD_DEV_INIT_COMPLETE_FLAG BIT(11) +#define UHS2_DEV_INIT_PAYLOAD_LEN 1 +#define UHS2_DEV_INIT_RESP_LEN 6 +#define UHS2_DEV_ENUM_PAYLOAD_LEN 1 +#define UHS2_DEV_ENUM_RESP_LEN 8 +#define UHS2_CFG_WRITE_PAYLOAD_LEN 2 +#define UHS2_CFG_WRITE_PHY_SET_RESP_LEN 4 +#define UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN 5 +#define UHS2_GO_DORMANT_PAYLOAD_LEN 1 + +/* + * UHS2 Argument: + * Refer to UHS-II Addendum Version 1.02 Figure 6-8, the format of DCMD Argument is described below: + * bit [3:0] : Reserved + * bit [6:3] : TMODE(Transfer Mode) + * bit 3: DAM(Data Access Mode) + * bit 4: TLUM(TLEN Unit Mode) + * bit 5: LM(Length Mode) + * bit 6: DM(Duplex Mode) + * bit [7] : R/W(Read/Write) + * 0: Control read command + * 1: Control write command + * bit [15:8] : Reserved + * + * I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD. + * The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last. + */ +#define UHS2_DCMD_DM_POS 6 +#define UHS2_DCMD_2L_HD_MODE (1 << UHS2_DCMD_DM_POS) +#define UHS2_DCMD_LM_POS 5 +#define UHS2_DCMD_LM_TLEN_EXIST (1 << UHS2_DCMD_LM_POS) +#define UHS2_DCMD_TLUM_POS 4 +#define UHS2_DCMD_TLUM_BYTE_MODE (1 << UHS2_DCMD_TLUM_POS) +#define UHS2_NATIVE_DCMD_DAM_POS 3 +#define UHS2_NATIVE_DCMD_DAM_IO (1 << UHS2_NATIVE_DCMD_DAM_POS) + +#define UHS2_RES_NACK_POS 7 +#define UHS2_RES_NACK_MASK (0x1 << UHS2_RES_NACK_POS) + +#define UHS2_RES_ECODE_POS 4 +#define UHS2_RES_ECODE_MASK 0x7 +#define UHS2_RES_ECODE_COND 1 +#define UHS2_RES_ECODE_ARG 2 +#define UHS2_RES_ECODE_GEN 3 + +/* IOADR of device registers */ +#define UHS2_IOADR_GENERIC_CAPS 0x00 +#define UHS2_IOADR_PHY_CAPS 0x02 +#define UHS2_IOADR_LINK_CAPS 0x04 +#define UHS2_IOADR_RSV_CAPS 0x06 +#define UHS2_IOADR_GENERIC_SETTINGS 0x08 +#define UHS2_IOADR_PHY_SETTINGS 0x0A +#define UHS2_IOADR_LINK_SETTINGS 0x0C +#define UHS2_IOADR_PRESET 0x40 + +/* SD application packets */ +#define UHS2_SD_CMD_INDEX_POS 8 + +#define UHS2_SD_CMD_APP_POS 14 +#define UHS2_SD_CMD_APP (1 << UHS2_SD_CMD_APP_POS) + +/* UHS-II Device Registers */ +#define UHS2_DEV_CONFIG_REG 0x000 + +/* General Caps and Settings registers */ +#define UHS2_DEV_CONFIG_GEN_CAPS (UHS2_DEV_CONFIG_REG + 0x000) +#define UHS2_DEV_CONFIG_N_LANES_POS 8 +#define UHS2_DEV_CONFIG_N_LANES_MASK 0x3F +#define UHS2_DEV_CONFIG_2L_HD_FD 0x1 +#define UHS2_DEV_CONFIG_2D1U_FD 0x2 +#define UHS2_DEV_CONFIG_1D2U_FD 0x4 +#define UHS2_DEV_CONFIG_2D2U_FD 0x8 +#define UHS2_DEV_CONFIG_DADR_POS 14 +#define UHS2_DEV_CONFIG_DADR_MASK 0x1 +#define UHS2_DEV_CONFIG_APP_POS 16 +#define UHS2_DEV_CONFIG_APP_MASK 0xFF +#define UHS2_DEV_CONFIG_APP_SD_MEM 0x1 + +#define UHS2_DEV_CONFIG_GEN_SET (UHS2_DEV_CONFIG_REG + 0x008) +#define UHS2_DEV_CONFIG_GEN_SET_N_LANES_POS 8 +#define UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD 0x0 +#define UHS2_DEV_CONFIG_GEN_SET_2D1U_FD 0x2 +#define UHS2_DEV_CONFIG_GEN_SET_1D2U_FD 0x3 +#define UHS2_DEV_CONFIG_GEN_SET_2D2U_FD 0x4 +#define UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE BIT(31) + +/* PHY Caps and Settings registers */ +#define UHS2_DEV_CONFIG_PHY_CAPS (UHS2_DEV_CONFIG_REG + 0x002) +#define UHS2_DEV_CONFIG_PHY_MINOR_MASK 0xF +#define UHS2_DEV_CONFIG_PHY_MAJOR_POS 4 +#define UHS2_DEV_CONFIG_PHY_MAJOR_MASK 0x3 +#define UHS2_DEV_CONFIG_CAN_HIBER_POS 15 +#define UHS2_DEV_CONFIG_CAN_HIBER_MASK 0x1 +#define UHS2_DEV_CONFIG_PHY_CAPS1 (UHS2_DEV_CONFIG_REG + 0x003) +#define UHS2_DEV_CONFIG_N_LSS_SYN_MASK 0xF +#define UHS2_DEV_CONFIG_N_LSS_DIR_POS 4 +#define UHS2_DEV_CONFIG_N_LSS_DIR_MASK 0xF + +#define UHS2_DEV_CONFIG_PHY_SET (UHS2_DEV_CONFIG_REG + 0x00A) +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_POS 6 +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_A 0x0 +#define UHS2_DEV_CONFIG_PHY_SET_SPEED_B 0x1 + +/* LINK-TRAN Caps and Settings registers */ +#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS (UHS2_DEV_CONFIG_REG + 0x004) +#define UHS2_DEV_CONFIG_LT_MINOR_MASK 0xF +#define UHS2_DEV_CONFIG_LT_MAJOR_POS 4 +#define UHS2_DEV_CONFIG_LT_MAJOR_MASK 0x3 +#define UHS2_DEV_CONFIG_N_FCU_POS 8 +#define UHS2_DEV_CONFIG_N_FCU_MASK 0xFF +#define UHS2_DEV_CONFIG_DEV_TYPE_POS 16 +#define UHS2_DEV_CONFIG_DEV_TYPE_MASK 0x7 +#define UHS2_DEV_CONFIG_MAX_BLK_LEN_POS 20 +#define UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK 0xFFF +#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS1 (UHS2_DEV_CONFIG_REG + 0x005) +#define UHS2_DEV_CONFIG_N_DATA_GAP_MASK 0xFF + +#define UHS2_DEV_CONFIG_LINK_TRAN_SET (UHS2_DEV_CONFIG_REG + 0x00C) +#define UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN 0x200 +#define UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS 16 + +/* Preset register */ +#define UHS2_DEV_CONFIG_PRESET (UHS2_DEV_CONFIG_REG + 0x040) + +#define UHS2_DEV_INT_REG 0x100 + +#define UHS2_DEV_STATUS_REG 0x180 + +#define UHS2_DEV_CMD_REG 0x200 +#define UHS2_DEV_CMD_FULL_RESET (UHS2_DEV_CMD_REG + 0x000) +#define UHS2_DEV_CMD_GO_DORMANT_STATE (UHS2_DEV_CMD_REG + 0x001) +#define UHS2_DEV_CMD_DORMANT_HIBER BIT(7) +#define UHS2_DEV_CMD_DEVICE_INIT (UHS2_DEV_CMD_REG + 0x002) +#define UHS2_DEV_INIT_COMPLETE_FLAG BIT(11) +#define UHS2_DEV_CMD_ENUMERATE (UHS2_DEV_CMD_REG + 0x003) +#define UHS2_DEV_CMD_TRANS_ABORT (UHS2_DEV_CMD_REG + 0x004) + +#define UHS2_RCLK_MAX 52000000 +#define UHS2_RCLK_MIN 26000000 + +#endif /* LINUX_MMC_UHS2_H */ From patchwork Fri Sep 8 09:53:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377306 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 950A2EE57EC for ; Fri, 8 Sep 2023 09:54:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242521AbjIHJyV (ORCPT ); Fri, 8 Sep 2023 05:54:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236248AbjIHJyU (ORCPT ); Fri, 8 Sep 2023 05:54:20 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCBD61FF3; Fri, 8 Sep 2023 02:53:55 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1c1e3a4a06fso14666625ad.3; Fri, 08 Sep 2023 02:53:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166835; x=1694771635; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EbaRNmnCOLOmOywoRXHbog16VlYJTQrZHUWjLpjUZ38=; b=SKr2d1N+I4DgI1Zk8qJUKNOqBwzeG5ezNc84CFf6oodrvNObyCxO82EvPdQOu891Gq pcErPl2BMLWHWGiruVUPtnczQ/uMUcSTWZv2u3zgG2VwL7vvMdROZWgTluUIeHGm7EM/ DC8Z5fsy6bi7SYle64wDhAZLBNFhfNGpzkzgtTkh6iOsM1bsl1m0dvMyx/MHkIr2joly YNmK2Yhs6kFacQjL2CAR4vnLDcDLkWoG+qVPi1egcGItR0TvmOkKQ/vqMcUiXJBRlzKN xirTnRl4Idkqkbh+ddvwcerYNbFgy87Yj+W7P4gXMbIZErs1gRwieY58U1MWkZ1PukOK cDnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166835; x=1694771635; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EbaRNmnCOLOmOywoRXHbog16VlYJTQrZHUWjLpjUZ38=; b=FdAf5okmEkDnGLunK4bWbvxbYkQP9igrLEPbgpTiiUc4cPKBNeVJ66TOrkzEhWcbHl DmulE7PgM9eFU+Bg14/GJOwau+8/6q3gTfiTsxWcprW7S0lH0r8GrwjzYy9yxzRhWsal WwkNeCDPUFyToHbbB9JHw4wVLAjmSOWH/rRY1wPbRSLgx5yAT2egmpnaM2fBvJeYHBDv vF67qIfomqDByU7UP1S5yOp/5lTMlrYlSy1sdZ+kasNtxiIxnNZIecONtabMx5lWcSB2 gM1KLjH8Dm1SWdYrb+L2OP+4KtiIvXm2e32EcL9PViBMW4OwXgdW8pVo6vGp/AseuvAB t8yQ== X-Gm-Message-State: AOJu0YwpUOHQLppo14c2tXZxohFtv+cJKcMmyqfieSyoCybSsJdT90Gg BXqLrZSIv0A6OvRaDrKilTMfy+pc1Sc= X-Google-Smtp-Source: AGHT+IHrc7HDHwvER1NMgcWByTJatJeVLqg2SfywSyoBVjTyTu1yJTd8NSm3y9v7yLCK2jb/ByLMvA== X-Received: by 2002:a17:902:ea08:b0:1b3:9d13:34b3 with SMTP id s8-20020a170902ea0800b001b39d1334b3mr2503749plg.37.1694166834804; Fri, 08 Sep 2023 02:53:54 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:54 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Jason Lai , Victor Shih Subject: [PATCH V11 06/23] mmc: core: Support UHS-II card control and access Date: Fri, 8 Sep 2023 17:53:13 +0800 Message-Id: <20230908095330.12075-7-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Embed UHS-II access/control functionality into the MMC request processing flow. Signed-off-by: Ulf Hansson Signed-off-by: Jason Lai Signed-off-by: Victor Shih --- Updates in V10: - Move some definitions of PatchV9[02/23] to PatchV10[06/23]. - Move some definitions of PatchV9[05/23] to PatchV10[06/23]. - Drop do_multi in the mmc_blk_rw_rq_prep(). - Use tmode_half_duplex to instead of uhs2_tmode0_flag. - Move entire control of the tmode into mmc_uhs2_prepare_cmd(). Updates in V8: - Add MMC_UHS2_SUPPORT to be cleared in sd_uhs2_detect(). - Modify return value in sd_uhs2_attach(). Updates in V7: - Add mmc_uhs2_card_prepare_cmd helper function in sd_ops.h. - Drop uhs2_state in favor of ios->timing. - Remove unnecessary functions. --- drivers/mmc/core/core.c | 8 + drivers/mmc/core/mmc_ops.c | 24 +- drivers/mmc/core/mmc_ops.h | 1 + drivers/mmc/core/sd.c | 13 +- drivers/mmc/core/sd.h | 4 + drivers/mmc/core/sd_ops.c | 9 + drivers/mmc/core/sd_ops.h | 18 + drivers/mmc/core/sd_uhs2.c | 1147 +++++++++++++++++++++++++++++++++++- include/linux/mmc/core.h | 13 + include/linux/mmc/host.h | 18 + 10 files changed, 1206 insertions(+), 49 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index ba8808cd9318..f5dc653eafb0 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -334,6 +334,8 @@ static int mmc_mrq_prep(struct mmc_host *host, struct mmc_request *mrq) int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + __be32 payload[4]; /* for maximum size */ int err; init_completion(&mrq->cmd_completion); @@ -351,6 +353,8 @@ int mmc_start_request(struct mmc_host *host, struct mmc_request *mrq) if (err) return err; + mmc_uhs2_card_prepare_cmd(host, mrq, uhs2_cmd, payload); + led_trigger_event(host->led, LED_FULL); __mmc_start_request(host, mrq); @@ -430,6 +434,8 @@ EXPORT_SYMBOL(mmc_wait_for_req_done); */ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) { + struct uhs2_command uhs2_cmd; + __be32 payload[4]; /* for maximum size */ int err; /* @@ -450,6 +456,8 @@ int mmc_cqe_start_req(struct mmc_host *host, struct mmc_request *mrq) if (err) goto out_err; + mmc_uhs2_card_prepare_cmd(host, mrq, uhs2_cmd, payload); + err = host->cqe_ops->cqe_request(host, mrq); if (err) goto out_err; diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 3b3adbddf664..5c8e62e8f331 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c @@ -144,10 +144,24 @@ int mmc_set_dsr(struct mmc_host *host) return mmc_wait_for_cmd(host, &cmd, MMC_CMD_RETRIES); } +int __mmc_go_idle(struct mmc_host *host) +{ + struct mmc_command cmd = {}; + int err; + + cmd.opcode = MMC_GO_IDLE_STATE; + cmd.arg = 0; + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; + + err = mmc_wait_for_cmd(host, &cmd, 0); + mmc_delay(1); + + return err; +} + int mmc_go_idle(struct mmc_host *host) { int err; - struct mmc_command cmd = {}; /* * Non-SPI hosts need to prevent chipselect going active during @@ -163,13 +177,7 @@ int mmc_go_idle(struct mmc_host *host) mmc_delay(1); } - cmd.opcode = MMC_GO_IDLE_STATE; - cmd.arg = 0; - cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; - - err = mmc_wait_for_cmd(host, &cmd, 0); - - mmc_delay(1); + err = __mmc_go_idle(host); if (!mmc_host_is_spi(host)) { mmc_set_chip_select(host, MMC_CS_DONTCARE); diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h index 92d4194c7893..3eaefe989c80 100644 --- a/drivers/mmc/core/mmc_ops.h +++ b/drivers/mmc/core/mmc_ops.h @@ -25,6 +25,7 @@ struct mmc_command; int mmc_select_card(struct mmc_card *card); int mmc_deselect_cards(struct mmc_host *host); int mmc_set_dsr(struct mmc_host *host); +int __mmc_go_idle(struct mmc_host *host); int mmc_go_idle(struct mmc_host *host); int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr); int mmc_set_relative_addr(struct mmc_card *card); diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index c3e554344c99..8d2e739a7c5c 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -207,7 +207,7 @@ static int mmc_decode_csd(struct mmc_card *card) /* * Given a 64-bit response, decode to our card SCR structure. */ -static int mmc_decode_scr(struct mmc_card *card) +int mmc_decode_scr(struct mmc_card *card) { struct sd_scr *scr = &card->scr; unsigned int scr_struct; @@ -904,7 +904,7 @@ int mmc_sd_get_csd(struct mmc_card *card) return 0; } -static int mmc_sd_get_ro(struct mmc_host *host) +int mmc_sd_get_ro(struct mmc_host *host) { int ro; @@ -1630,11 +1630,6 @@ static void mmc_sd_detect(struct mmc_host *host) } } -static int sd_can_poweroff_notify(struct mmc_card *card) -{ - return card->ext_power.feature_support & SD_EXT_POWER_OFF_NOTIFY; -} - static int sd_busy_poweroff_notify_cb(void *cb_data, bool *busy) { struct sd_busy_data *data = cb_data; @@ -1658,7 +1653,7 @@ static int sd_busy_poweroff_notify_cb(void *cb_data, bool *busy) return 0; } -static int sd_poweroff_notify(struct mmc_card *card) +int sd_poweroff_notify(struct mmc_card *card) { struct sd_busy_data cb_data; u8 *reg_buf; @@ -1706,7 +1701,7 @@ static int _mmc_sd_suspend(struct mmc_host *host) if (mmc_card_suspended(card)) goto out; - if (sd_can_poweroff_notify(card)) + if (mmc_sd_can_poweroff_notify(card)) err = sd_poweroff_notify(card); else if (!mmc_host_is_spi(host)) err = mmc_deselect_cards(host); diff --git a/drivers/mmc/core/sd.h b/drivers/mmc/core/sd.h index 1af5a038bae9..d31259919ee5 100644 --- a/drivers/mmc/core/sd.h +++ b/drivers/mmc/core/sd.h @@ -11,10 +11,14 @@ struct mmc_card; int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr); int mmc_sd_get_csd(struct mmc_card *card); +int mmc_sd_get_ro(struct mmc_host *host); void mmc_decode_cid(struct mmc_card *card); int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, bool reinit); unsigned mmc_sd_get_max_clock(struct mmc_card *card); int mmc_sd_switch_hs(struct mmc_card *card); +/* These call back functions were also used by UHS2 sd card */ +int sd_poweroff_notify(struct mmc_card *card); + #endif diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c index a59cd592f06e..b0cba0cd24a5 100644 --- a/drivers/mmc/core/sd_ops.c +++ b/drivers/mmc/core/sd_ops.c @@ -27,6 +27,15 @@ int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card) if (WARN_ON(card && card->host != host)) return -EINVAL; + /* + * UHS2 packet has APP bit so only set APP_CMD flag here. + * Will set the APP bit when assembling UHS2 packet. + */ + if (host->flags & MMC_UHS2_SD_TRAN) { + host->uhs2_app_cmd = true; + return 0; + } + cmd.opcode = MMC_APP_CMD; if (card) { diff --git a/drivers/mmc/core/sd_ops.h b/drivers/mmc/core/sd_ops.h index 7667fc223b74..b8ff4713c914 100644 --- a/drivers/mmc/core/sd_ops.h +++ b/drivers/mmc/core/sd_ops.h @@ -11,6 +11,7 @@ #include struct mmc_card; +struct mmc_command; struct mmc_host; int mmc_app_set_bus_width(struct mmc_card *card, int width); @@ -19,8 +20,25 @@ int mmc_send_if_cond(struct mmc_host *host, u32 ocr); int mmc_send_if_cond_pcie(struct mmc_host *host, u32 ocr); int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca); int mmc_app_send_scr(struct mmc_card *card); +int mmc_decode_scr(struct mmc_card *card); int mmc_app_sd_status(struct mmc_card *card, void *ssr); int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card); +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq); + +static inline void mmc_uhs2_card_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq, + struct uhs2_command uhs2_cmd, __be32 payload[4]) +{ + if (host->flags & MMC_UHS2_SD_TRAN) { + uhs2_cmd.payload = payload; + mrq->cmd->uhs2_cmd = &uhs2_cmd; + mmc_uhs2_prepare_cmd(host, mrq); + } +} + +static inline int mmc_sd_can_poweroff_notify(struct mmc_card *card) +{ + return card->ext_power.feature_support & SD_EXT_POWER_OFF_NOTIFY; +} #endif diff --git a/drivers/mmc/core/sd_uhs2.c b/drivers/mmc/core/sd_uhs2.c index beb2541338ff..97c4608086e5 100644 --- a/drivers/mmc/core/sd_uhs2.c +++ b/drivers/mmc/core/sd_uhs2.c @@ -1,23 +1,51 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2021 Linaro Ltd - * * Author: Ulf Hansson * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Author: Yi Sun + * + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + * + * Copyright (C) 2022 Genesys Logic, Inc. + * Authors: Jason Lai + * + * Copyright (C) 2023 Genesys Logic, Inc. + * Authors: Victor Shih + * * Support for SD UHS-II cards */ #include +#include #include #include +#include +#include +#include +#include "card.h" #include "core.h" #include "bus.h" #include "sd.h" +#include "sd_ops.h" #include "mmc_ops.h" +#define UHS2_WAIT_CFG_COMPLETE_PERIOD_US (1 * 1000) /* 1ms */ +#define UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS 100 /* 100ms */ + static const unsigned int sd_uhs2_freqs[] = { 52000000, 26000000 }; +struct sd_uhs2_wait_active_state_data { + struct mmc_host *host; + struct mmc_command *cmd; +}; + static int sd_uhs2_power_up(struct mmc_host *host) { int err; @@ -44,10 +72,49 @@ static int sd_uhs2_power_off(struct mmc_host *host) host->ios.clock = 0; host->ios.timing = MMC_TIMING_LEGACY; host->ios.power_mode = MMC_POWER_OFF; + if (host->flags & MMC_UHS2_SD_TRAN) + host->flags &= ~MMC_UHS2_SD_TRAN; return host->ops->uhs2_control(host, UHS2_SET_IOS); } +/* + * sd_uhs2_cmd_assemble() - build up UHS-II command packet which is embedded in + * mmc_command structure + * @cmd: MMC command to executed + * @uhs2_cmd: UHS2 command corresponded to MMC command + * @header: Header field of UHS-II command cxpacket + * @arg: Argument field of UHS-II command packet + * @payload: Payload field of UHS-II command packet + * @plen: Payload length + * @resp: Response buffer is allocated by caller and it is used to keep + * the response of CM-TRAN command. For SD-TRAN command, uhs2_resp + * should be null and SD-TRAN command response should be stored in + * resp of mmc_command. + * @resp_len: Response buffer length + * + * The uhs2_command structure contains message packets which are transmited/ + * received on UHS-II bus. This function fills in the contents of uhs2_command + * structure and embededs UHS2 command into mmc_command structure, which is used + * in legacy SD operation functions. + * + */ +static void sd_uhs2_cmd_assemble(struct mmc_command *cmd, + struct uhs2_command *uhs2_cmd, + u16 header, u16 arg, __be32 *payload, + u8 plen, u8 *resp, u8 resp_len) +{ + uhs2_cmd->header = header; + uhs2_cmd->arg = arg; + uhs2_cmd->payload = payload; + uhs2_cmd->payload_len = plen * sizeof(u32); + uhs2_cmd->packet_len = uhs2_cmd->payload_len + 4; + + cmd->uhs2_cmd = uhs2_cmd; + cmd->uhs2_resp = resp; + cmd->uhs2_resp_len = resp_len; +} + /* * Run the phy initialization sequence, which mainly relies on the UHS-II host * to check that we reach the expected electrical state, between the host and @@ -55,7 +122,15 @@ static int sd_uhs2_power_off(struct mmc_host *host) */ static int sd_uhs2_phy_init(struct mmc_host *host) { - return 0; + int err = 0; + + err = host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) { + pr_err("%s: failed to initial phy for UHS-II!\n", + mmc_hostname(host)); + } + + return err; } /* @@ -64,6 +139,82 @@ static int sd_uhs2_phy_init(struct mmc_host *host) */ static int sd_uhs2_dev_init(struct mmc_host *host) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u32 cnt; + u32 dap, gap, resp_gap; + u16 header, arg; + __be32 payload[UHS2_DEV_INIT_PAYLOAD_LEN]; + u8 gd = 0; + u8 resp[UHS2_DEV_ENUM_RESP_LEN] = {0}; + int err; + + dap = host->uhs2_caps.dap; + gap = host->uhs2_caps.gap; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-21 to see DEVICE_INIT CCMD format. + * Head: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 002h + * Payload: + * - bit [3:0] : GAP(Group Allocated Power) + * - bit [7:4] : GD(Group Descriptor) + * - bit [11] : Complete Flag + * - bit [15:12]: DAP(Device Allocated Power) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + arg = ((UHS2_DEV_CMD_DEVICE_INIT & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_DEVICE_INIT >> 8); + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.3.1. + * Max. time from DEVICE_INIT CCMD EOP reception on Device + * Rx to its SOP transmission on Device Tx(Tfwd_init_cmd) is + * 1 second. + */ + cmd.busy_timeout = 1000; + + /* + * Refer to UHS-II Addendum Version 1.02 section 6.2.6.3. + * When the number of the DEVICE_INIT commands is reach to + * 30 tiems, Host shall stop issuing DEVICE_INIT command + * and regard it as an error. + */ + for (cnt = 0; cnt < 30; cnt++) { + payload[0] = ((dap & 0xF) << 12) | + UHS2_DEV_INIT_COMPLETE_FLAG | + ((gd & 0xF) << 4) | + (gap & 0xF); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, + payload, UHS2_DEV_INIT_PAYLOAD_LEN, + resp, UHS2_DEV_INIT_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (resp[3] != (UHS2_DEV_CMD_DEVICE_INIT & 0xFF)) { + pr_err("%s: DEVICE_INIT response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + if (resp[5] & 0x8) { + host->uhs2_caps.group_desc = gd; + return 0; + } + resp_gap = resp[4] & 0x0F; + if (gap == resp_gap) + gd++; + } + return 0; } @@ -74,6 +225,52 @@ static int sd_uhs2_dev_init(struct mmc_host *host) */ static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[UHS2_DEV_ENUM_PAYLOAD_LEN]; + u8 id_f = 0xF, id_l = 0x0; + u8 resp[UHS2_DEV_ENUM_RESP_LEN] = {0}; + int err; + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-28 to see ENUMERATE CCMD format. + * Header: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 003h + * Payload: + * - bit [3:0]: ID_L(Last Node ID) + * - bit [7:4]: ID_F(First Node ID) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD; + arg = ((UHS2_DEV_CMD_ENUMERATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_ENUMERATE >> 8); + + payload[0] = (id_f << 4) | id_l; + payload[0] = cpu_to_be32(payload[0]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_DEV_ENUM_PAYLOAD_LEN, + resp, UHS2_DEV_ENUM_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if (resp[3] != (UHS2_DEV_CMD_ENUMERATE & 0xFF)) { + pr_err("%s: ENUMERATE response is wrong!\n", + mmc_hostname(host)); + return -EIO; + } + + id_f = (resp[4] >> 4) & 0xF; + id_l = resp[4] & 0xF; + *node_id = id_f; + return 0; } @@ -84,6 +281,181 @@ static int sd_uhs2_enum(struct mmc_host *host, u32 *node_id) */ static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + u32 cap; + int err; + + /* + * Use Control Read CCMD to read Generic Capability from Configuration Register. + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = Generic Capability Register(CFG_BASE + 000h) + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; + arg = ((UHS2_DEV_CONFIG_GEN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CONFIG_GEN_CAPS >> 8); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Generic Capability Register: + * bit [7:0] : Reserved + * bit [13:8] : Device-Specific Number of Lanes and Functionality + * bit 8: 2L-HD + * bit 9: 2D-1U FD + * bit 10: 1D-2U FD + * bit 11: 2D-2U FD + * Others: Reserved + * bit [14] : DADR Length + * 0: 4 bytes + * 1: Reserved + * bit [23:16]: Application Type + * bit 16: 0=Non-SD memory, 1=SD memory + * bit 17: 0=Non-SDIO, 1=SDIO + * bit 18: 0=Card, 1=Embedded + * bit [63:24]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.n_lanes = + (cap >> UHS2_DEV_CONFIG_N_LANES_POS) & + UHS2_DEV_CONFIG_N_LANES_MASK; + card->uhs2_config.dadr_len = + (cap >> UHS2_DEV_CONFIG_DADR_POS) & + UHS2_DEV_CONFIG_DADR_MASK; + card->uhs2_config.app_type = + (cap >> UHS2_DEV_CONFIG_APP_POS) & + UHS2_DEV_CONFIG_APP_MASK; + + /* + * Use Control Read CCMD to read PHY Capability from Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PHY Capability Register(CFG_BASE + 002h) + */ + arg = ((UHS2_DEV_CONFIG_PHY_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * PHY Capability Register: + * bit [3:0] : PHY Minor Revision + * bit [5:4] : PHY Major Revision + * bit [15] : Support Hibernate Mode + * 0: Not support Hibernate Mode + * 1: Support Hibernate Mode + * bit [31:16]: Reserved + * bit [35:32]: Device-Specific N_LSS_SYN + * bit [39:36]: Device-Specific N_LSS_DIR + * bit [63:40]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.phy_minor_rev = + cap & UHS2_DEV_CONFIG_PHY_MINOR_MASK; + card->uhs2_config.phy_major_rev = + (cap >> UHS2_DEV_CONFIG_PHY_MAJOR_POS) & + UHS2_DEV_CONFIG_PHY_MAJOR_MASK; + card->uhs2_config.can_hibernate = + (cap >> UHS2_DEV_CONFIG_CAN_HIBER_POS) & + UHS2_DEV_CONFIG_CAN_HIBER_MASK; + + cap = cmd.resp[1]; + card->uhs2_config.n_lss_sync = + cap & UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + card->uhs2_config.n_lss_dir = + (cap >> UHS2_DEV_CONFIG_N_LSS_DIR_POS) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + if (card->uhs2_config.n_lss_sync == 0) + card->uhs2_config.n_lss_sync = 16 << 2; + else + card->uhs2_config.n_lss_sync <<= 2; + + if (card->uhs2_config.n_lss_dir == 0) + card->uhs2_config.n_lss_dir = 16 << 3; + else + card->uhs2_config.n_lss_dir <<= 3; + + /* + * Use Control Read CCMD to read LINK/TRAN Capability from Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = LINK/TRAN Capability Register(CFG_BASE + 004h) + */ + arg = ((UHS2_DEV_CONFIG_LINK_TRAN_CAPS & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_CAPS >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * LINK/TRAN Capability Register: + * bit [3:0] : LINK_TRAN Minor Revision + * bit [5:4] : LINK/TRAN Major Revision + * bit [7:6] : Reserved + * bit [15:8] : Device-Specific N_FCU + * bit [18:16]: Device Type + * 001b=Host + * 010b=Device + * 011b=Reserved for CMD issuable Device + * bit [19] : Reserved + * bit [31:20]: Device-Specific MAX_BLKLEN + * bit [39:32]: Device-Specific N_DATA_GAP + * bit [63:40]: Reserved + */ + cap = cmd.resp[0]; + card->uhs2_config.link_minor_rev = + cap & UHS2_DEV_CONFIG_LT_MINOR_MASK; + card->uhs2_config.link_major_rev = + (cap >> UHS2_DEV_CONFIG_LT_MAJOR_POS) & + UHS2_DEV_CONFIG_LT_MAJOR_MASK; + card->uhs2_config.n_fcu = + (cap >> UHS2_DEV_CONFIG_N_FCU_POS) & + UHS2_DEV_CONFIG_N_FCU_MASK; + card->uhs2_config.dev_type = + (cap >> UHS2_DEV_CONFIG_DEV_TYPE_POS) & + UHS2_DEV_CONFIG_DEV_TYPE_MASK; + card->uhs2_config.maxblk_len = + (cap >> UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) & + UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK; + + cap = cmd.resp[1]; + card->uhs2_config.n_data_gap = + cap & UHS2_DEV_CONFIG_N_DATA_GAP_MASK; + if (card->uhs2_config.n_fcu == 0) + card->uhs2_config.n_fcu = 256; + return 0; } @@ -98,26 +470,357 @@ static int sd_uhs2_config_read(struct mmc_host *host, struct mmc_card *card) */ static int sd_uhs2_config_write(struct mmc_host *host, struct mmc_card *card) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[UHS2_CFG_WRITE_PAYLOAD_LEN]; + u8 nMinDataGap; + int err; + u8 resp[5] = {0}; + + /* + * Use Control Write CCMD to set Generic Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = Generic Setting Register(CFG_BASE + 008h) + * - Payload = New contents to be written to Generic Setting Register + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | card->uhs2_config.node_id; + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + /* + * Most UHS-II cards only support FD and 2L-HD mode. Other lane numbers + * defined in UHS-II addendem Ver1.01 are optional. + */ + host->uhs2_caps.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + card->uhs2_config.n_lanes_set = UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD; + + payload[0] = card->uhs2_config.n_lanes_set << UHS2_DEV_CONFIG_N_LANES_POS; + payload[1] = 0; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + /* + * There is no payload because per spec, there should be + * no payload field for read CCMD. + * Plen is set in arg. Per spec, plen for read CCMD + * represents the len of read data which is assigned in payload + * of following RES (p136). + */ + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set PHY Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PHY Setting Register(CFG_BASE + 00Ah) + * - Payload = New contents to be written to PHY Setting Register + */ + arg = ((UHS2_DEV_CONFIG_PHY_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_PHY_SET >> 8); + + if (host->uhs2_caps.speed_range == UHS2_DEV_CONFIG_PHY_SET_SPEED_B) { + if (card->uhs2_config.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD && + host->uhs2_caps.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD) { + /* Support HD */ + host->ios.timing = MMC_TIMING_UHS2_SPEED_B_HD; + nMinDataGap = 1; + } else { + /* Only support 2L-FD so far */ + host->ios.timing = MMC_TIMING_UHS2_SPEED_B; + nMinDataGap = 3; + } + card->uhs2_config.speed_range_set = UHS2_DEV_CONFIG_PHY_SET_SPEED_B; + } else { + if (card->uhs2_config.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD && + host->uhs2_caps.n_lanes == UHS2_DEV_CONFIG_2L_HD_FD) { + /* Support HD */ + host->ios.timing = MMC_TIMING_UHS2_SPEED_A_HD; + nMinDataGap = 1; + } else { + /* Only support 2L-FD so far */ + host->ios.timing = MMC_TIMING_UHS2_SPEED_A; + nMinDataGap = 3; + } + card->uhs2_config.speed_range_set = UHS2_DEV_CONFIG_PHY_SET_SPEED_A; + } + + payload[0] = card->uhs2_config.speed_range_set << UHS2_DEV_CONFIG_PHY_SET_SPEED_POS; + + card->uhs2_config.n_lss_sync_set = (max(card->uhs2_config.n_lss_sync, + host->uhs2_caps.n_lss_sync) >> 2) & + UHS2_DEV_CONFIG_N_LSS_SYN_MASK; + host->uhs2_caps.n_lss_sync_set = card->uhs2_config.n_lss_sync_set; + + card->uhs2_config.n_lss_dir_set = (max(card->uhs2_config.n_lss_dir, + host->uhs2_caps.n_lss_dir) >> 3) & + UHS2_DEV_CONFIG_N_LSS_DIR_MASK; + host->uhs2_caps.n_lss_dir_set = card->uhs2_config.n_lss_dir_set; + + payload[1] = (card->uhs2_config.n_lss_dir_set << UHS2_DEV_CONFIG_N_LSS_DIR_POS) | + card->uhs2_config.n_lss_sync_set; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + memset(resp, 0, sizeof(resp)); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + resp, UHS2_CFG_WRITE_PHY_SET_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + if ((resp[2] & 0x80)) { + pr_err("%s: %s: UHS2 CMD not accepted, resp= 0x%x!\n", + mmc_hostname(host), __func__, resp[2]); + return -EIO; + } + + /* + * Use Control Write CCMD to set LINK/TRAN Setting in Configuration Register. + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = LINK/TRAN Setting Register(CFG_BASE + 00Ch) + * - Payload = New contents to be written to LINK/TRAN Setting Register + */ + arg = ((UHS2_DEV_CONFIG_LINK_TRAN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_LINK_TRAN_SET >> 8); + + if (card->uhs2_config.app_type == UHS2_DEV_CONFIG_APP_SD_MEM) + card->uhs2_config.maxblk_len_set = UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN; + else + card->uhs2_config.maxblk_len_set = min(card->uhs2_config.maxblk_len, + host->uhs2_caps.maxblk_len); + host->uhs2_caps.maxblk_len_set = card->uhs2_config.maxblk_len_set; + + card->uhs2_config.n_fcu_set = min(card->uhs2_config.n_fcu, host->uhs2_caps.n_fcu); + host->uhs2_caps.n_fcu_set = card->uhs2_config.n_fcu_set; + + card->uhs2_config.n_data_gap_set = max(nMinDataGap, card->uhs2_config.n_data_gap); + host->uhs2_caps.n_data_gap_set = card->uhs2_config.n_data_gap_set; + + host->uhs2_caps.max_retry_set = 3; + card->uhs2_config.max_retry_set = host->uhs2_caps.max_retry_set; + + payload[0] = (card->uhs2_config.maxblk_len_set << UHS2_DEV_CONFIG_MAX_BLK_LEN_POS) | + (card->uhs2_config.max_retry_set << UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS) | + (card->uhs2_config.n_fcu_set << UHS2_DEV_CONFIG_N_FCU_POS); + payload[1] = card->uhs2_config.n_data_gap_set; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Write CCMD to set Config Completion(payload bit 63) in Generic Setting + * Register. + * Header: + * - Control Write(R/W=1) with 8-Byte payload(PLEN=10b). + * - IOADR = PGeneric Setting Register(CFG_BASE + 008h) + * Payload: + * - bit [63]: Config Completion + * + * DLSM transits to Active state immediately when Config Completion is set to 1. + */ + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + payload[0] = 0; + payload[1] = UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE; + payload[0] = cpu_to_be32(payload[0]); + payload[1] = cpu_to_be32(payload[1]); + + memset(resp, 0, sizeof(resp)); + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_CFG_WRITE_PAYLOAD_LEN, + resp, UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Set host Config Setting registers */ + err = host->ops->uhs2_control(host, UHS2_SET_CONFIG); + if (err) { + pr_err("%s: %s: UHS2 SET_CONFIG fail!\n", mmc_hostname(host), __func__); + return err; + } + + return 0; +} + +static int sd_uhs2_go_dormant(struct mmc_host *host, u32 node_id) +{ + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + __be32 payload[1]; + int err; + + /* Disable Normal INT */ + err = host->ops->uhs2_control(host, UHS2_DISABLE_INT); + if (err) { + pr_err("%s: %s: UHS2 DISABLE_INT fail!\n", + mmc_hostname(host), __func__); + return err; + } + + /* + * Refer to UHS-II Addendum Version 1.02 Figure 6-17 to see GO_DORMANT_STATE CCMD format. + * Header: + * - Control Write(R/W=1) with 4-Byte payload(PLEN=01b). + * - IOADR = CMD_BASE + 001h + * Payload: + * - bit [7]: HBR(Entry to Hibernate Mode) + * 1: Host intends to enter Hibernate mode during Dormant state. + * The default setting is 0 because hibernate is currently not supported. + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + arg = ((UHS2_DEV_CMD_GO_DORMANT_STATE & 0xFF) << 8) | + UHS2_NATIVE_CMD_WRITE | + UHS2_NATIVE_CMD_PLEN_4B | + (UHS2_DEV_CMD_GO_DORMANT_STATE >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, payload, UHS2_GO_DORMANT_PAYLOAD_LEN, + NULL, 0); + + err = mmc_wait_for_cmd(host, &cmd, 0); + if (err) { + pr_err("%s: %s: UHS2 CMD send fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* Check Dormant State in Present */ + err = host->ops->uhs2_control(host, UHS2_CHECK_DORMANT); + if (err) + return err; + + /* Disable UHS2 card clock */ + err = host->ops->uhs2_control(host, UHS2_DISABLE_CLK); + if (err) + return err; + + /* Restore sd clock */ + mmc_delay(5); + err = host->ops->uhs2_control(host, UHS2_ENABLE_CLK); + if (err) + return err; + + /* Enable Normal INT */ + err = host->ops->uhs2_control(host, UHS2_ENABLE_INT); + if (err) + return err; + + /* Detect UHS2 */ + err = host->ops->uhs2_control(host, UHS2_PHY_INIT); + if (err) + return err; + + return 0; +} + +static int __sd_uhs2_wait_active_state_cb(void *cb_data, bool *busy) +{ + struct sd_uhs2_wait_active_state_data *data = cb_data; + struct mmc_host *host = data->host; + struct mmc_command *cmd = data->cmd; + int err; + + err = mmc_wait_for_cmd(host, cmd, 0); + if (err) + return err; + + if (cmd->resp[1] & UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE) + *busy = false; + else + *busy = true; + return 0; } -/* - * Initialize the UHS-II card through the SD-TRAN transport layer. This enables - * commands/requests to be backwards compatible through the legacy SD protocol. - * UHS-II cards has a specific power limit specified for VDD1/VDD2, that should - * be set through a legacy CMD6. Note that, the power limit that becomes set, - * survives a soft reset through the GO_DORMANT_STATE command. - */ -static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card) +static int sd_uhs2_go_dormant_state(struct mmc_host *host, u32 node_id) { + struct mmc_command cmd = {0}; + struct uhs2_command uhs2_cmd = {}; + u16 header, arg; + int err; + struct sd_uhs2_wait_active_state_data cb_data = { + .host = host, + .cmd = &cmd + }; + + err = sd_uhs2_go_dormant(host, node_id); + if (err) { + pr_err("%s: %s: UHS2 GO_DORMANT_STATE fail, err= 0x%x!\n", + mmc_hostname(host), __func__, err); + return err; + } + + /* + * Use Control Read CCMD to check Config Completion(bit 63) in Generic Setting Register. + * - Control Read(R/W=0) with 8-Byte payload(PLEN=10b). + * - IOADR = Generic Setting Register(CFG_BASE + 008h) + * + * When UHS-II card been switched to new speed mode, it will set Config Completion to 1. + */ + header = UHS2_NATIVE_PACKET | UHS2_PACKET_TYPE_CCMD | node_id; + arg = ((UHS2_DEV_CONFIG_GEN_SET & 0xFF) << 8) | + UHS2_NATIVE_CMD_READ | + UHS2_NATIVE_CMD_PLEN_8B | + (UHS2_DEV_CONFIG_GEN_SET >> 8); + + sd_uhs2_cmd_assemble(&cmd, &uhs2_cmd, header, arg, NULL, 0, NULL, 0); + err = __mmc_poll_for_busy(host, UHS2_WAIT_CFG_COMPLETE_PERIOD_US, + UHS2_WAIT_CFG_COMPLETE_TIMEOUT_MS, + &__sd_uhs2_wait_active_state_cb, &cb_data); + if (err) { + pr_err("%s: %s: Not switch to Active in 100 ms\n", mmc_hostname(host), __func__); + return err; + } + return 0; } +static void sd_uhs2_remove(struct mmc_host *host) +{ + mmc_remove_card(host->card); + host->card = NULL; +} + /* * Allocate the data structure for the mmc_card and run the UHS-II specific * initialization sequence. */ -static int sd_uhs2_init_card(struct mmc_host *host) +static int sd_uhs2_init_card(struct mmc_host *host, struct mmc_card *oldcard) { struct mmc_card *card; u32 node_id; @@ -131,9 +834,14 @@ static int sd_uhs2_init_card(struct mmc_host *host) if (err) return err; - card = mmc_alloc_card(host, &sd_type); - if (IS_ERR(card)) - return PTR_ERR(card); + if (oldcard) { + card = oldcard; + } else { + card = mmc_alloc_card(host, &sd_type); + if (IS_ERR(card)) + return PTR_ERR(card); + } + host->card = card; card->uhs2_config.node_id = node_id; card->type = MMC_TYPE_SD; @@ -146,18 +854,226 @@ static int sd_uhs2_init_card(struct mmc_host *host) if (err) goto err; - host->card = card; + /* If change speed to Range B, need to GO_DORMANT_STATE */ + if (host->ios.timing == MMC_TIMING_UHS2_SPEED_B || + host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD) { + err = sd_uhs2_go_dormant_state(host, node_id); + if (err) + return err; + } + + host->flags |= MMC_UHS2_SD_TRAN; + return 0; err: - mmc_remove_card(card); + sd_uhs2_remove(host); return err; } -static void sd_uhs2_remove(struct mmc_host *host) +int sd_uhs2_reinit(struct mmc_host *host) { - mmc_remove_card(host->card); - host->card = NULL; + struct mmc_card *card = host->card; + int err; + + sd_uhs2_power_up(host); + err = sd_uhs2_phy_init(host); + if (err) + return err; + + err = sd_uhs2_init_card(host, card); + if (err) + return err; + + mmc_card_set_present(card); + return err; +} + +/* + * Mask off any voltages we don't support and select + * the lowest voltage + */ +u32 sd_uhs2_select_voltage(struct mmc_host *host, u32 ocr) +{ + int bit; + int err; + + /* + * Sanity check the voltages that the card claims to + * support. + */ + if (ocr & 0x7F) { + dev_warn(mmc_dev(host), "card claims to support voltages below defined range\n"); + ocr &= ~0x7F; + } + + ocr &= host->ocr_avail; + if (!ocr) { + dev_warn(mmc_dev(host), "no support for card's volts\n"); + return 0; + } + + if (host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) { + bit = ffs(ocr) - 1; + ocr &= 3 << bit; + /* Power cycle */ + err = sd_uhs2_power_off(host); + if (err) + return 0; + err = sd_uhs2_reinit(host); + if (err) + return 0; + } else { + bit = fls(ocr) - 1; + ocr &= 3 << bit; + if (bit != host->ios.vdd) + dev_warn(mmc_dev(host), "exceeding card's volts\n"); + } + + return ocr; +} + +/* + * Initialize the UHS-II card through the SD-TRAN transport layer. This enables + * commands/requests to be backwards compatible through the legacy SD protocol. + * UHS-II cards has a specific power limit specified for VDD1/VDD2, that should + * be set through a legacy CMD6. Note that, the power limit that becomes set, + * survives a soft reset through the GO_DORMANT_STATE command. + */ +static int sd_uhs2_legacy_init(struct mmc_host *host, struct mmc_card *card) +{ + int err; + u32 cid[4]; + u32 ocr; + u32 rocr; + u8 *status; + int ro; + + /* Send CMD0 to reset SD card */ + err = __mmc_go_idle(host); + if (err) + return err; + + mmc_delay(1); + + /* Send CMD8 to communicate SD interface operation condition */ + err = mmc_send_if_cond(host, host->ocr_avail); + if (err) { + dev_warn(mmc_dev(host), "CMD8 error\n"); + goto err; + } + + /* + * Probe SD card working voltage. + */ + err = mmc_send_app_op_cond(host, 0, &ocr); + if (err) + goto err; + + card->ocr = ocr; + + /* + * Some SD cards claims an out of spec VDD voltage range. Let's treat + * these bits as being in-valid and especially also bit7. + */ + ocr &= ~0x7FFF; + rocr = sd_uhs2_select_voltage(host, ocr); + /* + * Some cards have zero value of rocr in UHS-II mode. Assign host's + * ocr value to rocr. + */ + if (!rocr) + rocr = host->ocr_avail; + + rocr |= (SD_OCR_CCS | SD_OCR_XPC); + + /* Wait SD power on ready */ + ocr = rocr; + + err = mmc_send_app_op_cond(host, ocr, &rocr); + if (err) + goto err; + + err = mmc_send_cid(host, cid); + if (err) + goto err; + + memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); + mmc_decode_cid(card); + + /* + * For native busses: get card RCA and quit open drain mode. + */ + err = mmc_send_relative_addr(host, &card->rca); + if (err) + goto err; + + err = mmc_sd_get_csd(card); + if (err) + goto err; + + /* + * Select card, as all following commands rely on that. + */ + err = mmc_select_card(card); + if (err) + goto err; + + /* + * Fetch SCR from card. + */ + err = mmc_app_send_scr(card); + if (err) + goto err; + + err = mmc_decode_scr(card); + if (err) + goto err; + + /* + * Switch to high power consumption mode. + * Even switch failed, sd card can still work at lower power consumption mode, but + * performance will be lower than high power consumption mode. + */ + status = kmalloc(64, GFP_KERNEL); + if (!status) + return -ENOMEM; + + if (!(card->csd.cmdclass & CCC_SWITCH)) { + pr_warn("%s: card lacks mandatory switch function, performance might suffer\n", + mmc_hostname(card->host)); + } else { + /* send CMD6 to set Maximum Power Consumption to get better performance */ + err = mmc_sd_switch(card, 0, 3, SD4_SET_POWER_LIMIT_1_80W, status); + if (!err) + err = mmc_sd_switch(card, 1, 3, SD4_SET_POWER_LIMIT_1_80W, status); + + err = 0; + } + + /* + * Check if read-only switch is active. + */ + ro = mmc_sd_get_ro(host); + if (ro < 0) { + pr_warn("%s: host does not support read-only switch, assuming write-enable\n", + mmc_hostname(host)); + } else if (ro > 0) { + mmc_card_set_readonly(card); + } + + /* + * NOTE: + * Should we read Externsion Register to check power notification feature here? + */ + + kfree(status); + + return 0; + +err: + sd_uhs2_remove(host); + return err; } static int sd_uhs2_alive(struct mmc_host *host) @@ -179,38 +1095,189 @@ static void sd_uhs2_detect(struct mmc_host *host) mmc_claim_host(host); mmc_detach_bus(host); sd_uhs2_power_off(host); + host->flags &= ~MMC_UHS2_SUPPORT; mmc_release_host(host); } } +static int _sd_uhs2_suspend(struct mmc_host *host) +{ + struct mmc_card *card = host->card; + int err = 0; + + mmc_claim_host(host); + + if (mmc_card_suspended(card)) + goto out; + + if (mmc_sd_can_poweroff_notify(card)) + err = sd_poweroff_notify(card); + + if (!err) { + sd_uhs2_power_off(host); + mmc_card_set_suspended(card); + } + +out: + mmc_release_host(host); + return err; +} + +/* + * Callback for suspend + */ static int sd_uhs2_suspend(struct mmc_host *host) { - return 0; + int err; + + err = _sd_uhs2_suspend(host); + if (!err) { + pm_runtime_disable(&host->card->dev); + pm_runtime_set_suspended(&host->card->dev); + } + + return err; +} + +/* + * This function tries to determine if the same card is still present + * and, if so, restore all state to it. + */ +static int _mmc_sd_uhs2_resume(struct mmc_host *host) +{ + int err = 0; + + mmc_claim_host(host); + + if (!mmc_card_suspended(host->card)) + goto out; + + /* Power up UHS2 SD card and re-initialize it. */ + err = sd_uhs2_reinit(host); + mmc_card_clr_suspended(host->card); + +out: + mmc_release_host(host); + return err; } +/* + * Callback for resume + */ static int sd_uhs2_resume(struct mmc_host *host) { + pm_runtime_enable(&host->card->dev); return 0; } +/* + * Callback for runtime_suspend. + */ static int sd_uhs2_runtime_suspend(struct mmc_host *host) { - return 0; + int err; + + if (!(host->caps & MMC_CAP_AGGRESSIVE_PM)) + return 0; + + err = _sd_uhs2_suspend(host); + if (err) + pr_err("%s: error %d doing aggressive suspend\n", mmc_hostname(host), err); + + return err; } static int sd_uhs2_runtime_resume(struct mmc_host *host) { - return 0; + int err; + + err = _mmc_sd_uhs2_resume(host); + if (err && err != -ENOMEDIUM) + pr_err("%s: error %d doing runtime resume\n", mmc_hostname(host), err); + + return err; } -static int sd_uhs2_shutdown(struct mmc_host *host) +static int sd_uhs2_hw_reset(struct mmc_host *host) { - return 0; + int err; + + sd_uhs2_power_off(host); + /* Wait at least 1 ms according to SD spec */ + mmc_delay(1); + sd_uhs2_power_up(host); + + err = sd_uhs2_reinit(host); + + return err; } -static int sd_uhs2_hw_reset(struct mmc_host *host) +/* + * mmc_uhs2_prepare_cmd - prepare for SD command packet + * @host: MMC host + * @mrq: MMC request + * + * Initialize and fill in a header and a payload of SD command packet. + * The caller should allocate uhs2_command in host->cmd->uhs2_cmd in + * advance. + * + * Return: 0 on success, non-zero error on failure + */ +void mmc_uhs2_prepare_cmd(struct mmc_host *host, struct mmc_request *mrq) { - return 0; + struct mmc_command *cmd; + struct uhs2_command *uhs2_cmd; + u16 header, arg; + __be32 *payload; + u8 plen; + + cmd = mrq->cmd; + header = host->card->uhs2_config.node_id; + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + header |= UHS2_PACKET_TYPE_DCMD; + else + header |= UHS2_PACKET_TYPE_CCMD; + + arg = cmd->opcode << UHS2_SD_CMD_INDEX_POS; + if (host->uhs2_app_cmd) { + arg |= UHS2_SD_CMD_APP; + host->uhs2_app_cmd = false; + } + + if (cmd->opcode == SD_APP_SEND_SCR || cmd->opcode == SD_APP_SD_STATUS || + cmd->opcode == MMC_SEND_EXT_CSD || cmd->opcode == SD_SWITCH || + cmd->opcode == SD_READ_EXTR_SINGLE || cmd->opcode == MMC_SEND_CSD || + cmd->opcode == MMC_SEND_CID) + cmd->uhs2_cmd->tmode_half_duplex = 0; + else + cmd->uhs2_cmd->tmode_half_duplex = mmc_card_uhs2_hd_mode(host); + + uhs2_cmd = cmd->uhs2_cmd; + payload = uhs2_cmd->payload; + plen = 2; /* at the maximum */ + + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC && + cmd->uhs2_cmd->tmode_half_duplex) { + if (mmc_card_uhs2_hd_mode(host)) + arg |= UHS2_DCMD_2L_HD_MODE; + + arg |= UHS2_DCMD_LM_TLEN_EXIST; + + if (cmd->data->blocks == 1 && + cmd->data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + arg |= UHS2_DCMD_TLUM_BYTE_MODE; + payload[1] = cpu_to_be32(cmd->data->blksz); + } else { + payload[1] = cpu_to_be32(cmd->data->blocks); + } + } else { + plen = 1; + } + + payload[0] = cpu_to_be32(cmd->arg); + sd_uhs2_cmd_assemble(cmd, uhs2_cmd, header, arg, payload, plen, NULL, 0); } static const struct mmc_bus_ops sd_uhs2_ops = { @@ -221,7 +1288,7 @@ static const struct mmc_bus_ops sd_uhs2_ops = { .resume = sd_uhs2_resume, .runtime_suspend = sd_uhs2_runtime_suspend, .runtime_resume = sd_uhs2_runtime_resume, - .shutdown = sd_uhs2_shutdown, + .shutdown = sd_uhs2_suspend, .hw_reset = sd_uhs2_hw_reset, }; @@ -229,6 +1296,8 @@ static int sd_uhs2_attach(struct mmc_host *host) { int err; + host->flags |= MMC_UHS2_SUPPORT; + err = sd_uhs2_power_up(host); if (err) goto err; @@ -237,7 +1306,7 @@ static int sd_uhs2_attach(struct mmc_host *host) if (err) goto err; - err = sd_uhs2_init_card(host); + err = sd_uhs2_init_card(host, NULL); if (err) goto err; @@ -254,21 +1323,32 @@ static int sd_uhs2_attach(struct mmc_host *host) goto remove_card; mmc_claim_host(host); + return 0; remove_card: - mmc_remove_card(host->card); - host->card = NULL; + sd_uhs2_remove(host); mmc_claim_host(host); - mmc_detach_bus(host); + err: + mmc_detach_bus(host); sd_uhs2_power_off(host); + host->flags &= ~MMC_UHS2_SUPPORT; return err; } +/** + * mmc_attach_sd_uhs2 - select UHS2 interface + * @host: MMC host + * + * Try to select UHS2 interface and initialize the bus for a given + * frequency, @freq. + * + * Return: 0 on success, non-zero error on failure + */ int mmc_attach_sd_uhs2(struct mmc_host *host) { - int i, err = 0; + int i, err; if (!(host->caps2 & MMC_CAP2_SD_UHS2)) return -EOPNOTSUPP; @@ -283,6 +1363,9 @@ int mmc_attach_sd_uhs2(struct mmc_host *host) */ for (i = 0; i < ARRAY_SIZE(sd_uhs2_freqs); i++) { host->f_init = sd_uhs2_freqs[i]; + pr_info("%s: %s: trying to init UHS-II card at %u Hz\n", + mmc_hostname(host), __func__, host->f_init); + err = sd_uhs2_attach(host); if (!err) break; diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h index 6efec0b9820c..4623651037dd 100644 --- a/include/linux/mmc/core.h +++ b/include/linux/mmc/core.h @@ -23,6 +23,15 @@ enum mmc_blk_status { MMC_BLK_NEW_REQUEST, }; +struct uhs2_command { + u16 header; + u16 arg; + __be32 *payload; + u32 payload_len; + u32 packet_len; + u8 tmode_half_duplex; +}; + struct mmc_command { u32 opcode; u32 arg; @@ -109,6 +118,10 @@ struct mmc_command { unsigned int busy_timeout; /* busy detect timeout in ms */ struct mmc_data *data; /* data segment associated with cmd */ struct mmc_request *mrq; /* associated request */ + + struct uhs2_command *uhs2_cmd; /* UHS2 command */ + u8 *uhs2_resp; /* UHS2 native cmd resp */ + u8 uhs2_resp_len; /* UHS2 native cmd resp len */ }; struct mmc_data { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 240397f1e11d..c300b1cfaf4d 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -126,6 +126,13 @@ struct sd_uhs2_caps { }; enum sd_uhs2_operation { + UHS2_PHY_INIT = 0, + UHS2_SET_CONFIG, + UHS2_ENABLE_INT, + UHS2_DISABLE_INT, + UHS2_ENABLE_CLK, + UHS2_DISABLE_CLK, + UHS2_CHECK_DORMANT, UHS2_SET_IOS, }; @@ -477,6 +484,11 @@ struct mmc_host { #endif #define MMC_CAP2_ALT_GPT_TEGRA (1 << 28) /* Host with eMMC that has GPT entry at a non-standard location */ + int flags; +#define MMC_UHS2_SUPPORT (1 << 0) +#define MMC_UHS2_SD_TRAN (1 << 1) + + bool uhs2_app_cmd; /* Host UHS-II APP Command */ struct sd_uhs2_caps uhs2_caps; /* Host UHS-II capabilities */ int fixed_drv_type; /* fixed driver type for non-removable media */ @@ -729,6 +741,12 @@ static inline void mmc_debugfs_err_stats_inc(struct mmc_host *host, host->err_stats[stat] += 1; } +static inline int mmc_card_uhs2_hd_mode(struct mmc_host *host) +{ + return host->ios.timing == MMC_TIMING_UHS2_SPEED_A_HD || + host->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD; +} + int mmc_sd_switch(struct mmc_card *card, int mode, int group, u8 value, u8 *resp); int mmc_send_status(struct mmc_card *card, u32 *status); int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error); From patchwork Fri Sep 8 09:53:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99FDAEE57EC for ; Fri, 8 Sep 2023 09:54:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236248AbjIHJyc (ORCPT ); Fri, 8 Sep 2023 05:54:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235491AbjIHJyc (ORCPT ); Fri, 8 Sep 2023 05:54:32 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B78B51FC4; Fri, 8 Sep 2023 02:53:58 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1c337aeefbdso17173175ad.0; Fri, 08 Sep 2023 02:53:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166838; x=1694771638; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H2z/7GJr9njJN008aAGR8b5C+FjyiTWMkYOJiGvgSes=; b=Ife/Eg5BZFcrXy+qPELeMM4Lh6X4RLM0gXNDqmA/GxwOwp40YITIXy/A71CYphX/RA MP3phb4gaXihdprIaWTfSdduNF+ZzZQfWAHKbO0B5PPGzHmq43yXA3bJ99uolo+/sp3I /P8HHHedgVRVbbiaQs5ffdJBQQ8jBbZV5PedqsNzr/vwHh93C40EQXInQ/7djMUodd3I YoG0AxfGKmHKDHMzIHxP4bhWF407qgDHWbq5Z/AqM4ctY2BIePsnjBJMqX15ax3NWVEr V4qcIh9VuyidFbZHkmZl6XHx8WbBBYnldpksWnSUxGSgUSI+3xtJQ7uRaDTLjfUIief3 Nkzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166838; x=1694771638; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H2z/7GJr9njJN008aAGR8b5C+FjyiTWMkYOJiGvgSes=; b=M+ybbFWqNK6JgdCg8TsMx9Vt2uMDcrdkur5MBlLhVTEEOEZYyn3vNDZW9ILjFPHwcO WVjgWJrybRkkbgrIuyo04fzdEYh40My6Y31SC8CaNWf1hL0jo375gBd4gCBCDR21LIoI ziNxy8ynMTGEo0o48xZV8vAsMzhXMFzHsMEQd5ygI1V3boime3eGGVrBB1zbVgEX3XiO PPSPAjxmju6zffRxw2+TtMLwRVP1v/QZgax5QuNHQC1BsOLXeKf4crgdpbybju+96RrV j90PKFCSZrSfC3ugIAvIOeQ04vW5ZQ18DNDrzYjT3a7ccmNAIlm3efqUU4VEHdFg1T2w eTCw== X-Gm-Message-State: AOJu0Yxvts7MpAmuN/f/WBSg4VkD/5yTduDzYHJhJSqbq38CiO1StHCj p+Ee3AbnTYqewL0WnQ5fsu4= X-Google-Smtp-Source: AGHT+IEvzNqe+WepHW4Jx5Gs8j8xLwmhBoqQJblRBJv0RUkzteGhNJBeRlQp/J62KdKQSmd8+BazqQ== X-Received: by 2002:a17:902:f80a:b0:1b6:6f12:502e with SMTP id ix10-20020a170902f80a00b001b66f12502emr1842627plb.49.1694166838142; Fri, 08 Sep 2023 02:53:58 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:53:57 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 07/23] mmc: sdhci: add UHS-II related definitions in headers Date: Fri, 8 Sep 2023 17:53:14 +0800 Message-Id: <20230908095330.12075-8-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Add UHS-II related definitions in sdhci.h and sdhci-uhs2.h. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Modify the commit message. Updates in V8: - Use tabs instead of spaces. Updates in V7: - Reorder values and positions of definitions. Updates in V6: - Rename definitions. - Use BIT() GENMASK() instead of bitwise operations. --- drivers/mmc/host/sdhci-uhs2.h | 177 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 54 ++++++++++- 2 files changed, 230 insertions(+), 1 deletion(-) create mode 100644 drivers/mmc/host/sdhci-uhs2.h diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h new file mode 100644 index 000000000000..e993f41ffb7f --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * linux/drivers/mmc/host/sdhci-uhs2.h - Secure Digital Host Controller Interface driver + * + * Header file for Host Controller UHS2 related registers. + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + */ +#ifndef __SDHCI_UHS2_H +#define __SDHCI_UHS2_H + +#include + +/* SDHCI Category C registers : UHS2 usage */ + +#define SDHCI_UHS2_CM_TRAN_RESP 0x10 +#define SDHCI_UHS2_SD_TRAN_RESP 0x18 +#define SDHCI_UHS2_SD_TRAN_RESP_1 0x1C + +/* SDHCI Category B registers : UHS2 only */ + +#define SDHCI_UHS2_BLOCK_SIZE 0x80 +#define SDHCI_UHS2_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF)) + +#define SDHCI_UHS2_BLOCK_COUNT 0x84 + +#define SDHCI_UHS2_CMD_PACKET 0x88 +#define SDHCI_UHS2_CMD_PACK_MAX_LEN 20 + +#define SDHCI_UHS2_TRANS_MODE 0x9C +#define SDHCI_UHS2_TRNS_DMA BIT(0) +#define SDHCI_UHS2_TRNS_BLK_CNT_EN BIT(1) +#define SDHCI_UHS2_TRNS_DATA_TRNS_WRT BIT(4) +#define SDHCI_UHS2_TRNS_BLK_BYTE_MODE BIT(5) +#define SDHCI_UHS2_TRNS_RES_R5 BIT(6) +#define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN BIT(7) +#define SDHCI_UHS2_TRNS_RES_INT_DIS BIT(8) +#define SDHCI_UHS2_TRNS_WAIT_EBSY BIT(14) +#define SDHCI_UHS2_TRNS_2L_HD BIT(15) + +#define SDHCI_UHS2_CMD 0x9E +#define SDHCI_UHS2_CMD_SUB_CMD BIT(2) +#define SDHCI_UHS2_CMD_DATA BIT(5) +#define SDHCI_UHS2_CMD_TRNS_ABORT BIT(6) +#define SDHCI_UHS2_CMD_CMD12 BIT(7) +#define SDHCI_UHS2_CMD_DORMANT GENMASK(7, 6) +#define SDHCI_UHS2_CMD_PACK_LEN_MASK GENMASK(12, 8) + +#define SDHCI_UHS2_RESPONSE 0xA0 +#define SDHCI_UHS2_RESPONSE_MAX_LEN 20 + +#define SDHCI_UHS2_MSG_SELECT 0xB4 +#define SDHCI_UHS2_MSG_SELECT_CURR 0x0 +#define SDHCI_UHS2_MSG_SELECT_ONE 0x1 +#define SDHCI_UHS2_MSG_SELECT_TWO 0x2 +#define SDHCI_UHS2_MSG_SELECT_THREE 0x3 + +#define SDHCI_UHS2_MSG 0xB8 + +#define SDHCI_UHS2_DEV_INT_STATUS 0xBC + +#define SDHCI_UHS2_DEV_SELECT 0xBE +#define SDHCI_UHS2_DEV_SEL_MASK GENMASK(3, 0) +#define SDHCI_UHS2_DEV_SEL_INT_MSG_EN BIT(7) + +#define SDHCI_UHS2_DEV_INT_CODE 0xBF + +#define SDHCI_UHS2_SW_RESET 0xC0 +#define SDHCI_UHS2_SW_RESET_FULL BIT(0) +#define SDHCI_UHS2_SW_RESET_SD BIT(1) + +#define SDHCI_UHS2_TIMER_CTRL 0xC2 +#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK GENMASK(7, 4) + +#define SDHCI_UHS2_INT_STATUS 0xC4 +#define SDHCI_UHS2_INT_STATUS_ENABLE 0xC8 +#define SDHCI_UHS2_INT_SIGNAL_ENABLE 0xCC +#define SDHCI_UHS2_INT_HEADER_ERR BIT(0) +#define SDHCI_UHS2_INT_RES_ERR BIT(1) +#define SDHCI_UHS2_INT_RETRY_EXP BIT(2) +#define SDHCI_UHS2_INT_CRC BIT(3) +#define SDHCI_UHS2_INT_FRAME_ERR BIT(4) +#define SDHCI_UHS2_INT_TID_ERR BIT(5) +#define SDHCI_UHS2_INT_UNRECOVER BIT(7) +#define SDHCI_UHS2_INT_EBUSY_ERR BIT(8) +#define SDHCI_UHS2_INT_ADMA_ERROR BIT(15) +#define SDHCI_UHS2_INT_CMD_TIMEOUT BIT(16) +#define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT BIT(17) +#define SDHCI_UHS2_INT_VENDOR_ERR BIT(27) +#define SDHCI_UHS2_INT_ERROR_MASK ( \ + SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) +#define SDHCI_UHS2_INT_CMD_ERR_MASK ( \ + SDHCI_UHS2_INT_HEADER_ERR | \ + SDHCI_UHS2_INT_RES_ERR | \ + SDHCI_UHS2_INT_FRAME_ERR | \ + SDHCI_UHS2_INT_TID_ERR | \ + SDHCI_UHS2_INT_CMD_TIMEOUT) +/* CRC Error occurs during a packet receiving */ +#define SDHCI_UHS2_INT_DATA_ERR_MASK ( \ + SDHCI_UHS2_INT_RETRY_EXP | \ + SDHCI_UHS2_INT_CRC | \ + SDHCI_UHS2_INT_UNRECOVER | \ + SDHCI_UHS2_INT_EBUSY_ERR | \ + SDHCI_UHS2_INT_ADMA_ERROR | \ + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) + +#define SDHCI_UHS2_SETTINGS_PTR 0xE0 +#define SDHCI_UHS2_GEN_SETTINGS_POWER_LOW BIT(0) +#define SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK GENMASK(11, 8) +#define SDHCI_UHS2_FD_OR_2L_HD 0x0 /* 2 lanes */ +#define SDHCI_UHS2_2D1U_FD 0x2 /* 3 lanes, 2 down, 1 up, full duplex */ +#define SDHCI_UHS2_1D2U_FD 0x3 /* 3 lanes, 1 down, 2 up, full duplex */ +#define SDHCI_UHS2_2D2U_FD 0x4 /* 4 lanes, 2 down, 2 up, full duplex */ + +#define SDHCI_UHS2_PHY_SET_SPEED_B BIT(6) +#define SDHCI_UHS2_PHY_HIBERNATE_EN BIT(12) +#define SDHCI_UHS2_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_PHY_N_LSS_DIR_MASK GENMASK(23, 20) + +#define SDHCI_UHS2_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_TRAN_RETRY_CNT_MASK GENMASK(17, 16) +#define SDHCI_UHS2_TRAN_1_N_DAT_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_CAPS_PTR 0xE2 +#define SDHCI_UHS2_CAPS_OFFSET 0 +#define SDHCI_UHS2_CAPS_DAP_MASK GENMASK(3, 0) +#define SDHCI_UHS2_CAPS_GAP_MASK GENMASK(7, 4) +#define SDHCI_UHS2_CAPS_GAP(gap) ((gap) * 360) +#define SDHCI_UHS2_CAPS_LANE_MASK GENMASK(13, 8) +#define SDHCI_UHS2_CAPS_2L_HD_FD 1 +#define SDHCI_UHS2_CAPS_2D1U_FD 2 +#define SDHCI_UHS2_CAPS_1D2U_FD 4 +#define SDHCI_UHS2_CAPS_2D2U_FD 8 +#define SDHCI_UHS2_CAPS_ADDR_64 BIT(14) +#define SDHCI_UHS2_CAPS_BOOT BIT(15) +#define SDHCI_UHS2_CAPS_DEV_TYPE_MASK GENMASK(17, 16) +#define SDHCI_UHS2_CAPS_DEV_TYPE_RMV 0 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB 1 +#define SDHCI_UHS2_CAPS_DEV_TYPE_EMB_RMV 2 +#define SDHCI_UHS2_CAPS_NUM_DEV_MASK GENMASK(21, 18) +#define SDHCI_UHS2_CAPS_BUS_TOPO_MASK GENMASK(23, 22) +#define SDHCI_UHS2_CAPS_BUS_TOPO_SHIFT 22 +#define SDHCI_UHS2_CAPS_BUS_TOPO_P2P 0 +#define SDHCI_UHS2_CAPS_BUS_TOPO_RING 1 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB 2 +#define SDHCI_UHS2_CAPS_BUS_TOPO_HUB_RING 3 + +#define SDHCI_UHS2_CAPS_PHY_OFFSET 4 +#define SDHCI_UHS2_CAPS_PHY_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_PHY_RANGE_MASK GENMASK(7, 6) +#define SDHCI_UHS2_CAPS_PHY_RANGE_A 0 +#define SDHCI_UHS2_CAPS_PHY_RANGE_B 1 +#define SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK GENMASK(19, 16) +#define SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK GENMASK(23, 20) +#define SDHCI_UHS2_CAPS_TRAN_OFFSET 8 +#define SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK GENMASK(5, 0) +#define SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK GENMASK(15, 8) +#define SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK GENMASK(18, 16) +#define SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK GENMASK(31, 20) + +#define SDHCI_UHS2_CAPS_TRAN_1_OFFSET 12 +#define SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK GENMASK(7, 0) + +#define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 +#define SDHCI_UHS2_VENDOR_PTR 0xE8 + +#endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f219bdea8f28..4f23d54a7557 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -43,8 +43,23 @@ #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 +/* + * Defined in Host Version 4.0. + */ +#define SDHCI_TRNS_RES_TYPE 0x40 +#define SDHCI_TRNS_RES_ERR_CHECK 0x80 +#define SDHCI_TRNS_RES_INT_DIS 0x0100 + #define SDHCI_COMMAND 0x0E #define SDHCI_CMD_RESP_MASK 0x03 + +/* + * Host Version 4.10 adds this bit to distinguish a main command or + * sub command. + * For example with SDIO, CMD52 (sub command) issued during CMD53 (main command). + */ +#define SDHCI_CMD_SUB_CMD 0x04 + #define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_DATA 0x20 @@ -65,6 +80,9 @@ #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT 0x00000001 #define SDHCI_DATA_INHIBIT 0x00000002 + +#define SDHCI_DAT_4_TO_7_LVL_MASK 0x000000F0 + #define SDHCI_DOING_WRITE 0x00000100 #define SDHCI_DOING_READ 0x00000200 #define SDHCI_SPACE_AVAILABLE 0x00000400 @@ -80,6 +98,15 @@ #define SDHCI_DATA_0_LVL_MASK 0x00100000 #define SDHCI_CMD_LVL 0x01000000 +/* Host Version 4.10 */ + +#define SDHCI_HOST_REGULATOR_STABLE 0x02000000 +#define SDHCI_CMD_NOT_ISSUED_ERR 0x08000000 +#define SDHCI_SUB_CMD_STATUS 0x10000000 +#define SDHCI_UHS2_IN_DORMANT_STATE 0x20000000 +#define SDHCI_UHS2_LANE_SYNC 0x40000000 +#define SDHCI_UHS2_IF_DETECT 0x80000000 + #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 @@ -117,7 +144,7 @@ #define SDHCI_CLOCK_CONTROL 0x2C #define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK 0xFF #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 @@ -146,6 +173,10 @@ #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_RETUNE 0x00001000 + +/* Host Version 4.10 */ +#define SDHCI_INT_FX_EVENT 0x00002000 + #define SDHCI_INT_CQE 0x00004000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 @@ -159,6 +190,9 @@ #define SDHCI_INT_AUTO_CMD_ERR 0x01000000 #define SDHCI_INT_ADMA_ERROR 0x02000000 +/* Host Version 4.0 */ +#define SDHCI_INT_RESP_ERR 0x08000000 + #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 @@ -185,6 +219,9 @@ #define SDHCI_AUTO_CMD_END_BIT 0x00000008 #define SDHCI_AUTO_CMD_INDEX 0x00000010 +/* Host Version 4.10 */ +#define SDHCI_AUTO_CMD_RESP_ERR 0x0020 + #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 #define SDHCI_CTRL_UHS_SDR12 0x0000 @@ -193,6 +230,7 @@ #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHS2 0x0007 #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -201,9 +239,12 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHS2_ENABLE 0x0100 +#define SDHCI_CTRL_ADMA2_LEN_MODE 0x0400 #define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -226,11 +267,13 @@ #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_CAPABILITIES_1 0x44 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 #define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_SUPPORT_UHS2 0x00000008 #define SDHCI_DRIVER_TYPE_A 0x00000010 #define SDHCI_DRIVER_TYPE_C 0x00000020 #define SDHCI_DRIVER_TYPE_D 0x00000040 @@ -239,6 +282,7 @@ #define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) #define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) #define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_CAN_VDD2_180 0x10000000 /* UHS-2 1.8V VDD2 */ #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ #define SDHCI_MAX_CURRENT 0x48 @@ -246,11 +290,14 @@ #define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) #define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) #define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) +#define SDHCI_MAX_CURRENT_1 0x4C +#define SDHCI_MAX_CURRENT_VDD2_180_MASK GENMASK(7, 0) /* UHS2 */ #define SDHCI_MAX_CURRENT_MULTIPLIER 4 /* 4C-4F reserved for more max current */ #define SDHCI_SET_ACMD12_ERROR 0x50 +/* Host Version 4.10 */ #define SDHCI_SET_INT_ERROR 0x52 #define SDHCI_ADMA_ERROR 0x54 @@ -269,10 +316,15 @@ #define SDHCI_PRESET_FOR_SDR104 0x6C #define SDHCI_PRESET_FOR_DDR50 0x6E #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ + +/* UHS2 */ +#define SDHCI_PRESET_FOR_UHS2 0x74 #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) #define SDHCI_PRESET_CLKGEN_SEL BIT(10) #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) +#define SDHCI_ADMA3_ADDRESS 0x78 + #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE From patchwork Fri Sep 8 09:53:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377308 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F298FEE57EB for ; Fri, 8 Sep 2023 09:54:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238941AbjIHJy5 (ORCPT ); Fri, 8 Sep 2023 05:54:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235491AbjIHJy5 (ORCPT ); Fri, 8 Sep 2023 05:54:57 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD4931FC1; Fri, 8 Sep 2023 02:54:10 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1c1f8aaab9aso16180855ad.1; Fri, 08 Sep 2023 02:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166841; x=1694771641; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LyPbEFpkzPPO08G39OM8RGCfzkiK36Nkx+lw4uNCZ9o=; b=SuQN7kDqXVQjmUOgASWRtR+gvcJlxsAKrHwJ4giXc/OaGe2NfZD62Gl19dzyL6FAUo ypXelaHCyz13OQI2Jx3jj6NRwW7KG4Hs10+7c/77HtRr10R8ntlMudkWZkPvuTeVHDdQ y4ugohaBcVUM9T9Gjuh7pu/XW0qcLE3A+j1OKIuLV/CkxIWwo+VwSe4Oy7fPlw8uIfkJ mmSFv+3TfLG0MMXc2w/WQWODqx278Rby4L2h5Q5XaJNqsg9slosvZAtTVJ2DE+ZY7uE7 TDIPER3/O6tPFIDHMJ2ziHkEMuHJXt3YJ/H0aNgLisqC5VT7qUxHIukWWiBKMbZdY4yL YDZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166841; x=1694771641; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LyPbEFpkzPPO08G39OM8RGCfzkiK36Nkx+lw4uNCZ9o=; b=FFHVKUoJJMEcKY+Isq3IpfXBv45HnLneDuLZcm9LwYeY3CQuF5rnDG0jTO9UQZW3RL wbBv1abWpN7sfIJCKv5rheCbiuOutSCWvhKPH/feNpLrhS3m8XEiwPOyMbYm662Cgevo FfpRzZkHYoVH5LoERi2cWZxFFK26FDK+fZM+SWKnSM8UnzkW3NPWAwwHkTa+2allL7wC LBZ3EjCXEUulc85OI3ms0qQaVPbak2/ZPA+TZ8WMN+xVjDCWYoh7zDCPWBEcW/G28oZE vzxFkSooHKiraLLxbWPs40yOCmToK+2uk5RPQAc1NuTUYrmUTsfjZoyc6HeZRWpQTlVF hMrQ== X-Gm-Message-State: AOJu0YwzgPz5n3ql3WBjzJFTjAziJGjSXUyqZzOaJHoPS0Fn5VVtknrT TUUDkQsGAWv4jSGNpTMFHEc= X-Google-Smtp-Source: AGHT+IHP3k4F0djgHCV0KSjbzmcdwXYN7MZWLYEunoiw1pglpskgGNXRPs3CEiKknT3s0u5s6gp7tA== X-Received: by 2002:a17:903:11c8:b0:1be:f53c:7d1d with SMTP id q8-20020a17090311c800b001bef53c7d1dmr2637879plh.23.1694166840929; Fri, 08 Sep 2023 02:54:00 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:00 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 08/23] mmc: sdhci: add UHS-II module and add a kernel configuration Date: Fri, 8 Sep 2023 17:53:15 +0800 Message-Id: <20230908095330.12075-9-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This patch adds sdhci-uhs2.c as a module for UHS-II support. This is a skeleton for further development in this patch series. This kernel configuration, CONFIG_MMC_SDHCI_UHS2, will be used in the following commits to indicate UHS-II specific code in sdhci controllers. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Modify the commit message. Updates in V8: - Modify MODULE_LICENSE from "GPL v2" to "GPL". Updates in V6: - Merage V5 of patch[7] and patch[9] in to V6 of patch[8]. --- drivers/mmc/host/Kconfig | 9 +++++++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-uhs2.c | 46 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 drivers/mmc/host/sdhci-uhs2.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 159a3e9490ae..215f1ab011dd 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -98,6 +98,15 @@ config MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER This is the case for the Nintendo Wii SDHCI. +config MMC_SDHCI_UHS2 + tristate "UHS2 support on SDHCI controller" + depends on MMC_SDHCI + help + This option is selected by SDHCI controller drivers that want to + support UHS2-capable devices. + + If you have a controller with this feature, say Y or M here. + config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index a693fa3d3f1c..799f21d1f81f 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_MMC_PXA) += pxamci.o obj-$(CONFIG_MMC_MXC) += mxcmmc.o obj-$(CONFIG_MMC_MXS) += mxs-mmc.o obj-$(CONFIG_MMC_SDHCI) += sdhci.o +obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o sdhci-pci-y += sdhci-pci-core.o sdhci-pci-o2micro.o sdhci-pci-arasan.o \ sdhci-pci-dwc-mshc.o sdhci-pci-gli.o diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c new file mode 100644 index 000000000000..608f8ad5aaed --- /dev/null +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * linux/drivers/mmc/host/sdhci_uhs2.c - Secure Digital Host Controller + * Interface driver + * + * Copyright (C) 2014 Intel Corp, All Rights Reserved. + * Copyright (C) 2020 Genesys Logic, Inc. + * Authors: Ben Chuang + * Copyright (C) 2020 Linaro Limited + * Author: AKASHI Takahiro + */ + +#include + +#include "sdhci.h" +#include "sdhci-uhs2.h" + +#define DRIVER_NAME "sdhci_uhs2" +#define DBG(f, x...) \ + pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) + +/*****************************************************************************\ + * * + * Driver init/exit * + * * +\*****************************************************************************/ + +static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) +{ + return 0; +} + +static int __init sdhci_uhs2_mod_init(void) +{ + return 0; +} +module_init(sdhci_uhs2_mod_init); + +static void __exit sdhci_uhs2_mod_exit(void) +{ +} +module_exit(sdhci_uhs2_mod_exit); + +MODULE_AUTHOR("Intel, Genesys Logic, Linaro"); +MODULE_DESCRIPTION("MMC UHS-II Support"); +MODULE_LICENSE("GPL"); From patchwork Fri Sep 8 09:53:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13233EE57EB for ; Fri, 8 Sep 2023 09:55:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235491AbjIHJzC (ORCPT ); Fri, 8 Sep 2023 05:55:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242472AbjIHJzC (ORCPT ); Fri, 8 Sep 2023 05:55:02 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED7911FE8; Fri, 8 Sep 2023 02:54:13 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1bf092a16c9so16307585ad.0; Fri, 08 Sep 2023 02:54:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166844; x=1694771644; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wVKElK4C2zJzSOfixf3qU5LUkfD56mObdk8BVSuhNg=; b=irL0sq5qsG3Z/KqeWB0Hpg8bo5xxNLb2KMgD5qjxrpuZ96P4imr+e8lWO8+kKHg2MA 8uC++8+41p5o5ygR1R8mBco//Vcx0t2PKOdS/Y4pvEJ9vwtEwDUitn5uffiCT6pLJOhK Uc7MlmrYp6R4zjroLF8fx+MGv9YInIgHptGumJhRNWW3josvoHX1dymEVlz7r/KB/IJ3 iBx00GfrPf3PLOv5D7xEk8tXVOOwlP4Z8liP38lE6mgGwqdvU/ymfuF2Q8r5vZQiUxOL KCj6kLs6Sa0bFPNAf5Ap8+ho+icNUIH0pADhIDXBRY/1B2FMFWALKruaOs3K72H4Iprp JfMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166844; x=1694771644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wVKElK4C2zJzSOfixf3qU5LUkfD56mObdk8BVSuhNg=; b=QjpTeENtxr2uiKIP81p273zm1TWboF0DJLNNXZCBqLV7GazyUyU7EXMneKxvd36+Ny 7oO+z1Ub1PXC+CuRni2J1V2MVxeKl1NQZryRYrp/jJuLfG/m/oDJyl+nyAAiHWHXmm/R T6ft4RIF2Q8dHjuEv5gjjQjWiofzv3NmXe+OyrgNQ0Vf0hqJMsuUWaF0nCBkG9qb9PLT nMiM4PqA3HXSG2isB9sm9HnDbyhZ/tr2m36FawCZOmYPaGyxv0r4F48QQvrRDw/Di+v1 rGBQuP3aoBQcN2ggXVeoJnjmB18QlM0cYZSijkPHGPf0SCBkE7hob3J09/uUWHJwsL7S 73Xw== X-Gm-Message-State: AOJu0Yz71BHDrP4lblQfDFlc3+RtUav2DeeiIV7BwHH5+p2LRRIWzrE2 LJWy/8FfKA6Am8Z4imifaH0= X-Google-Smtp-Source: AGHT+IHyOZUKOk93NxK4+3eawmblPEakimnhNrJolhJFRERmcn4IxwRX0GeRzoDrSoiM9gJ3x0rrWA== X-Received: by 2002:a17:902:c081:b0:1bc:422a:b9fd with SMTP id j1-20020a170902c08100b001bc422ab9fdmr2183856pld.13.1694166843873; Fri, 08 Sep 2023 02:54:03 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:03 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 09/23] mmc: sdhci-uhs2: dump UHS-II registers Date: Fri, 8 Sep 2023 17:53:16 +0800 Message-Id: <20230908095330.12075-10-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Dump UHS-II specific registers, if available, in sdhci_dumpregs() for informative/debugging use. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V7: - Use sdhci_uhs2_mode() to simplify code. Updates in V6: - Remove unnecessary code. --- drivers/mmc/host/sdhci-uhs2.c | 30 ++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 4 ++++ drivers/mmc/host/sdhci.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 4 files changed, 38 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 608f8ad5aaed..e339821d3504 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -18,6 +18,36 @@ #define DRIVER_NAME "sdhci_uhs2" #define DBG(f, x...) \ pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) +#define SDHCI_UHS2_DUMP(f, x...) \ + pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) + +void sdhci_uhs2_dump_regs(struct sdhci_host *host) +{ + if (!(sdhci_uhs2_mode(host))) + return; + + SDHCI_UHS2_DUMP("==================== UHS2 ==================\n"); + SDHCI_UHS2_DUMP("Blk Size: 0x%08x | Blk Cnt: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_BLOCK_SIZE), + sdhci_readl(host, SDHCI_UHS2_BLOCK_COUNT)); + SDHCI_UHS2_DUMP("Cmd: 0x%08x | Trn mode: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_CMD), + sdhci_readw(host, SDHCI_UHS2_TRANS_MODE)); + SDHCI_UHS2_DUMP("Int Stat: 0x%08x | Dev Sel : 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_DEV_INT_STATUS), + sdhci_readb(host, SDHCI_UHS2_DEV_SELECT)); + SDHCI_UHS2_DUMP("Dev Int Code: 0x%08x\n", + sdhci_readb(host, SDHCI_UHS2_DEV_INT_CODE)); + SDHCI_UHS2_DUMP("Reset: 0x%08x | Timer: 0x%08x\n", + sdhci_readw(host, SDHCI_UHS2_SW_RESET), + sdhci_readw(host, SDHCI_UHS2_TIMER_CTRL)); + SDHCI_UHS2_DUMP("ErrInt: 0x%08x | ErrIntEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_STATUS), + sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE)); + SDHCI_UHS2_DUMP("ErrSigEn: 0x%08x\n", + sdhci_readl(host, SDHCI_UHS2_INT_SIGNAL_ENABLE)); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); /*****************************************************************************\ * * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index e993f41ffb7f..2bfe18d29bca 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -174,4 +174,8 @@ #define SDHCI_UHS2_EMBED_CTRL_PTR 0xE6 #define SDHCI_UHS2_VENDOR_PTR 0xE8 +struct sdhci_host; + +void sdhci_uhs2_dump_regs(struct sdhci_host *host); + #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ff41aa56564e..753b251179f2 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -110,6 +110,9 @@ void sdhci_dumpregs(struct sdhci_host *host) } } + if (host->ops->dump_uhs2_regs) + host->ops->dump_uhs2_regs(host); + if (host->ops->dump_vendor_regs) host->ops->dump_vendor_regs(host); diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 4f23d54a7557..43ad3f4b7672 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -720,6 +720,7 @@ struct sdhci_ops { void (*request_done)(struct sdhci_host *host, struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); + void (*dump_uhs2_regs)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS From patchwork Fri Sep 8 09:53:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C45D4EE57EB for ; Fri, 8 Sep 2023 09:55:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229822AbjIHJzm (ORCPT ); Fri, 8 Sep 2023 05:55:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242472AbjIHJzh (ORCPT ); Fri, 8 Sep 2023 05:55:37 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ECF21BEA; Fri, 8 Sep 2023 02:54:45 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bf57366ccdso21392365ad.1; Fri, 08 Sep 2023 02:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166847; x=1694771647; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gT4GYvp7XZLzsi+yWOCwdJmnYZ/3FfZ/O3XhWmznl5k=; b=dXx91g1/sLgw6q65t3r/Vy/0C7b4KtH760RoFEQMl/J+5A89fKD9H0h4rujNRI+0L0 gmsfC+ZxF3z16+JdglZfQYKauSGS+WbbSHv6oaA1pv+ZqFy66blLaiz24F3IESeRgqwL qo4CShu9HbBIIk4siSPCVUTB34NZX9VsY07+FvJdqjw92OC+PKXDa7vijo9aUVhPuKB8 5kZ8/bZHWQtWfY6Kh/AzkRqcxjNTpduidUJyZcQ8QUimm19YtL3Xism80+EPgVZu/WGP WbxWfJW1uU5aCom1RbOGDfr4en6hxdnodEhOtPKqOeuUZ1Byx+npL6GlyKSWCgaEYPb1 CI8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166847; x=1694771647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gT4GYvp7XZLzsi+yWOCwdJmnYZ/3FfZ/O3XhWmznl5k=; b=AALG0QA7k86AVyborUgfpPzNsPhDrSMpRCAYCKyklwpWEt1R6th4r8THjF0xUlXCwE RvR1aETvLjWe2FUbyBERjp6x4u/B3gOlUX6urxaxogJVNkYDnLECa9FHwEQYGGe9P9Da plExeHOLQ/BWrDxEBoN6EBS7vLZTmOXYbN7d1QT4wmRGE/cGeHSvRg/l1XKg+dEBtckA NF7r+K39FiDRkinvptKABG3R/Tns5YAxLI7ATnAv2lzH5M1ORueqxYIEWS65j6KN9yK2 wapmKvUc4uvQCWH30pm0n7BrHGsm82JGnQwL7xfUQBYMfnd4iamQWHF3Kkzh67iAcTY9 DDiQ== X-Gm-Message-State: AOJu0Ywt3Tqf0MrP6NHNn4ZzZFFn5i6aQwKyI1RkuFD+VrgndI7G3QAZ mPMmIK0rPWiHj+3KwE9tmtcESXWNWM8= X-Google-Smtp-Source: AGHT+IH7bwZk4RYDVmXa3pphcU9P4mgjI8SDjl1x2ZvDhcrexLeDvAoTQBMKSIFhfcQUgJIFW7SgPQ== X-Received: by 2002:a17:903:d2:b0:1bb:55be:e198 with SMTP id x18-20020a17090300d200b001bb55bee198mr2067797plc.0.1694166847074; Fri, 08 Sep 2023 02:54:07 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:06 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 10/23] mmc: sdhci-uhs2: add reset function and uhs2_mode function Date: Fri, 8 Sep 2023 17:53:17 +0800 Message-Id: <20230908095330.12075-11-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Sdhci_uhs2_reset() does a UHS-II specific reset operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Adjust the position of matching brackets. Updates in V6: - Remove unnecessary functions and simplify code. --- drivers/mmc/host/sdhci-uhs2.c | 45 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 ++ 2 files changed, 47 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index e339821d3504..dfc80a7f1bad 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -10,7 +10,9 @@ * Author: AKASHI Takahiro */ +#include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -49,6 +51,49 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); +/*****************************************************************************\ + * * + * Low level functions * + * * +\*****************************************************************************/ + +bool sdhci_uhs2_mode(struct sdhci_host *host) +{ + return host->mmc->flags & MMC_UHS2_SUPPORT; +} + +/** + * sdhci_uhs2_reset - invoke SW reset + * @host: SDHCI host + * @mask: Control mask + * + * Invoke SW reset, depending on a bit in @mask and wait for completion. + */ +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) +{ + unsigned long timeout; + u32 val; + + sdhci_writew(host, mask, SDHCI_UHS2_SW_RESET); + + if (mask & SDHCI_UHS2_SW_RESET_FULL) + host->clock = 0; + + /* Wait max 100 ms */ + timeout = 100000; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readw, val, !(val & mask), 10, + timeout, true, host, SDHCI_UHS2_SW_RESET)) { + pr_err("%s: %s: Reset 0x%x never completed.\n", __func__, + mmc_hostname(host->mmc), (int)mask); + pr_err("%s: clean reset bit\n", mmc_hostname(host->mmc)); + sdhci_writeb(host, 0, SDHCI_UHS2_SW_RESET); + return; + } +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); + /*****************************************************************************\ * * * Driver init/exit * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 2bfe18d29bca..8253d50f7852 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -177,5 +177,7 @@ struct sdhci_host; void sdhci_uhs2_dump_regs(struct sdhci_host *host); +bool sdhci_uhs2_mode(struct sdhci_host *host); +void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); #endif /* __SDHCI_UHS2_H */ From patchwork Fri Sep 8 09:53:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67BD1EE57EF for ; Fri, 8 Sep 2023 09:55:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242717AbjIHJzo (ORCPT ); Fri, 8 Sep 2023 05:55:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242702AbjIHJzj (ORCPT ); Fri, 8 Sep 2023 05:55:39 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4794A2120; Fri, 8 Sep 2023 02:54:47 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1c34c9cc9b9so14815525ad.3; Fri, 08 Sep 2023 02:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166850; x=1694771650; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dguUjMOvjRLJariqiYEYbcld50cWoXzcuD1+RCxeUPc=; b=llGJFusiaTJybQJud8L6mIbV1GI4OW35pouhHehNLG2zNdTOH0+djtFWmWXJrHmsdU p6rDFaMlyJt4+ujROI5r1rqLWPqJhnV5gvvW9WQSvAC5Fpbi/nJrPCHkghikH/abIhmW sAuegH9WelNTq45l+D55B6+a6rwg9xwckebL312ifxnw3wI/ozhI13kkIuc3Iihx4Imq kZfCZPNiAB5ApQ4L8HUuQO1l0M4i7xqDOCZQTDfywMGb3JunBg0Fo7fTCh3v/2wTQjZD Zg1fD2GSDw8Nq6S/UvY0p38fFFlP8a7oLoqQa6yhS1tonKMJ49LEvB0e4yA23olFMvBY Ry7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166850; x=1694771650; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dguUjMOvjRLJariqiYEYbcld50cWoXzcuD1+RCxeUPc=; b=T1hB+ai+qafgh1Z35do+GEI3RTKCCnLI5KYROBIVqDYEzd1/6kXjYegaVE79wBFy7k 8sPiZ8pnrssXfmkFkjin39/d05w/ZD9uA0eYafS8AswMrcqrZ4M55aAQBfsrBuZZ4sPl kj2DrUbg2FtBn2W+Sm4MV+IkHLhhA9Jpd3NbHlCe0ibTA7c3i+uVPOTNuo0TvxRssAH2 U5vUDjkBSZ/HyWElD2qdC/wiyxD7W4O0xE7EzsnjL2W82hNs4Ng9htwPa1vThK6sTg/L ERTQ5RHvx1xIawSffn8oV5Hv2SL7/Gw3O6uxX4qo7UL68vdec5ZAga2xmvSHGCi/CvTe 0ZIg== X-Gm-Message-State: AOJu0Yzi2NOHONjx5eFlzTL5+HzyO/A5Gcd54cBbeamcK0Ag4U0k4tCu UjLc0fknHf72S2UkpYi0Rn4YKn4I5ug= X-Google-Smtp-Source: AGHT+IF7LdqVh/AMnlrwmjBripgHBeSlkejbAIfxn2GhZyDP03CZSIkNqrojJBNduNdfLCY9EqwzKw== X-Received: by 2002:a17:902:e80f:b0:1c0:bcbc:d64 with SMTP id u15-20020a170902e80f00b001c0bcbc0d64mr2176994plg.51.1694166849878; Fri, 08 Sep 2023 02:54:09 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:09 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 11/23] mmc: sdhci-uhs2: add set_power() to support vdd2 Date: Fri, 8 Sep 2023 17:53:18 +0800 Message-Id: <20230908095330.12075-12-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a UHS-II version of sdhci's set_power operation. VDD2, as well as VDD, is handled here. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V10: - Move some definitions of PatchV9[05/23] to PatchV10[11/23]. Updates in V9: - Modify annotations in sdhci_get_vdd_value(). Updates in V8: - Adjust the position of matching brackets. - Add the initial value of the pwr in sdhci_uhs2_set_power(). Updates in V7: - Add clear the power reg before setting a new value in sdhci_uhs2_set_power(). - Add MMC_VDD_34_35 case and MMC_VDD_35_36 case in sdhci_get_vdd_value(). - Drop pwr variable in sdhci_get_vdd_value(). Updates in V6: - Add mmc_opt_regulator_set_ocr(). - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 48 +++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 61 +++++++++++++++++++---------------- drivers/mmc/host/sdhci.h | 1 + include/linux/mmc/host.h | 1 + 4 files changed, 83 insertions(+), 28 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index dfc80a7f1bad..fc37a34629c2 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -57,6 +57,13 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * * \*****************************************************************************/ +static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, + struct regulator *supply, + unsigned short vdd_bit) +{ + return IS_ERR_OR_NULL(supply) ? 0 : mmc_regulator_set_ocr(mmc, supply, vdd_bit); +} + bool sdhci_uhs2_mode(struct sdhci_host *host) { return host->mmc->flags & MMC_UHS2_SUPPORT; @@ -94,6 +101,47 @@ void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask) } EXPORT_SYMBOL_GPL(sdhci_uhs2_reset); +static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) +{ + struct mmc_host *mmc = host->mmc; + u8 pwr = 0; + + if (mode != MMC_POWER_OFF) { + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", + mmc_hostname(host->mmc), vdd); + pwr |= SDHCI_VDD2_POWER_180; + } + + if (host->pwr == pwr) + return; + host->pwr = pwr; + + if (pwr == 0) { + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc2, 0); + } else { + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + /* support 1.8v only for now */ + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc2, fls(MMC_VDD_165_195) - 1); + + /* Clear the power reg before setting a new value */ + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + /* vdd first */ + pwr |= SDHCI_POWER_ON; + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + mdelay(5); + + pwr |= SDHCI_VDD2_POWER_ON; + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + mdelay(5); + } +} + /*****************************************************************************\ * * * Driver init/exit * diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 753b251179f2..eca54a16e7fc 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -23,7 +23,7 @@ #include #include #include - +#include #include #include @@ -2061,41 +2061,46 @@ static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); } +unsigned short sdhci_get_vdd_value(unsigned short vdd) +{ + switch (1 << vdd) { + case MMC_VDD_165_195: + /* + * Without a regulator, SDHCI does not support 2.0v + * so we only get here if the driver deliberately + * added the 2.0v range to ocr_avail. Map it to 1.8v + * for the purpose of turning on the power. + */ + case MMC_VDD_20_21: + return SDHCI_POWER_180; + case MMC_VDD_29_30: + case MMC_VDD_30_31: + return SDHCI_POWER_300; + case MMC_VDD_32_33: + case MMC_VDD_33_34: + /* + * 3.4V ~ 3.6V are valid only for those platforms where it's + * known that the voltage range is supported by hardware. + */ + case MMC_VDD_34_35: + case MMC_VDD_35_36: + return SDHCI_POWER_330; + default: + return 0; + } +} +EXPORT_SYMBOL_GPL(sdhci_get_vdd_value); + void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd) { u8 pwr = 0; if (mode != MMC_POWER_OFF) { - switch (1 << vdd) { - case MMC_VDD_165_195: - /* - * Without a regulator, SDHCI does not support 2.0v - * so we only get here if the driver deliberately - * added the 2.0v range to ocr_avail. Map it to 1.8v - * for the purpose of turning on the power. - */ - case MMC_VDD_20_21: - pwr = SDHCI_POWER_180; - break; - case MMC_VDD_29_30: - case MMC_VDD_30_31: - pwr = SDHCI_POWER_300; - break; - case MMC_VDD_32_33: - case MMC_VDD_33_34: - /* - * 3.4 ~ 3.6V are valid only for those platforms where it's - * known that the voltage range is supported by hardware. - */ - case MMC_VDD_34_35: - case MMC_VDD_35_36: - pwr = SDHCI_POWER_330; - break; - default: + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) { WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); - break; } } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 43ad3f4b7672..f3bd558b337f 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -837,6 +837,7 @@ void sdhci_set_power(struct sdhci_host *host, unsigned char mode, void sdhci_set_power_and_bus_voltage(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +unsigned short sdhci_get_vdd_value(unsigned short vdd); void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, unsigned short vdd); int sdhci_get_cd_nogpio(struct mmc_host *mmc); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index c300b1cfaf4d..b2b789a28383 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -363,6 +363,7 @@ struct mmc_pwrseq; struct mmc_supply { struct regulator *vmmc; /* Card power supply */ + struct regulator *vmmc2; /* UHS2 VDD2 power supply */ struct regulator *vqmmc; /* Optional Vccq supply */ struct regulator *vqmmc2; /* Optional supply for phy */ }; From patchwork Fri Sep 8 09:53:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98ED5EE57ED for ; Fri, 8 Sep 2023 09:55:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232766AbjIHJzn (ORCPT ); Fri, 8 Sep 2023 05:55:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242730AbjIHJzk (ORCPT ); Fri, 8 Sep 2023 05:55:40 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 649942123; Fri, 8 Sep 2023 02:54:52 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-56a8794b5adso1400707a12.2; Fri, 08 Sep 2023 02:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166853; x=1694771653; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ei7XNMDznm4gQAPUvGl27pd9IQStOyHk63FGnzmJMW8=; b=FYSUQRk+lKJ0vF1ignrm9aSbGj95BjBRxH198dxBjdOZRqPct2HoXnOlmAJiurPzNr jwQ67rThs5t/hWxXs+ETQJxllNcz0xTs2ioKSy2XQhNGUC75cG3vu7dIch2bKlrp16fw OG/sJb9vVfxQV49t+jemuY+X7JbOrBHNt82ymcLAqvWPmJ0Xunfy/76SzGHn0VtnNi9w 2DYPd4HoUvYgqfEXLDQBEnS/YNi/MCn/ekIYJ6CtRnsyrjsHMTvouexW04x/vUeOzWVB UPW+X/pp7OLeG/Bf0qGjNX6kZYCRFnpBl/j/J3IwdWgK1CVq8Vod6q7A/Ger/kKpCQy/ ap2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166853; x=1694771653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ei7XNMDznm4gQAPUvGl27pd9IQStOyHk63FGnzmJMW8=; b=ao7T4jqdlIUAfYjcdilHxko6loG+7uxDKi6rEMiTCiFy91NZHwacgASnotVB2ANGs2 lOPsK1XYEWBfy/tX0gTicUoWiCsCoYyv/WCB7opQ7T93RESwXtSQV64MI07QHuvC4szw ZdkWWYSE317dv2G8QHebQESkRT/uZqPZOJ+J3k3UobrFan3zZl+/PGHGv/XNM3IyyirT KYJ7a5dmgx6GbwUaF4OGJuoHWPQu02OfjumU7abAEbz9YsJRHv2hoPty381nRYB6ZpOy hxxKcsUa0rdB8FbN7ZurWKBIqls6eNuemdZ4kOdq9HmygOQZJAuPawRaxjjPcP3s7/vk ZjvQ== X-Gm-Message-State: AOJu0YyaHFpByJ0ufpJfIL2J0i+C+pw8Fh8fuBVVUHTwyPGJlQ2dOPiT ocqfx/J5DvMj1mOieOpBrOA= X-Google-Smtp-Source: AGHT+IGblyl8Ovf8J90lX1yyJvr8vPlJRmgbqJvYuuNIWJlUDtZ0BbX6Z0vXbaLmM28ay5a55XPjPg== X-Received: by 2002:a05:6a20:7343:b0:153:6ce7:294d with SMTP id v3-20020a056a20734300b001536ce7294dmr2344261pzc.12.1694166852711; Fri, 08 Sep 2023 02:54:12 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:12 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 12/23] mmc: sdhci-uhs2: skip signal_voltage_switch() Date: Fri, 8 Sep 2023 17:53:19 +0800 Message-Id: <20230908095330.12075-13-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih For UHS2, the signal voltage is supplied by vdd2 which is already 1.8v, so no voltage switch required. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V5: - Use sdhci_uhs2_mode() to simplify code in sdhci_uhs2_start_signal_voltage_switch(). --- drivers/mmc/host/sdhci-uhs2.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index fc37a34629c2..92fb69b7e209 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -142,6 +142,27 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, un } } +/*****************************************************************************\ + * * + * MMC callbacks * + * * +\*****************************************************************************/ + +static int sdhci_uhs2_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + + /* + * For UHS2, the signal voltage is supplied by vdd2 which is + * already 1.8v so no voltage switch required. + */ + if (sdhci_uhs2_mode(host)) + return 0; + + return sdhci_start_signal_voltage_switch(mmc, ios); +} + /*****************************************************************************\ * * * Driver init/exit * @@ -150,6 +171,9 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, un static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_uhs2_start_signal_voltage_switch; + return 0; } From patchwork Fri Sep 8 09:53:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1222EE57EE for ; Fri, 8 Sep 2023 09:55:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242472AbjIHJzo (ORCPT ); Fri, 8 Sep 2023 05:55:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242744AbjIHJzk (ORCPT ); Fri, 8 Sep 2023 05:55:40 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 373792126; Fri, 8 Sep 2023 02:54:53 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1c0d0bf18d7so15075175ad.0; Fri, 08 Sep 2023 02:54:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166855; x=1694771655; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EGi6sD/0z+vEmIB7Q0DnnHWWHQnmVsUVEwzrXdfL/i8=; b=fhGwRTCYJfuWyShcADc3pj+5YZOXDfz6iD5SxI1K9D4tHECvghTYWPCthEkNBCpXTl h1ujBqCiqmpQ5gbjV3BOZcp7xwxHOh1/autZ4YHIqJINBCc2vrj+o8q9aN6wRjUiND3a qGIQOsqTUz45zeC1/G3Q/3ttCKt1NablpRKuG7ab4IpuLT4M6xmgMaVTTUHkYnLILQxh tZrxw3OB9XQIZI5lLwJ/1Lm2gc3943gOU7pnWXf/uGPE+IikU6EzfPf/PSeqCu2sP6BS Inv70UJzgTHTjnLWWv3pByf2ZYKdhvTvqdtC0ZI+jFkSZt4SUX+baRTaMqb8f1Gv2g9R O3Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166855; x=1694771655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EGi6sD/0z+vEmIB7Q0DnnHWWHQnmVsUVEwzrXdfL/i8=; b=hXxBu9hEUrEV84cd6D5NwRngng0KfKg9DW5Q0lN7+OoI5oFCkPA0rwEH0rZ/BEgpgu Hs8aJH68rCiuuqrkzUav0SiZeJqN9r1XX+riS83kJXcKwVskBA2JQo640C2DC5TrW4jK VFbdlHTkryKGh4SfWpWfVmh7PGRvEcdEN+JkqSzJEK8IVg9RXNe/4mWA2j12OCaU0OyG IsEXf2ZAOpTMGodIxcJBTsGfI1RGM+N19TtnbbSAlZ5NuKgZyhrIZhTs3/DA23AJb09s iJB5McUbFxiIixC6xRs6LT60jx9uoANzygOunwEZODHT2UkIwarMHc6xlq75vyi8dcbE KQxA== X-Gm-Message-State: AOJu0Ywug/fArBRlQEoo1p0g/+EQcUNVzTGJocWIw9HHzQH1WlVLKisZ 25konoby2NXmYVAdvQ7UW5I= X-Google-Smtp-Source: AGHT+IE8RyEcnp1rXGaSHnkYDc03w6++JuXIeAcNZfSXI+3J6IRoM9DeEPa4LQaJednOMbcFr78oJw== X-Received: by 2002:a17:902:d710:b0:1bf:3c10:1d70 with SMTP id w16-20020a170902d71000b001bf3c101d70mr1845055ply.6.1694166855428; Fri, 08 Sep 2023 02:54:15 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:15 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 13/23] mmc: sdhci-uhs2: add set_timeout() Date: Fri, 8 Sep 2023 17:53:20 +0800 Message-Id: <20230908095330.12075-14-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a UHS-II version of sdhci's set_timeout() operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Initialization be combined with declaration and realigned in sdhci_calc_timeout_uhs2(). - Forward declare struct mmc_command in sdhci_uhs2.h. Updates in V6: - Use GENMASK() and FIELD_PREP() in some case. - Use sdhci_uhs2_mode() to simplify code. - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 72 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + 2 files changed, 74 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 92fb69b7e209..d519e6ce6199 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -142,6 +143,77 @@ static void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, un } } +static u8 sdhci_calc_timeout_uhs2(struct sdhci_host *host, u8 *cmd_res, u8 *dead_lock) +{ + /* timeout in us */ + unsigned int dead_lock_timeout = 1 * 1000 * 1000; + unsigned int cmd_res_timeout = 5 * 1000; + unsigned int current_timeout; + u8 count; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < cmd_res_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for CMD_RES!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *cmd_res = count; + + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < dead_lock_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for DEADLOCK!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *dead_lock = count; + + return count; +} + +static void __sdhci_uhs2_set_timeout(struct sdhci_host *host) +{ + u8 cmd_res, dead_lock; + + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + cmd_res |= FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); +} + +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) +{ + __sdhci_set_timeout(host, cmd); + + if (sdhci_uhs2_mode(host)) + __sdhci_uhs2_set_timeout(host); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); + /*****************************************************************************\ * * * MMC callbacks * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 8253d50f7852..ccf4e1834c2d 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -175,9 +175,11 @@ #define SDHCI_UHS2_VENDOR_PTR 0xE8 struct sdhci_host; +struct mmc_command; void sdhci_uhs2_dump_regs(struct sdhci_host *host); bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); #endif /* __SDHCI_UHS2_H */ From patchwork Fri Sep 8 09:53:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E3C2EE57ED for ; Fri, 8 Sep 2023 09:55:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242760AbjIHJzq (ORCPT ); Fri, 8 Sep 2023 05:55:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235623AbjIHJzm (ORCPT ); Fri, 8 Sep 2023 05:55:42 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3489B2125; Fri, 8 Sep 2023 02:54:53 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1bdbf10333bso15319335ad.1; Fri, 08 Sep 2023 02:54:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166858; x=1694771658; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f5n3eE3Ata3IyatGkRiLKnqfCiSvDcm1Sfzsxn9YuHc=; b=UPWfNdcchFAOyzCGs51N/bYEXV/T+BtSOXMj/BfRyk9OnV9YUUVnY2E4LrNUxVZpgJ GLswsCMFaTRXtDEquFN0T/cUgkSjfa72Kx0S2fwCiVO2cjvtGZZJn1KFN+qrGDn9+0A+ +iEAvPMTcrFQBodcxG0uzfWWrRRBHM8XR+LLNVDSJxMTRNdNj8sbdPc9mns0Ldh2wC74 QlcPnesMbmSj8OFcCqTT+81LtaCI/COEaBfaLFJqpdMHcsDGzDumcxaC5CPxz+l4K2ZV oyZgL37QOStmEvbI+LJrJAfdI7iP13lS45Yam0sAvJVnDnMNKFGEi7LeksSbSZr1YNbc FSxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166858; x=1694771658; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f5n3eE3Ata3IyatGkRiLKnqfCiSvDcm1Sfzsxn9YuHc=; b=vLQ5ANCflB7U9Axdci0mWehrq2F0M7PrEls8lTLZPZgj05mrl6zwD7XSp8cT+q+AO/ I0kV/UXcIPs2tGMGVm7vvir0wXaFrtApF6xlUGvKrHqZSZP8/FObsspG1yIlgwyZPfY9 uDRGvDfn9SKV6XcZ5GCr3BxQ84MvUm/PNN3vqMOZlAWPmM7haeZR+FwnOEDLBvIrEwAi tzD5xfyNXcuuo3WhDywAN68GuUW9W5CDjWsdK2ZEYqwoTELzDaS5uAjOK40X5OpfXGth O5N1kwdoDXnK4k1cO0otpXABxooh/n7FbeUz2bcRmoT8KMCm4togRQkbVY5m6nsVXiri yiNw== X-Gm-Message-State: AOJu0YyaHosmOXcH4XfKJTVEHrhfI/Pke1NuMsffYgSsAauh3fepQYoG lo71tkYjnvuXA1mnMdNH1o8= X-Google-Smtp-Source: AGHT+IG+P+xqJgTIoHpX+bN9EY0nbD+XWMJI+GANqBnMtPRkFHn0SG9zaVCPgLkb7j0Q5gaSE4+HwA== X-Received: by 2002:a17:902:e547:b0:1c3:6860:121d with SMTP id n7-20020a170902e54700b001c36860121dmr2488338plf.29.1694166858263; Fri, 08 Sep 2023 02:54:18 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:18 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 14/23] mmc: sdhci-uhs2: add set_ios() Date: Fri, 8 Sep 2023 17:53:21 +0800 Message-Id: <20230908095330.12075-15-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a sdhci version of mmc's set_ios operation. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Simplity the turning_on_clk in sdhci_set_ios(). Updates in V8: - Add the judgment formula for MMC_TIMING_SPEED_A_HD, MMC_TIMING_SPEED_B and MMC_TIMING_SPEED_B_HD in __sdhci_uhs2_set_ios(). - Add the switch case for MMC_TIMING_SPEED_A_HD, MMC_TIMING_SPEED_B and MMC_TIMING_SPEED_B_HD in sdhci_get_preset_value(). - mmc_opt_regulator_set_ocr() to instead of mmc_regulator_set_ocr() in sdhci_uhs2_set_ios(). Updates in V7: - Remove unnecessary functions. Updates in V6: - Modify return value in some functions. - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 94 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + drivers/mmc/host/sdhci.c | 55 ++++++++++++-------- drivers/mmc/host/sdhci.h | 2 + 4 files changed, 131 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index d519e6ce6199..ad791c48f681 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -214,6 +214,70 @@ void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) } EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); +/** + * sdhci_uhs2_clear_set_irqs - set Error Interrupt Status Enable register + * @host: SDHCI host + * @clear: bit-wise clear mask + * @set: bit-wise set mask + * + * Set/unset bits in UHS-II Error Interrupt Status Enable register + */ +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) +{ + u32 ier; + + ier = sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE); + ier &= ~clear; + ier |= set; + sdhci_writel(host, ier, SDHCI_UHS2_INT_STATUS_ENABLE); + sdhci_writel(host, ier, SDHCI_UHS2_INT_SIGNAL_ENABLE); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_clear_set_irqs); + +static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + u8 cmd_res, dead_lock; + u16 ctrl_2; + + /* UHS2 Timeout Control */ + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + + /* change to use calculate value */ + cmd_res |= FIELD_PREP(SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK, dead_lock); + + sdhci_uhs2_clear_set_irqs(host, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT, + 0); + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); + sdhci_uhs2_clear_set_irqs(host, 0, + SDHCI_UHS2_INT_CMD_TIMEOUT | + SDHCI_UHS2_INT_DEADLOCK_TIMEOUT); + + /* UHS2 timing. Note, UHS2 timing is disabled when powering off */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ios->timing == MMC_TIMING_UHS2_SPEED_A || + ios->timing == MMC_TIMING_UHS2_SPEED_A_HD || + ios->timing == MMC_TIMING_UHS2_SPEED_B || + ios->timing == MMC_TIMING_UHS2_SPEED_B_HD) + ctrl_2 |= SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE; + else + ctrl_2 &= ~(SDHCI_CTRL_UHS2 | SDHCI_CTRL_UHS2_ENABLE); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + host->timing = ios->timing; + + if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) + sdhci_enable_preset_value(host, true); + + if (host->ops->set_power) + host->ops->set_power(host, ios->power_mode, ios->vdd); + else + sdhci_uhs2_set_power(host, ios->power_mode, ios->vdd); + + sdhci_set_clock(host, host->clock); +} + /*****************************************************************************\ * * * MMC callbacks * @@ -235,6 +299,36 @@ static int sdhci_uhs2_start_signal_voltage_switch(struct mmc_host *mmc, return sdhci_start_signal_voltage_switch(mmc, ios); } +static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + + pr_debug("%s: clock %uHz powermode %u Vdd %u timing %u\n", + mmc_hostname(mmc), ios->clock, ios->power_mode, ios->vdd, ios->timing); + + if (!sdhci_uhs2_mode(host)) { + sdhci_set_ios(mmc, ios); + return 0; + } + + if (ios->power_mode == MMC_POWER_UNDEFINED) + return 0; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (ios->power_mode == MMC_POWER_OFF) { + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + mmc_opt_regulator_set_ocr(mmc, mmc->supply.vmmc2, 0); + } + return -1; + } + + sdhci_set_ios_common(mmc, ios); + + __sdhci_uhs2_set_ios(mmc, ios); + + return 0; +} + /*****************************************************************************\ * * * Driver init/exit * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index ccf4e1834c2d..a3641c5f8c77 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -181,5 +181,6 @@ void sdhci_uhs2_dump_regs(struct sdhci_host *host); bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); +void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index eca54a16e7fc..57209accbb03 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -47,8 +47,6 @@ static unsigned int debug_quirks = 0; static unsigned int debug_quirks2; -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); - static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_dumpregs(struct sdhci_host *host) @@ -1877,6 +1875,12 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host) case MMC_TIMING_MMC_HS400: preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); break; + case MMC_TIMING_UHS2_SPEED_A: + case MMC_TIMING_UHS2_SPEED_A_HD: + case MMC_TIMING_UHS2_SPEED_B: + case MMC_TIMING_UHS2_SPEED_B_HD: + preset = sdhci_readw(host, SDHCI_PRESET_FOR_UHS2); + break; default: pr_warn("%s: Invalid UHS-I mode selected\n", mmc_hostname(host->mmc)); @@ -2323,24 +2327,9 @@ static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_i (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type); } -void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios) { struct sdhci_host *host = mmc_priv(mmc); - bool reinit_uhs = host->reinit_uhs; - bool turning_on_clk = false; - u8 ctrl; - - host->reinit_uhs = false; - - if (ios->power_mode == MMC_POWER_UNDEFINED) - return; - - if (host->flags & SDHCI_DEVICE_DEAD) { - if (!IS_ERR(mmc->supply.vmmc) && - ios->power_mode == MMC_POWER_OFF) - mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); - return; - } /* * Reset the chip on each power off. @@ -2357,8 +2346,6 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_enable_preset_value(host, false); if (!ios->clock || ios->clock != host->clock) { - turning_on_clk = ios->clock && !host->clock; - host->ops->set_clock(host, ios->clock); host->clock = ios->clock; @@ -2374,6 +2361,31 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) mmc->max_busy_timeout /= host->timeout_clk; } } +} +EXPORT_SYMBOL_GPL(sdhci_set_ios_common); + +void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + bool reinit_uhs = host->reinit_uhs; + bool turning_on_clk; + u8 ctrl; + + host->reinit_uhs = false; + + if (ios->power_mode == MMC_POWER_UNDEFINED) + return; + + if (host->flags & SDHCI_DEVICE_DEAD) { + if (!IS_ERR(mmc->supply.vmmc) && + ios->power_mode == MMC_POWER_OFF) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + return; + } + + turning_on_clk = ios->clock != host->clock && ios->clock && !host->clock; + + sdhci_set_ios_common(mmc, ios); if (host->ops->set_power) host->ops->set_power(host, ios->power_mode, ios->vdd); @@ -2957,7 +2969,7 @@ int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) } EXPORT_SYMBOL_GPL(sdhci_execute_tuning); -static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) { /* Host Controller v3.00 defines preset value registers */ if (host->version < SDHCI_SPEC_300) @@ -2985,6 +2997,7 @@ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) host->preset_enabled = enable; } } +EXPORT_SYMBOL_GPL(sdhci_enable_preset_value); static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f3bd558b337f..03d29423a678 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -847,6 +847,8 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); From patchwork Fri Sep 8 09:53:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377316 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 937F7EE57EC for ; Fri, 8 Sep 2023 09:55:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237492AbjIHJzr (ORCPT ); Fri, 8 Sep 2023 05:55:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241279AbjIHJzm (ORCPT ); Fri, 8 Sep 2023 05:55:42 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 410262127; Fri, 8 Sep 2023 02:54:53 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1c0d0bf18d7so15075685ad.0; Fri, 08 Sep 2023 02:54:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166861; x=1694771661; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pGB6aEfT29O/np/vugEtzabJh26wlJ/7P9M9FZXoZFU=; b=f4NVmaf6y5cvYwLMG0y6PwFn3Mb4ZAF/BhdCe6dWggf5LWuVg4MZV2JTvA4uT7gGxq LcaGgK71wND94zxEZm9W8D8Bkv1RjPnbYy0mBv1Sn0ULzCKJBzHlB6jSDl8gOnGcNnQ0 HVHJ78m141Aw+P+I+m73HjgTkBLSOfoCZmtDROqsFmFYvFo0aJlDvglrhJ4fUc0t4U3H F3iCvoPNnvOzVYQ5pgA2JtY8MrbXFInk4mUA7I8tfNBHNi5sBBRBXdug7YAjbuOisfB6 +02Sf8+4Ws5hZTb2NJA5/yQSl4puUEfZ1ef/dKZ9PV7VFBzg9MEOHXiakNMm27WSkOq+ EiqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166861; x=1694771661; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pGB6aEfT29O/np/vugEtzabJh26wlJ/7P9M9FZXoZFU=; b=UuXpiyiCjOLf0aJQZLJK+SAjG3RjPk8cF6VUuwZDyU1NjnuMaSEbbjEgBqiNYO4C/h uojmM+9aTdIMezrpQUuZTG9w9e8QgrDgAj/kljaku+4Yg8k6cC25QtpvY3Kj7ZZLZG9x +Rrsgfg5hsVk26JKDiBXE7jt1jTxyHdRETWtLLgmxuEp5qMCYXOoeMWP0wpZdMtkpCzf fvm6KHpJ6CoCChsVfyHp1ix0oEWyvvcShfkBJFbU2xh3MGm2IAx5Xdxvy6COW7xvuQSb NNdo2YT1Nuhjgcd7nund98sG7mu2vn/M58SI7giCphGLPND7URAmHFoCEFxX3+UyTktv g9FA== X-Gm-Message-State: AOJu0Yy5uEaGMIfaCrHtMnGdOoAxSQahPRI2nuxVnp4lI3uTdSkjMJpS SFE51H6QeqFBSst3qrkdFNU= X-Google-Smtp-Source: AGHT+IHekJLrSh99CoK7ufa11hWTAENrAfgmOOY1PQAuxFVyJ9ggCoBxgR6c69SvBJdN4XaDI8zUSw== X-Received: by 2002:a17:902:e74f:b0:1c3:4565:21a with SMTP id p15-20020a170902e74f00b001c34565021amr2684085plf.49.1694166861070; Fri, 08 Sep 2023 02:54:21 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:20 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 15/23] mmc: sdhci-uhs2: add detect_init() to detect the interface Date: Fri, 8 Sep 2023 17:53:22 +0800 Message-Id: <20230908095330.12075-16-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Sdhci_uhs2_do_detect_init() is a sdhci version of mmc's uhs2_detect_init operation. After detected, the host's UHS-II capabilities will be set up here and interrupts will also be enabled. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - usleep_range() to instead of udelay() in sdhci_uhs2_interface_detect(). - read_poll_timeout() to instead of read_poll_timeout_atomic() in sdhci_uhs2_interface_detect(). - Modify return value in sdhci_uhs2_do_detect_init(). Updates in V7: - Drop using uhs2_reset ops and use sdhci_uhs2_reset() in sdhci_uhs2_do_detect_init(). Updates in V6: - Remove unnecessary functions. - Wrap at 100 columns in some functions. --- drivers/mmc/host/sdhci-uhs2.c | 112 ++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index ad791c48f681..4c2a56629ab3 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -335,6 +335,118 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) * * \*****************************************************************************/ +static int sdhci_uhs2_interface_detect(struct sdhci_host *host) +{ + int timeout = 100000; /* 100ms */ + u32 val; + + usleep_range(50, 200); /* wait for 50us - 200us before check */ + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + /* Enable UHS2 error interrupts */ + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + + /* 150ms */ + timeout = 150000; + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + + DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n", + mmc_hostname(host->mmc)); + return 0; +} + +static int sdhci_uhs2_init(struct sdhci_host *host) +{ + u16 caps_ptr = 0; + u32 caps_gen = 0; + u32 caps_phy = 0; + u32 caps_tran[2] = {0, 0}; + struct mmc_host *mmc = host->mmc; + + caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR); + if (caps_ptr < 0x100 || caps_ptr > 0x1FF) { + pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n", + mmc_hostname(mmc), caps_ptr); + return -ENODEV; + } + caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); + caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); + caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET); + caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET); + + /* General Caps */ + mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK; + mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen); + mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen); + mmc->uhs2_caps.addr64 = (caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0; + mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen); + + /* PHY Caps */ + mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK; + mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy); + mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy); + mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy); + if (mmc->uhs2_caps.n_lss_sync == 0) + mmc->uhs2_caps.n_lss_sync = 16 << 2; + else + mmc->uhs2_caps.n_lss_sync <<= 2; + if (mmc->uhs2_caps.n_lss_dir == 0) + mmc->uhs2_caps.n_lss_dir = 16 << 3; + else + mmc->uhs2_caps.n_lss_dir <<= 3; + + /* LINK/TRAN Caps */ + mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK; + mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]); + if (mmc->uhs2_caps.n_fcu == 0) + mmc->uhs2_caps.n_fcu = 256; + mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]); + mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]); + mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK; + + return 0; +} + +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + + DBG("Begin do uhs2 detect init.\n"); + + if (sdhci_uhs2_interface_detect(host)) { + pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + if (sdhci_uhs2_init(host)) { + pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc)); + return -EIO; + } + + /* Init complete, do soft reset and enable UHS2 error irqs. */ + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK); + /* + * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared + * by SDHCI_UHS2_SW_RESET_SD + */ + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + + return 0; +} + static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch = From patchwork Fri Sep 8 09:53:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377314 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96FA7EE57EB for ; Fri, 8 Sep 2023 09:55:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242748AbjIHJzp (ORCPT ); Fri, 8 Sep 2023 05:55:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242689AbjIHJzm (ORCPT ); Fri, 8 Sep 2023 05:55:42 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 924591FC1; Fri, 8 Sep 2023 02:54:55 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-56b2e689828so1405597a12.1; Fri, 08 Sep 2023 02:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166864; x=1694771664; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=foX0JP3DAWSOOC0u2+6IXCRMxX6qZKC8TnZGDqevErY=; b=JvblvJO2QJUV7r4NQgDUYNSD+47AiN24MARFBeFcvbmtjt6DF2miVIkhhPTB86G2A5 JlwOBQY5m/CTNqKI5B+s5Qyry9nZ+4KoGNEiCchABnSw2AI/4OddEP8ffzUbQ3QCkEHf KaoNsngL7EzAWkbiOrdGCYPF9QfwGAmZkgIXQb/NXrSTv90lIkp2OuOZS51l1EYOe8lL SdLFcyLuQOtYYmqU7B7/qryKTovKKk0mRYcqxlfMLgD/AJhaPgg+yYcnjLxRu/mruRLC fTDFp4l5b7rLN+QDLaFc1GZ3n39kLSiIw04lLZ19CZ9xLXEMwxw+5bQOhObgWH6Ae4U/ rHyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166864; x=1694771664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=foX0JP3DAWSOOC0u2+6IXCRMxX6qZKC8TnZGDqevErY=; b=fjbvRXFQ83+a/6olmj6pHp604Aw4yJSNxTbcBvHODI8k6NuGEaDtVq8l7YsnQwiDPC YQXd9rQQWEFItT8caL1FkE2t6/WxbyVdt2Gg/3MMx9Ffl+M1UL+y3p/fk9pjELBXQY/W rYTXic6McO2MUL2RBoOEgdb/M5Boe4lD2Tb0T/oVQpo6H6FvH7Mlm8UMWYWJ+jd+LP3e AUYIWsPckRkBSELfWBJcHjNBuqPTHfz/TTOShw26ECHUmJDiSQP4GiKYquLKXI5IPsN6 8ZxQJ9yh24muXNFstL2ynMZOtKChiXjRAzT6xc0hsB34OhtLgKhTMrsoL3M7wK4hb4/N q7ww== X-Gm-Message-State: AOJu0Yyb3LdhhpF2rqhr3nMqCPf9jCKGVC6kY2riaboWZ2PUxr3sOh6d Xbz+k2+87O4aJxWxVX5UcVHY6VWiPhA= X-Google-Smtp-Source: AGHT+IG2+kS4vtZmgB9s3/RN3rs15QAraRpLAZKbDv3xIsOai3UHoeLRNmbLMEKzs5ddn1d0CnxwtQ== X-Received: by 2002:a05:6a20:ce83:b0:134:4f86:7990 with SMTP id if3-20020a056a20ce8300b001344f867990mr2141584pzb.3.1694166864095; Fri, 08 Sep 2023 02:54:24 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:23 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 16/23] mmc: sdhci-uhs2: add clock operations Date: Fri, 8 Sep 2023 17:53:23 +0800 Message-Id: <20230908095330.12075-17-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Remove unnecessary include file. - read_poll_timeout() to instead of read_poll_timeout_atomic() in sdhci_uhs2_enable_clk(). - Put the comment on the end and put the lines in descending line length in sdhci_uhs2_enable_clk(). - Modify return value in sdhci_uhs2_enable_clk(). Updates in V6: - Remove unnecessary functions. --- drivers/mmc/host/sdhci-uhs2.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 4c2a56629ab3..af1b0c5e48fd 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -329,6 +329,36 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) return 0; } +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + return 0; +} + +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + int timeout_us = 20000; /* 20ms */ + u32 val; + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE), + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + /*****************************************************************************\ * * * Driver init/exit * From patchwork Fri Sep 8 09:53:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A3C5EE57EE for ; Fri, 8 Sep 2023 09:55:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242730AbjIHJzs (ORCPT ); Fri, 8 Sep 2023 05:55:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241168AbjIHJzn (ORCPT ); Fri, 8 Sep 2023 05:55:43 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B831FE2; Fri, 8 Sep 2023 02:54:56 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1bf6ea270b2so14103425ad.0; Fri, 08 Sep 2023 02:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166867; x=1694771667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AI2qWA9XhDl3lpIqedIzHA9EWnR4IN8BpGre5NF9u4c=; b=QcT5Eki/DHWri2v+DaklJq/zLxu1R7Ho+ajJTBXyFRFFIeACUdpbUfim64/WXBPTPv Y6ejSzazHZFI2sBFx2WvWJDvct4HvKdSq01FpvuekIev8Ii8GzjEdyJo7w8u8buXdX8W xJtPCdZR7WALLicZwZv4I2Vi1ET9ihZXPdtCQgNfMhudi0zxGojGPRT8tK0Ym5SJnnv+ j6rVBWWy8DjNMVpbn/DAKWa6DOkSKChdzTsNorWfxgEgDDp+HIc/+Uk3scJq9LDdVoYe DRb6fYUrMOcp/gDJaBqF3nFhj3JTSfO8w10vgQMALamMYjcsSRuXgEMS4z9Fl2A9wjWA lkoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166867; x=1694771667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AI2qWA9XhDl3lpIqedIzHA9EWnR4IN8BpGre5NF9u4c=; b=YZVLuIu7Rolu/7Shak35zVFRxOTkjmubPrYIIZ/R2zGLmDGhe97zvWCXq3C5CUYu6Q WNvUAyElu0uBDx5ag/ePEzbbGB40hE1iOPJRs8hHuq9jvuLPmklrpawCFSdSOXqOFiC8 QXG1cS3UjWaLnSd0dhJ7osXE+mfmdmK6mEEwJkWj9fxzzcSsdcF5AP5+L07XBIB9QoG3 xwgcMkSej6mQTHRlGvnT8IVIWK7j3DhmE/UY2kMY9Oqb+R1MWzedzz/AxlSmZ234H21a cZRXPb+EY6TnlQvyX9tUVh9GKHjGKa9eSYDQB1xGhFlCGgCEicBQkZXRnKJAdXAML2YE Ng8Q== X-Gm-Message-State: AOJu0YxzweIYi+eCCtpm0XcxWjANs9wcZrU0j7qBLnaQVjMsyF5hWTxJ olk7NEAjfSErdbm4TeyL7cg= X-Google-Smtp-Source: AGHT+IF8sjO4rVxj9E595Tp6TVo8pedM5wQ8FHngX3sGT4HsOpwjZpKUh9uWxed407XS6sD2cDfABw== X-Received: by 2002:a17:902:e54b:b0:1b9:f7f4:5687 with SMTP id n11-20020a170902e54b00b001b9f7f45687mr2693013plf.24.1694166866847; Fri, 08 Sep 2023 02:54:26 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:26 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 17/23] mmc: sdhci-uhs2: add uhs2_control() to initialise the interface Date: Fri, 8 Sep 2023 17:53:24 +0800 Message-Id: <20230908095330.12075-18-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a sdhci version of mmc's uhs2_set_reg operation. UHS-II interface (related registers) will be initialised here. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Reorder the definitions and lose the parentheses in sdhci_uhs2_set_config(). - read_poll_timeout() to instead of read_poll_timeout_atomic() in sdhci_uhs2_check_dormant(). Updates in V7: - Remove unnecessary function. Updates in V6: - Remove unnecessary function. - Remove unnecessary parameter when call the DBG(). - Cancel export state of some functions. --- drivers/mmc/host/sdhci-uhs2.c | 88 +++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index af1b0c5e48fd..09b86fec9f7b 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -278,6 +278,48 @@ static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) sdhci_set_clock(host, host->clock); } +static void sdhci_uhs2_set_config(struct sdhci_host *host) +{ + u32 value; + u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR); + u16 sdhci_uhs2_gen_set_reg = sdhci_uhs2_set_ptr; + u16 sdhci_uhs2_phy_set_reg = sdhci_uhs2_set_ptr + 4; + u16 sdhci_uhs2_tran_set_reg = sdhci_uhs2_set_ptr + 8; + u16 sdhci_uhs2_tran_set_1_reg = sdhci_uhs2_set_ptr + 12; + + /* Set Gen Settings */ + value = FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs2_caps.n_lanes_set); + sdhci_writel(host, value, sdhci_uhs2_gen_set_reg); + + /* Set PHY Settings */ + value = FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.n_lss_dir_set) | + FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_sync_set); + if (host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B || + host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD) + value |= SDHCI_UHS2_PHY_SET_SPEED_B; + sdhci_writel(host, value, sdhci_uhs2_phy_set_reg); + + /* Set LINK-TRAN Settings */ + value = FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps.max_retry_set) | + FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set); + sdhci_writel(host, value, sdhci_uhs2_tran_set_reg); + sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_set_1_reg); +} + +static int sdhci_uhs2_check_dormant(struct sdhci_host *host) +{ + int timeout = 100000; /* 100ms */ + u32 val; + + if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STATE), + 100, timeout, true, host, SDHCI_PRESENT_STATE)) { + pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return -EIO; + } + return 0; +} + /*****************************************************************************\ * * * MMC callbacks * @@ -359,6 +401,51 @@ static int sdhci_uhs2_enable_clk(struct mmc_host *mmc) return 0; } +static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc); + +static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct mmc_ios *ios = &mmc->ios; + int err = 0; + + DBG("Begin uhs2 control, act %d.\n", op); + + switch (op) { + case UHS2_PHY_INIT: + err = sdhci_uhs2_do_detect_init(mmc); + break; + case UHS2_SET_CONFIG: + sdhci_uhs2_set_config(host); + break; + case UHS2_ENABLE_INT: + sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT); + break; + case UHS2_DISABLE_INT: + sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0); + break; + case UHS2_CHECK_DORMANT: + err = sdhci_uhs2_check_dormant(host); + break; + case UHS2_DISABLE_CLK: + err = sdhci_uhs2_disable_clk(mmc); + break; + case UHS2_ENABLE_CLK: + err = sdhci_uhs2_enable_clk(mmc); + break; + case UHS2_SET_IOS: + err = sdhci_uhs2_set_ios(mmc, ios); + break; + default: + pr_err("%s: input sd uhs2 operation %d is wrong!\n", + mmc_hostname(host->mmc), op); + err = -EIO; + break; + } + + return err; +} + /*****************************************************************************\ * * * Driver init/exit * @@ -481,6 +568,7 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) { host->mmc_host_ops.start_signal_voltage_switch = sdhci_uhs2_start_signal_voltage_switch; + host->mmc_host_ops.uhs2_control = sdhci_uhs2_control; return 0; } From patchwork Fri Sep 8 09:53:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5132EE57EB for ; Fri, 8 Sep 2023 09:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240856AbjIHJzu (ORCPT ); Fri, 8 Sep 2023 05:55:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242752AbjIHJzq (ORCPT ); Fri, 8 Sep 2023 05:55:46 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2858D1FDA; Fri, 8 Sep 2023 02:54:58 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1bf078d5f33so16882015ad.3; Fri, 08 Sep 2023 02:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166870; x=1694771670; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gtYlqqhFqFVYtFkprm2YqdLZmUEybK65Y+HMJZYF/mo=; b=O6CYGiMlZGuR3QsB3XezLp5zGhr4Fugemm8ZolJBAPxRL+qfWmvZKJg3GsTHvezAHc h/7zYy0VeAZG/s5BUvvHdevJFBewinjdprih9MAVQ6hK97koRjroLLuQj1sjFG7QSxMW 4+8dcoh2vqcoRQD/Fy3gcDP5grsC3LykBlT4YwCUnryXhPKjywMatW1mJxRc1xRrGrSK xXCErgfvRTok8uEMGx0jSgdvusZMrTuZ3/K67uC9GPVJ9+etIub9K0ganobKK+WlGthb xB/RFdHM/TXsFNhhjvZaye3MDaeqk18XGWcA1HhAc1MeVnF8V555Kc2Mw3g1fDV73Dg1 yMJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166870; x=1694771670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gtYlqqhFqFVYtFkprm2YqdLZmUEybK65Y+HMJZYF/mo=; b=X1sBPCeF1SunEB3DYVJI2zYEQ+LXHlw+k4EY7VSTQ/AEuCNQvL37RD3xqVtl2uoMIT CfvWTRfDem0iyT3k9wTmjKqLF79/sSMjGjqNeqXcsWJMhSozuxs1U0SSQkE3lcqNdya9 hBNsK7HQIt0cEVhP9eXglfbciJfdKN818OWGsRPYMxsPuemw7//7vnqWuaZawVX+5mt0 3R4706mRNDi4ozaIr9h9i1gIUbNdhKm/5w8H9iRNBrP0SBwx7QAuII5AmAhWQ7+23r3D jgxtatkDlgLI+YRZrR/NhPSFAxtP5FB/OJLuAubFXLywstPpAuapo8XkSnOrPQr9s7EW 4oRw== X-Gm-Message-State: AOJu0YwQjiR35u2aKSKH8VTKBHZ9WALEy+/lPHV5iBcvtqhtLtTmeY42 jeYSNVEoOMzKWOo4z3uSnqg= X-Google-Smtp-Source: AGHT+IFbfv+jUHWgJ11B3AJz1BvcnY4wMwqYAddnIfIzl0T8ajhBaQkPd/NrzFtA9aMEKZPYqQYurg== X-Received: by 2002:a17:902:e88e:b0:1c3:4565:22f with SMTP id w14-20020a170902e88e00b001c34565022fmr2401483plg.21.1694166869727; Fri, 08 Sep 2023 02:54:29 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:29 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 18/23] mmc: sdhci-uhs2: add request() and others Date: Fri, 8 Sep 2023 17:53:25 +0800 Message-Id: <20230908095330.12075-19-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a sdhci version of mmc's request operation. It covers both UHS-I and UHS-II. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih --- Updates in V11: - Drop the check mmc_card_uhs2_hd_mode(host->mmc) in sdhci_uhs2_set_transfer_mode(). Updates in V10: - Use tmode_half_duplex to instead of uhs2_tmode0_flag in sdhci_uhs2_set_transfer_mode(). Updates in V9: - Modify the annotations in __sdhci_uhs2_send_command(). Updates in V8: - Adjust the position of matching brackets in sdhci_uhs2_send_command_retry(). - Modify CameCase definition in __sdhci_uhs2_finish_command(). - Modify error message in __sdhci_uhs2_finish_command(). - sdhci_uhs2_send_command_retry() to instead of sdhci_uhs2_send_command() in sdhci_uhs2_request(). - Use sdhci_uhs2_mode() to simplify code in sdhci_uhs2_request_atomic(). - Add forward declaration for sdhci_send_command(). Updates in V7: - Cancel export state of some functions. - Remove unnecessary whitespace changes. Updates in V6: - Add uhs2_dev_cmd() to simplify code. - Remove unnecessary functions. - Cancel export state of some functions. - Drop use CONFIG_MMC_DEBUG(). - Wrap at 100 columns in some functions. --- drivers/mmc/host/sdhci-uhs2.c | 412 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.c | 49 ++-- drivers/mmc/host/sdhci.h | 8 + 3 files changed, 454 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 09b86fec9f7b..1f8d527424fd 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -24,6 +26,8 @@ #define SDHCI_UHS2_DUMP(f, x...) \ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) +#define UHS2_ARG_IOADR_MASK 0xfff + void sdhci_uhs2_dump_regs(struct sdhci_host *host) { if (!(sdhci_uhs2_mode(host))) @@ -58,6 +62,11 @@ EXPORT_SYMBOL_GPL(sdhci_uhs2_dump_regs); * * \*****************************************************************************/ +static inline u16 uhs2_dev_cmd(struct mmc_command *cmd) +{ + return be16_to_cpu((__be16)cmd->uhs2_cmd->arg) & UHS2_ARG_IOADR_MASK; +} + static inline int mmc_opt_regulator_set_ocr(struct mmc_host *mmc, struct regulator *supply, unsigned short vdd_bit) @@ -446,6 +455,408 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op) return err; } +/*****************************************************************************\ + * * + * Core functions * + * * +\*****************************************************************************/ + +static void sdhci_uhs2_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) +{ + struct mmc_data *data = cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); + + sdhci_writew(host, data->blksz, SDHCI_UHS2_BLOCK_SIZE); + sdhci_writew(host, data->blocks, SDHCI_UHS2_BLOCK_COUNT); +} + +static void sdhci_uhs2_finish_data(struct sdhci_host *host) +{ + struct mmc_data *data = host->data; + + __sdhci_finish_data_common(host); + + __sdhci_finish_mrq(host, data->mrq); +} + +static void sdhci_uhs2_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) +{ + u16 mode; + struct mmc_data *data = cmd->data; + + if (!data) { + /* clear Auto CMD settings for no data CMDs */ + if (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_TRANS_ABORT) { + mode = 0; + } else { + mode = sdhci_readw(host, SDHCI_UHS2_TRANS_MODE); + if (cmd->opcode == MMC_STOP_TRANSMISSION || cmd->opcode == MMC_ERASE) + mode |= SDHCI_UHS2_TRNS_WAIT_EBSY; + else + /* send status mode */ + if (cmd->opcode == MMC_SEND_STATUS) + mode = 0; + } + + DBG("UHS2 no data trans mode is 0x%x.\n", mode); + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + return; + } + + WARN_ON(!host->data); + + mode = SDHCI_UHS2_TRNS_BLK_CNT_EN | SDHCI_UHS2_TRNS_WAIT_EBSY; + if (data->flags & MMC_DATA_WRITE) + mode |= SDHCI_UHS2_TRNS_DATA_TRNS_WRT; + + if (data->blocks == 1 && + data->blksz != 512 && + cmd->opcode != MMC_READ_SINGLE_BLOCK && + cmd->opcode != MMC_WRITE_BLOCK) { + mode &= ~SDHCI_UHS2_TRNS_BLK_CNT_EN; + mode |= SDHCI_UHS2_TRNS_BLK_BYTE_MODE; + } + + if (host->flags & SDHCI_REQ_USE_DMA) + mode |= SDHCI_UHS2_TRNS_DMA; + + if (cmd->uhs2_cmd->tmode_half_duplex) + mode |= SDHCI_UHS2_TRNS_2L_HD; + + sdhci_writew(host, mode, SDHCI_UHS2_TRANS_MODE); + + DBG("UHS2 trans mode is 0x%x.\n", mode); +} + +static void __sdhci_uhs2_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + int i, j; + int cmd_reg; + + i = 0; + sdhci_writel(host, + ((u32)cmd->uhs2_cmd->arg << 16) | + (u32)cmd->uhs2_cmd->header, + SDHCI_UHS2_CMD_PACKET + i); + i += 4; + + /* + * Per spec, payload (config) should be MSB before sending out. + * But we don't need convert here because had set payload as + * MSB when preparing config read/write commands. + */ + for (j = 0; j < cmd->uhs2_cmd->payload_len / sizeof(u32); j++) { + sdhci_writel(host, *(cmd->uhs2_cmd->payload + j), SDHCI_UHS2_CMD_PACKET + i); + i += 4; + } + + for ( ; i < SDHCI_UHS2_CMD_PACK_MAX_LEN; i += 4) + sdhci_writel(host, 0, SDHCI_UHS2_CMD_PACKET + i); + + DBG("UHS2 CMD packet_len = %d.\n", cmd->uhs2_cmd->packet_len); + for (i = 0; i < cmd->uhs2_cmd->packet_len; i++) + DBG("UHS2 CMD_PACKET[%d] = 0x%x.\n", i, + sdhci_readb(host, SDHCI_UHS2_CMD_PACKET + i)); + + cmd_reg = FIELD_PREP(SDHCI_UHS2_CMD_PACK_LEN_MASK, cmd->uhs2_cmd->packet_len); + if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) + cmd_reg |= SDHCI_UHS2_CMD_DATA; + if (cmd->opcode == MMC_STOP_TRANSMISSION) + cmd_reg |= SDHCI_UHS2_CMD_CMD12; + + /* UHS2 Native ABORT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_TRANS_ABORT)) + cmd_reg |= SDHCI_UHS2_CMD_TRNS_ABORT; + + /* UHS2 Native DORMANT */ + if ((cmd->uhs2_cmd->header & UHS2_NATIVE_PACKET) && + (uhs2_dev_cmd(cmd) == UHS2_DEV_CMD_GO_DORMANT_STATE)) + cmd_reg |= SDHCI_UHS2_CMD_DORMANT; + + DBG("0x%x is set to UHS2 CMD register.\n", cmd_reg); + + sdhci_writew(host, cmd_reg, SDHCI_UHS2_CMD); +} + +static bool sdhci_uhs2_send_command(struct sdhci_host *host, struct mmc_command *cmd) +{ + int flags; + u32 mask; + unsigned long timeout; + + WARN_ON(host->cmd); + + /* Initially, a command has no error */ + cmd->error = 0; + + if (cmd->opcode == MMC_STOP_TRANSMISSION) + cmd->flags |= MMC_RSP_BUSY; + + mask = SDHCI_CMD_INHIBIT; + + if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) + return false; + + host->cmd = cmd; + host->data_timeout = 0; + if (sdhci_data_line_cmd(cmd)) { + WARN_ON(host->data_cmd); + host->data_cmd = cmd; + __sdhci_uhs2_set_timeout(host); + } + + if (cmd->data) + sdhci_uhs2_prepare_data(host, cmd); + + sdhci_uhs2_set_transfer_mode(host, cmd); + + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { + WARN_ONCE(1, "Unsupported response type!\n"); + /* + * This does not happen in practice because 136-bit response + * commands never have busy waiting, so rather than complicate + * the error path, just remove busy waiting and continue. + */ + cmd->flags &= ~MMC_RSP_BUSY; + } + + if (!(cmd->flags & MMC_RSP_PRESENT)) + flags = SDHCI_CMD_RESP_NONE; + else if (cmd->flags & MMC_RSP_136) + flags = SDHCI_CMD_RESP_LONG; + else if (cmd->flags & MMC_RSP_BUSY) + flags = SDHCI_CMD_RESP_SHORT_BUSY; + else + flags = SDHCI_CMD_RESP_SHORT; + + if (cmd->flags & MMC_RSP_CRC) + flags |= SDHCI_CMD_CRC; + if (cmd->flags & MMC_RSP_OPCODE) + flags |= SDHCI_CMD_INDEX; + + timeout = jiffies; + if (host->data_timeout) + timeout += nsecs_to_jiffies(host->data_timeout); + else if (!cmd->data && cmd->busy_timeout > 9000) + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; + else + timeout += 10 * HZ; + sdhci_mod_timer(host, cmd->mrq, timeout); + + __sdhci_uhs2_send_command(host, cmd); + + return true; +} + +static bool sdhci_uhs2_send_command_retry(struct sdhci_host *host, + struct mmc_command *cmd, + unsigned long flags) + __releases(host->lock) + __acquires(host->lock) +{ + struct mmc_command *deferred_cmd = host->deferred_cmd; + int timeout = 10; /* Approx. 10 ms */ + bool present; + + while (!sdhci_uhs2_send_command(host, cmd)) { + if (!timeout--) { + pr_err("%s: Controller never released inhibit bit(s).\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + cmd->error = -EIO; + return false; + } + + spin_unlock_irqrestore(&host->lock, flags); + + usleep_range(1000, 1250); + + present = host->mmc->ops->get_cd(host->mmc); + + spin_lock_irqsave(&host->lock, flags); + + /* A deferred command might disappear, handle that */ + if (cmd == deferred_cmd && cmd != host->deferred_cmd) + return true; + + if (sdhci_present_error(host, cmd, present)) + return false; + } + + if (cmd == host->deferred_cmd) + host->deferred_cmd = NULL; + + return true; +} + +static void __sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd = host->cmd; + u8 resp; + u8 ecode; + bool breada0 = 0; + int i; + + if (host->mmc->flags & MMC_UHS2_SD_TRAN) { + resp = sdhci_readb(host, SDHCI_UHS2_RESPONSE + 2); + if (resp & UHS2_RES_NACK_MASK) { + ecode = (resp >> UHS2_RES_ECODE_POS) & UHS2_RES_ECODE_MASK; + pr_err("%s: NACK response, ECODE=0x%x.\n", mmc_hostname(host->mmc), ecode); + } + breada0 = 1; + } + + if (cmd->uhs2_resp && + cmd->uhs2_resp_len && cmd->uhs2_resp_len <= 20) { + /* Get whole response of some native CCMD, like + * DEVICE_INIT, ENUMERATE. + */ + for (i = 0; i < cmd->uhs2_resp_len; i++) + cmd->uhs2_resp[i] = sdhci_readb(host, SDHCI_UHS2_RESPONSE + i); + } else { + /* Get SD CMD response and Payload for some read + * CCMD, like INQUIRY_CFG. + */ + /* Per spec (p136), payload field is divided into + * a unit of DWORD and transmission order within + * a DWORD is big endian. + */ + if (!breada0) + sdhci_readl(host, SDHCI_UHS2_RESPONSE); + for (i = 4; i < 20; i += 4) { + cmd->resp[i / 4 - 1] = + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i) << 24) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 1) + << 16) | + (sdhci_readb(host, + SDHCI_UHS2_RESPONSE + i + 2) + << 8) | + sdhci_readb(host, SDHCI_UHS2_RESPONSE + i + 3); + } + } +} + +static void sdhci_uhs2_finish_command(struct sdhci_host *host) +{ + struct mmc_command *cmd = host->cmd; + + __sdhci_uhs2_finish_command(host); + + host->cmd = NULL; + + if (cmd->mrq->cap_cmd_during_tfr && cmd == cmd->mrq->cmd) + mmc_command_done(host->mmc, cmd->mrq); + + /* + * The host can send and interrupt when the busy state has + * ended, allowing us to wait without wasting CPU cycles. + * The busy signal uses DAT0 so this is similar to waiting + * for data to complete. + * + * Note: The 1.0 specification is a bit ambiguous about this + * feature so there might be some problems with older + * controllers. + */ + if (cmd->flags & MMC_RSP_BUSY) { + if (cmd->data) { + DBG("Cannot wait for busy signal when also doing a data transfer"); + } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && + cmd == host->data_cmd) { + /* Command complete before busy is ended */ + return; + } + } + + /* Processed actual command. */ + if (host->data && host->data_early) + sdhci_uhs2_finish_data(host); + + if (!cmd->data) + __sdhci_finish_mrq(host, cmd->mrq); +} + +void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct mmc_command *cmd; + unsigned long flags; + bool present; + + if (!(sdhci_uhs2_mode(host))) { + sdhci_request(mmc, mrq); + return; + } + + mrq->stop = NULL; + mrq->sbc = NULL; + if (mrq->data) + mrq->data->stop = NULL; + + /* Firstly check card presence */ + present = mmc->ops->get_cd(mmc); + + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_present_error(host, mrq->cmd, present)) + goto out_finish; + + cmd = mrq->cmd; + + if (!sdhci_uhs2_send_command_retry(host, cmd, flags)) + goto out_finish; + + spin_unlock_irqrestore(&host->lock, flags); + + return; + +out_finish: + sdhci_finish_mrq(host, mrq); + spin_unlock_irqrestore(&host->lock, flags); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_request); + +int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct mmc_command *cmd; + unsigned long flags; + int ret = 0; + + if (!sdhci_uhs2_mode(host)) + return sdhci_request_atomic(mmc, mrq); + + spin_lock_irqsave(&host->lock, flags); + + if (sdhci_present_error(host, mrq->cmd, true)) { + sdhci_finish_mrq(host, mrq); + goto out_finish; + } + + cmd = mrq->cmd; + + /* + * The HSQ may send a command in interrupt context without polling + * the busy signaling, which means we should return BUSY if controller + * has not released inhibit bits to allow HSQ trying to send request + * again in non-atomic context. So we should not finish this request + * here. + */ + if (!sdhci_uhs2_send_command(host, cmd)) + ret = -EBUSY; + +out_finish: + spin_unlock_irqrestore(&host->lock, flags); + return ret; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_request_atomic); + /*****************************************************************************\ * * * Driver init/exit * @@ -569,6 +980,7 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) host->mmc_host_ops.start_signal_voltage_switch = sdhci_uhs2_start_signal_voltage_switch; host->mmc_host_ops.uhs2_control = sdhci_uhs2_control; + host->mmc_host_ops.request = sdhci_uhs2_request; return 0; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 57209accbb03..9d031e83b6ba 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -147,10 +147,11 @@ void sdhci_enable_v4_mode(struct sdhci_host *host) } EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); -static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) +bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; } +EXPORT_SYMBOL_GPL(sdhci_data_line_cmd); static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) { @@ -502,14 +503,15 @@ static inline void sdhci_led_deactivate(struct sdhci_host *host) #endif -static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, - unsigned long timeout) +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, + unsigned long timeout) { if (sdhci_data_line_cmd(mrq->cmd)) mod_timer(&host->data_timer, timeout); else mod_timer(&host->timer, timeout); } +EXPORT_SYMBOL_GPL(sdhci_mod_timer); static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) { @@ -1076,8 +1078,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) __sdhci_set_timeout(host, cmd); } -static void sdhci_initialize_data(struct sdhci_host *host, - struct mmc_data *data) +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data) { WARN_ON(host->data); @@ -1090,6 +1091,7 @@ static void sdhci_initialize_data(struct sdhci_host *host, host->data_early = 0; host->data->bytes_xfered = 0; } +EXPORT_SYMBOL_GPL(sdhci_initialize_data); static inline void sdhci_set_block_info(struct sdhci_host *host, struct mmc_data *data) @@ -1112,12 +1114,8 @@ static inline void sdhci_set_block_info(struct sdhci_host *host, } } -static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data) { - struct mmc_data *data = cmd->data; - - sdhci_initialize_data(host, data); - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { struct scatterlist *sg; unsigned int length_mask, offset_mask; @@ -1202,6 +1200,16 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } sdhci_set_transfer_irqs(host); +} +EXPORT_SYMBOL_GPL(sdhci_prepare_dma); + +static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) +{ + struct mmc_data *data = cmd->data; + + sdhci_initialize_data(host, data); + + sdhci_prepare_dma(host, data); sdhci_set_block_info(host, data); } @@ -1519,7 +1527,7 @@ static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) WARN_ON(i >= SDHCI_MAX_MRQS); } -static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { if (host->cmd && host->cmd->mrq == mrq) host->cmd = NULL; @@ -1543,15 +1551,17 @@ static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) if (!sdhci_has_requests(host)) sdhci_led_deactivate(host); } +EXPORT_SYMBOL_GPL(__sdhci_finish_mrq); -static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) { __sdhci_finish_mrq(host, mrq); queue_work(host->complete_wq, &host->complete_work); } +EXPORT_SYMBOL_GPL(sdhci_finish_mrq); -static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) +void __sdhci_finish_data_common(struct sdhci_host *host) { struct mmc_command *data_cmd = host->data_cmd; struct mmc_data *data = host->data; @@ -1585,6 +1595,14 @@ static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) data->bytes_xfered = 0; else data->bytes_xfered = data->blksz * data->blocks; +} +EXPORT_SYMBOL_GPL(__sdhci_finish_data_common); + +static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout) +{ + struct mmc_data *data = host->data; + + __sdhci_finish_data_common(host); /* * Need to send CMD12 if - @@ -1719,8 +1737,8 @@ static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) return true; } -static bool sdhci_present_error(struct sdhci_host *host, - struct mmc_command *cmd, bool present) +bool sdhci_present_error(struct sdhci_host *host, + struct mmc_command *cmd, bool present) { if (!present || host->flags & SDHCI_DEVICE_DEAD) { cmd->error = -ENOMEDIUM; @@ -1729,6 +1747,7 @@ static bool sdhci_present_error(struct sdhci_host *host, return false; } +EXPORT_SYMBOL_GPL(sdhci_present_error); static bool sdhci_send_command_retry(struct sdhci_host *host, struct mmc_command *cmd, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 03d29423a678..9a2bd319d94c 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -828,6 +828,14 @@ static inline void sdhci_read_caps(struct sdhci_host *host) __sdhci_read_caps(host, NULL, NULL, NULL); } +bool sdhci_data_line_cmd(struct mmc_command *cmd); +void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout); +void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); +void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); +void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); +void __sdhci_finish_data_common(struct sdhci_host *host); +bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present); u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, unsigned int *actual_clock); void sdhci_set_clock(struct sdhci_host *host, unsigned int clock); From patchwork Fri Sep 8 09:53:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28DEBEE57E0 for ; Fri, 8 Sep 2023 09:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236690AbjIHJ40 (ORCPT ); Fri, 8 Sep 2023 05:56:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46506 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242808AbjIHJzy (ORCPT ); Fri, 8 Sep 2023 05:55:54 -0400 Received: from mail-pl1-x62a.google.com (mail-pl1-x62a.google.com [IPv6:2607:f8b0:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8257E1FE8; Fri, 8 Sep 2023 02:55:00 -0700 (PDT) Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-1c3887039d4so1827755ad.1; Fri, 08 Sep 2023 02:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166872; x=1694771672; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z/ZOte/qbNtr/TBqtV2Vm9YkNQqkjKIc4fwQMBZfcVY=; b=ar+OM1WZ3r60z5NbJIPDwNIdzC6qEjkeF1TQm6AzilBJ6ZfBiUVCkd/nFM1QTUYh7t mq/dAsMQlUAUGRWeTYi7fPzSamnSh81rT+3t8PfkOqeT8XvB5f/9u2Is3MxMc8RAdOtT 4Lmc+tSB/GIF31M2QZychkre8BLfhzb2dI+pRJ1+lddRYhcFDqPNA7dQt20emyOTdmQ2 07ve6uMU8n+WkmHujVDAZOqbFKhfAC+f6T1EotNiRUPt+z3JG0pVmOZnB5vvIZ+YdiBN CgZ3NDD8Ia3mRIFoFg/6zDO9+KtvekFPSFjuXlUJVsEZmy3MyKLBE+i+Ymu8hRyNDUb4 2/9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166872; x=1694771672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z/ZOte/qbNtr/TBqtV2Vm9YkNQqkjKIc4fwQMBZfcVY=; b=Dthv+lsIv5oL0jPMHPWkkqak2ESb7pEYak0LYU3fwBRsbGmC7jRAvwMJZtjXq63DG/ P6spw+wIUjczqMDdeErQapzD8GRDNOdkrdqNLcwfB00+JSi+/VSMtYtVLk2LbnxnkDLQ kOiGuSUvVs3g0GoMxS3T4k2NNR9k/L9B1mCHBHnJHMykX4tby2wGLvWFkLg8Sj9F/udE m1EOb86kmywK3gse7lw7J6M5zajLwkt6/Gr5tu5PSyLUuNyceOJLsKOjcQAaNvKJjUX4 t4e9aoIMYFuVExa5GbkcaKg9nOu30zequ5zNZqpvONxc2OL0v/T0CydDpR8pe5ZCqLbz xPHQ== X-Gm-Message-State: AOJu0Yz2dAUGDyk/Fx88gMsO9ha8EnV6Gci0PiBY9XdoARc2dzKD5hxC SmKtjFJDBqXJk22aFwgI8YE= X-Google-Smtp-Source: AGHT+IEc5ZZ3nBetWy72R7sycBQ5uy5wyzyrtuR8X5iqOvBnzSvP4wvjqqTjLadwAdiFBiY9JMZIqA== X-Received: by 2002:a17:902:7483:b0:1bb:891b:8bd with SMTP id h3-20020a170902748300b001bb891b08bdmr2218709pll.34.1694166872530; Fri, 08 Sep 2023 02:54:32 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:32 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 19/23] mmc: sdhci-uhs2: add irq() and others Date: Fri, 8 Sep 2023 17:53:26 +0800 Message-Id: <20230908095330.12075-20-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a UHS-II version of sdhci's request() operation. It handles UHS-II related command interrupts and errors. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Cancel export state of sdhci_set_mrq_done() function. Updates in V8: - Forward declare struct mmc_request in sdhci_uhs2.h. - Remove forward declaration of sdhci_send_command(). - Use mmc_dev() to simplify code in sdhci_request_done_dma(). Updates in V7: - Remove unnecessary functions. - Use sdhci_uhs2_mode() to simplify code in sdhci_uhs2_irq(). - Modify descriptions in sdhci_uhs2_irq(). - Cancel export state of some functions. Updates in V6: - Remove unnecessary functions. - Add sdhci_uhs2_mode() in sdhci_uhs2_complete_work(). - Add sdhci_uhs2_mode() in sdhci_uhs2_thread_irq(). --- drivers/mmc/host/sdhci-uhs2.c | 215 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 4 + drivers/mmc/host/sdhci.c | 99 +++++++++------- drivers/mmc/host/sdhci.h | 4 + 4 files changed, 277 insertions(+), 45 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 1f8d527424fd..7e4265c404ac 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -782,6 +782,221 @@ static void sdhci_uhs2_finish_command(struct sdhci_host *host) __sdhci_finish_mrq(host, cmd->mrq); } +/*****************************************************************************\ + * * + * Request done * + * * +\*****************************************************************************/ + +static bool sdhci_uhs2_request_done(struct sdhci_host *host) +{ + unsigned long flags; + struct mmc_request *mrq; + int i; + + spin_lock_irqsave(&host->lock, flags); + + for (i = 0; i < SDHCI_MAX_MRQS; i++) { + mrq = host->mrqs_done[i]; + if (mrq) + break; + } + + if (!mrq) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + /* + * Always unmap the data buffers if they were mapped by + * sdhci_prepare_data() whenever we finish with a request. + * This avoids leaking DMA mappings on error. + */ + if (host->flags & SDHCI_REQ_USE_DMA) + sdhci_request_done_dma(host, mrq); + + /* + * The controller needs a reset of internal state machines + * upon error conditions. + */ + if (sdhci_needs_reset(host, mrq)) { + /* + * Do not finish until command and data lines are available for + * reset. Note there can only be one other mrq, so it cannot + * also be in mrqs_done, otherwise host->cmd and host->data_cmd + * would both be null. + */ + if (host->cmd || host->data_cmd) { + spin_unlock_irqrestore(&host->lock, flags); + return true; + } + + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + host->pending_reset = false; + } + + host->mrqs_done[i] = NULL; + + spin_unlock_irqrestore(&host->lock, flags); + + if (host->ops->request_done) + host->ops->request_done(host, mrq); + else + mmc_request_done(host->mmc, mrq); + + return false; +} + +static void sdhci_uhs2_complete_work(struct work_struct *work) +{ + struct sdhci_host *host = container_of(work, struct sdhci_host, + complete_work); + + if (!sdhci_uhs2_mode(host)) { + sdhci_complete_work(work); + return; + } + + while (!sdhci_uhs2_request_done(host)) + ; +} + +/*****************************************************************************\ + * * + * Interrupt handling * + * * +\*****************************************************************************/ + +static void __sdhci_uhs2_irq(struct sdhci_host *host, u32 uhs2mask) +{ + struct mmc_command *cmd = host->cmd; + + DBG("*** %s got UHS2 error interrupt: 0x%08x\n", + mmc_hostname(host->mmc), uhs2mask); + + if (uhs2mask & SDHCI_UHS2_INT_CMD_ERR_MASK) { + if (!host->cmd) { + pr_err("%s: Got cmd interrupt 0x%08x but no cmd.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + host->cmd->error = -EILSEQ; + if (uhs2mask & SDHCI_UHS2_INT_CMD_TIMEOUT) + host->cmd->error = -ETIMEDOUT; + } + + if (uhs2mask & SDHCI_UHS2_INT_DATA_ERR_MASK) { + if (!host->data) { + pr_err("%s: Got data interrupt 0x%08x but no data.\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + sdhci_dumpregs(host); + return; + } + + if (uhs2mask & SDHCI_UHS2_INT_DEADLOCK_TIMEOUT) { + pr_err("%s: Got deadlock timeout interrupt 0x%08x\n", + mmc_hostname(host->mmc), + (unsigned int)uhs2mask); + host->data->error = -ETIMEDOUT; + } else if (uhs2mask & SDHCI_UHS2_INT_ADMA_ERROR) { + pr_err("%s: ADMA error = 0x %x\n", + mmc_hostname(host->mmc), + sdhci_readb(host, SDHCI_ADMA_ERROR)); + host->data->error = -EIO; + } else { + host->data->error = -EILSEQ; + } + } + + if (host->data && host->data->error) + sdhci_uhs2_finish_data(host); + else + sdhci_finish_mrq(host, cmd->mrq); +} + +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask) +{ + u32 mask = intmask, uhs2mask; + + if (!sdhci_uhs2_mode(host)) + goto out; + + if (intmask & SDHCI_INT_ERROR) { + uhs2mask = sdhci_readl(host, SDHCI_UHS2_INT_STATUS); + if (!(uhs2mask & SDHCI_UHS2_INT_ERROR_MASK)) + goto cmd_irq; + + /* Clear error interrupts */ + sdhci_writel(host, uhs2mask & SDHCI_UHS2_INT_ERROR_MASK, + SDHCI_UHS2_INT_STATUS); + + /* Handle error interrupts */ + __sdhci_uhs2_irq(host, uhs2mask); + + /* Caller, sdhci_irq(), doesn't have to care about UHS-2 errors */ + intmask &= ~SDHCI_INT_ERROR; + mask &= SDHCI_INT_ERROR; + } + +cmd_irq: + if (intmask & SDHCI_INT_CMD_MASK) { + /* Clear command interrupt */ + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, SDHCI_INT_STATUS); + + /* Handle command interrupt */ + if (intmask & SDHCI_INT_RESPONSE) + sdhci_uhs2_finish_command(host); + + /* Caller, sdhci_irq(), doesn't have to care about UHS-2 commands */ + intmask &= ~SDHCI_INT_CMD_MASK; + mask &= SDHCI_INT_CMD_MASK; + } + + /* Clear already-handled interrupts. */ + sdhci_writel(host, mask, SDHCI_INT_STATUS); + +out: + return intmask; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_irq); + +static irqreturn_t sdhci_uhs2_thread_irq(int irq, void *dev_id) +{ + struct sdhci_host *host = dev_id; + struct mmc_command *cmd; + unsigned long flags; + u32 isr; + + if (!sdhci_uhs2_mode(host)) + return sdhci_thread_irq(irq, dev_id); + + while (!sdhci_uhs2_request_done(host)) + ; + + spin_lock_irqsave(&host->lock, flags); + + isr = host->thread_isr; + host->thread_isr = 0; + + cmd = host->deferred_cmd; + if (cmd && !sdhci_uhs2_send_command_retry(host, cmd, flags)) + sdhci_finish_mrq(host, cmd->mrq); + + spin_unlock_irqrestore(&host->lock, flags); + + if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { + struct mmc_host *mmc = host->mmc; + + mmc->ops->card_event(mmc); + mmc_detect_change(mmc, msecs_to_jiffies(200)); + } + + return IRQ_HANDLED; +} + void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct sdhci_host *host = mmc_priv(mmc); diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index a3641c5f8c77..3aa2cb4b39d6 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -176,11 +176,15 @@ struct sdhci_host; struct mmc_command; +struct mmc_request; void sdhci_uhs2_dump_regs(struct sdhci_host *host); bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); +void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq); +int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); +u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9d031e83b6ba..318d4830732f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1497,7 +1497,7 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); } -static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) { return (!(host->flags & SDHCI_DEVICE_DEAD) && ((mrq->cmd && mrq->cmd->error) || @@ -1505,6 +1505,7 @@ static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) (mrq->data && mrq->data->stop && mrq->data->stop->error) || (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); } +EXPORT_SYMBOL_GPL(sdhci_needs_reset); static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq) { @@ -3110,6 +3111,53 @@ static const struct mmc_host_ops sdhci_ops = { * * \*****************************************************************************/ +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq) +{ + struct mmc_data *data = mrq->data; + + if (data && data->host_cookie == COOKIE_MAPPED) { + if (host->bounce_buffer) { + /* + * On reads, copy the bounced data into the + * sglist + */ + if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { + unsigned int length = data->bytes_xfered; + + if (length > host->bounce_buffer_size) { + pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", + mmc_hostname(host->mmc), + host->bounce_buffer_size, + data->bytes_xfered); + /* Cap it down and continue */ + length = host->bounce_buffer_size; + } + dma_sync_single_for_cpu(mmc_dev(host->mmc), + host->bounce_addr, + host->bounce_buffer_size, + DMA_FROM_DEVICE); + sg_copy_from_buffer(data->sg, + data->sg_len, + host->bounce_buffer, + length); + } else { + /* No copying, just switch ownership */ + dma_sync_single_for_cpu(mmc_dev(host->mmc), + host->bounce_addr, + host->bounce_buffer_size, + mmc_get_dma_dir(data)); + } + } else { + /* Unmap the raw data */ + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, + mmc_get_dma_dir(data)); + } + data->host_cookie = COOKIE_UNMAPPED; + } +} +EXPORT_SYMBOL_GPL(sdhci_request_done_dma); + static bool sdhci_request_done(struct sdhci_host *host) { unsigned long flags; @@ -3174,48 +3222,7 @@ static bool sdhci_request_done(struct sdhci_host *host) sdhci_set_mrq_done(host, mrq); } - if (data && data->host_cookie == COOKIE_MAPPED) { - if (host->bounce_buffer) { - /* - * On reads, copy the bounced data into the - * sglist - */ - if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE) { - unsigned int length = data->bytes_xfered; - - if (length > host->bounce_buffer_size) { - pr_err("%s: bounce buffer is %u bytes but DMA claims to have transferred %u bytes\n", - mmc_hostname(host->mmc), - host->bounce_buffer_size, - data->bytes_xfered); - /* Cap it down and continue */ - length = host->bounce_buffer_size; - } - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - DMA_FROM_DEVICE); - sg_copy_from_buffer(data->sg, - data->sg_len, - host->bounce_buffer, - length); - } else { - /* No copying, just switch ownership */ - dma_sync_single_for_cpu( - mmc_dev(host->mmc), - host->bounce_addr, - host->bounce_buffer_size, - mmc_get_dma_dir(data)); - } - } else { - /* Unmap the raw data */ - dma_unmap_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, - mmc_get_dma_dir(data)); - } - data->host_cookie = COOKIE_UNMAPPED; - } + sdhci_request_done_dma(host, mrq); } host->mrqs_done[i] = NULL; @@ -3230,7 +3237,7 @@ static bool sdhci_request_done(struct sdhci_host *host) return false; } -static void sdhci_complete_work(struct work_struct *work) +void sdhci_complete_work(struct work_struct *work) { struct sdhci_host *host = container_of(work, struct sdhci_host, complete_work); @@ -3238,6 +3245,7 @@ static void sdhci_complete_work(struct work_struct *work) while (!sdhci_request_done(host)) ; } +EXPORT_SYMBOL_GPL(sdhci_complete_work); static void sdhci_timeout_timer(struct timer_list *t) { @@ -3693,7 +3701,7 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) return result; } -static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) +irqreturn_t sdhci_thread_irq(int irq, void *dev_id) { struct sdhci_host *host = dev_id; struct mmc_command *cmd; @@ -3723,6 +3731,7 @@ static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) return IRQ_HANDLED; } +EXPORT_SYMBOL_GPL(sdhci_thread_irq); /*****************************************************************************\ * * diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 9a2bd319d94c..6bbb9f073f29 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -832,6 +832,7 @@ bool sdhci_data_line_cmd(struct mmc_command *cmd); void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, unsigned long timeout); void sdhci_initialize_data(struct sdhci_host *host, struct mmc_data *data); void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data); +bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq); void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq); void __sdhci_finish_data_common(struct sdhci_host *host); @@ -861,6 +862,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable); +void sdhci_request_done_dma(struct sdhci_host *host, struct mmc_request *mrq); +void sdhci_complete_work(struct work_struct *work); +irqreturn_t sdhci_thread_irq(int irq, void *dev_id); void sdhci_adma_write_desc(struct sdhci_host *host, void **desc, dma_addr_t addr, int len, unsigned int cmd); From patchwork Fri Sep 8 09:53:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE057EE57F2 for ; Fri, 8 Sep 2023 09:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229602AbjIHJ4Z (ORCPT ); Fri, 8 Sep 2023 05:56:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242824AbjIHJzy (ORCPT ); Fri, 8 Sep 2023 05:55:54 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14DDC1FE9; Fri, 8 Sep 2023 02:55:04 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-68a3e943762so1733321b3a.1; Fri, 08 Sep 2023 02:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166875; x=1694771675; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LqJbyoX2A5YRP0/3PONf/FC/kmwXHvITX8kMGpZeK+Y=; b=IDcOu9y2QKXo4gVxHmQOtC9Xc86ZfoOy2nNc1sYmb9DgsJVbW9hSAJYiv4qlSibBgi hYhZOqDlYw+L80zFVvNh7sqZbJuVqYMO8w9KWCNdATPTf5RHLEVJF/7AhN5Vup1RSL0U YuuKszdIPcg0kHArnxe67hLxnjkZzhL0tcG00H3MHAzi+DHwkZSsE6pSzoeftZV7bGrK 3fP+1cvXnF0wVazQ+B2CfEJTL8OPUPdcoxlvFX3eNXDGksrMaTAIh47BKVAlLEmaOajr t4VhZDfG+0GUzACEjDpJQ3jiRo6PacsyywmtZIEP3BmlK8Rlig5riNhxwR+E8VJ+5Lsk 5lqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166875; x=1694771675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LqJbyoX2A5YRP0/3PONf/FC/kmwXHvITX8kMGpZeK+Y=; b=KdQwbq2SkohMIpA+MTHRd16j39VASJFR8tsCci6ZR7wnEuSXPxNfKh+PAgbTRq1tjI HnBt9oTywbjzJSM+a2UisepfKjiIkY/M7KCyDa2Ucbi/8OcGvvbgEkvjWIq3p7Gr+Qmf dQI/m1DRzEXP0iDt35VxeeRcLtckEm03dlSGTGNT6PWydy3AFVr3uOU1C37Z5yH+v7fi z8ExM4bgQD6+jQuA+N0qOqZj0npobiWviNLTLYNAXGZwWA7DbMjBqu5wqDs3hEqD37sw fGznhLvSz4FCqBWIYAW1/geztEx+oxAIpQ6HEtKi7MMUKCMbTc6BG9SMpfCNwWxFo6Kx edKA== X-Gm-Message-State: AOJu0YwbHFfBjJCuQBCueHkjb7i02xY6Y0Orji1hcmPZhZ/UsMuuZKp8 dm2224Kj2Ix6ZbhkMChsHj0= X-Google-Smtp-Source: AGHT+IE6vAU6Gd51BBL5k6733bxyTnTrSKttYHiYrZyBW9VB8g90Z3GfBtObJPYkgiHsfx7DFNmiBA== X-Received: by 2002:a05:6a20:734d:b0:149:7a49:f7be with SMTP id v13-20020a056a20734d00b001497a49f7bemr2471372pzc.4.1694166875259; Fri, 08 Sep 2023 02:54:35 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:35 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 20/23] mmc: sdhci-uhs2: add add_host() and others to set up the driver Date: Fri, 8 Sep 2023 17:53:27 +0800 Message-Id: <20230908095330.12075-21-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This is a UHS-II version of sdhci's add_host/remove_host operation. Any sdhci drivers which are capable of handling UHS-II cards must call those functions instead of the corresponding sdhci's. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V11: - Remove unused ocr_avail_uhs2. Updates in V10: - Move some definitions of PatchV9[05/23] to PatchV10[20/23]. Updates in V8: - Change return type to void for __sdhci_uhs2_add_host_v4(). - Remove unused variables in __sdhci_uhs2_add_host_v4(). Updates in V7: - __sdhci_add_host() to instead of __sdhci_uhs2_add_host() in sdhci_uhs2_add_host(). - Cancel export state of some functions. Updates in V6: - Add complete_work_fn/thread_irq_fn variables in struct sdhci_host. - Use complete_work_fn/thread_irq_fn variables in sdhci_alloc_host() and sdhci_uhs2_add_host(). - Use sdhci_uhs2_mode() to simplify code in __sdhci_uhs2_remove_host(). --- drivers/mmc/host/sdhci-uhs2.c | 100 ++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 2 + drivers/mmc/host/sdhci.c | 7 ++- drivers/mmc/host/sdhci.h | 3 + 4 files changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 7e4265c404ac..add0eea55b24 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-uhs2.h" @@ -997,6 +998,105 @@ static irqreturn_t sdhci_uhs2_thread_irq(int irq, void *dev_id) return IRQ_HANDLED; } +/*****************************************************************************\ + * + * Device allocation/registration * + * * +\*****************************************************************************/ + +static void __sdhci_uhs2_add_host_v4(struct sdhci_host *host, u32 caps1) +{ + struct mmc_host *mmc; + u32 max_current_caps2; + + mmc = host->mmc; + + /* Support UHS2 */ + if (caps1 & SDHCI_SUPPORT_UHS2) + mmc->caps2 |= MMC_CAP2_SD_UHS2; + + max_current_caps2 = sdhci_readl(host, SDHCI_MAX_CURRENT_1); + + if ((caps1 & SDHCI_CAN_VDD2_180) && + !max_current_caps2 && + !IS_ERR(mmc->supply.vmmc2)) { + /* UHS2 - VDD2 */ + int curr = regulator_get_current_limit(mmc->supply.vmmc2); + + if (curr > 0) { + /* convert to SDHCI_MAX_CURRENT format */ + curr = curr / 1000; /* convert to mA */ + curr = curr / SDHCI_MAX_CURRENT_MULTIPLIER; + curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); + max_current_caps2 = curr; + } + } + + if (!(caps1 & SDHCI_CAN_VDD2_180)) + mmc->caps2 &= ~MMC_CAP2_SD_UHS2; +} + +static int sdhci_uhs2_host_ops_init(struct sdhci_host *host); + +static void __sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + if (!sdhci_uhs2_mode(host)) + return; + + if (!dead) + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_FULL); +} + +int sdhci_uhs2_add_host(struct sdhci_host *host) +{ + struct mmc_host *mmc = host->mmc; + int ret; + + ret = sdhci_setup_host(host); + if (ret) + return ret; + + if (host->version >= SDHCI_SPEC_400) + __sdhci_uhs2_add_host_v4(host, host->caps1); + + if ((mmc->caps2 & MMC_CAP2_SD_UHS2) && !host->v4_mode) + /* host doesn't want to enable UHS2 support */ + mmc->caps2 &= ~MMC_CAP2_SD_UHS2; + + /* overwrite ops */ + if (mmc->caps2 & MMC_CAP2_SD_UHS2) + sdhci_uhs2_host_ops_init(host); + + host->complete_work_fn = sdhci_uhs2_complete_work; + host->thread_irq_fn = sdhci_uhs2_thread_irq; + + /* LED support not implemented for UHS2 */ + host->quirks |= SDHCI_QUIRK_NO_LED; + + ret = __sdhci_add_host(host); + if (ret) + goto cleanup; + + return 0; + +cleanup: + if (host->version >= SDHCI_SPEC_400) + __sdhci_uhs2_remove_host(host, 0); + + sdhci_cleanup_host(host); + + return ret; +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_add_host); + +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead) +{ + __sdhci_uhs2_remove_host(host, dead); + + sdhci_remove_host(host, dead); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_remove_host); + void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct sdhci_host *host = mmc_priv(mmc); diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 3aa2cb4b39d6..bd5aae054c6f 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -186,5 +186,7 @@ void sdhci_uhs2_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set); void sdhci_uhs2_request(struct mmc_host *mmc, struct mmc_request *mrq); int sdhci_uhs2_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq); u32 sdhci_uhs2_irq(struct sdhci_host *host, u32 intmask); +int sdhci_uhs2_add_host(struct sdhci_host *host); +void sdhci_uhs2_remove_host(struct sdhci_host *host, int dead); #endif /* __SDHCI_UHS2_H */ diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 318d4830732f..b3de7e30ba54 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4104,6 +4104,9 @@ struct sdhci_host *sdhci_alloc_host(struct device *dev, host->max_timeout_count = 0xE; + host->complete_work_fn = sdhci_complete_work; + host->thread_irq_fn = sdhci_thread_irq; + return host; } @@ -4853,7 +4856,7 @@ int __sdhci_add_host(struct sdhci_host *host) if (!host->complete_wq) return -ENOMEM; - INIT_WORK(&host->complete_work, sdhci_complete_work); + INIT_WORK(&host->complete_work, host->complete_work_fn); timer_setup(&host->timer, sdhci_timeout_timer, 0); timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0); @@ -4862,7 +4865,7 @@ int __sdhci_add_host(struct sdhci_host *host) sdhci_init(host, 0); - ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, + ret = request_threaded_irq(host->irq, sdhci_irq, host->thread_irq_fn, IRQF_SHARED, mmc_hostname(mmc), host); if (ret) { pr_err("%s: Failed to request IRQ %d: %d\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 6bbb9f073f29..5235f2da6568 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -626,6 +626,9 @@ struct sdhci_host { struct timer_list timer; /* Timer for timeouts */ struct timer_list data_timer; /* Timer for data timeouts */ + void (*complete_work_fn)(struct work_struct *work); + irqreturn_t (*thread_irq_fn)(int irq, void *dev_id); + #if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA) struct dma_chan *rx_chan; struct dma_chan *tx_chan; From patchwork Fri Sep 8 09:53:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58BB0EE57EE for ; Fri, 8 Sep 2023 09:56:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241579AbjIHJ42 (ORCPT ); Fri, 8 Sep 2023 05:56:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242790AbjIHJzu (ORCPT ); Fri, 8 Sep 2023 05:55:50 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13CE61FC0; Fri, 8 Sep 2023 02:55:04 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1c1f7f7151fso14708385ad.1; Fri, 08 Sep 2023 02:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166878; x=1694771678; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I8s+ls8Yw6NMJtaPKq6UHyd+YkBQYdgGHT2EXOl3gig=; b=qoE5NaSsAVcMCg55dp8M93+qCAbk1lTLlqzFyCdVQCOQzQjIaKF0ANspZgNAudyucB ycCPzomoyxwTkvhpGFjZlG9ZDTb72Hlyfg3L0Cgb6ItPrRcRKCnpPZ64WT1XmHInZhJT /NY8gpt/+w0HzbxwAq3ekF7YzhJikJ0BO+/yG+FdENBQ9GSSgw9SqV6cO+y7nYYC6tuB 9znf0hvzgJS5Y06/IDozsDwBGM/mFJEX80ZBVqsujNT/9rTEn0X7CQAKHGNDMd4jstbp XHwY2U68FnFpivM7yIyGdXqmLet8KtwCLHZ+56WxxuhbJ6S75UaltJloN/u8lhTbNCb7 ylkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166878; x=1694771678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I8s+ls8Yw6NMJtaPKq6UHyd+YkBQYdgGHT2EXOl3gig=; b=P6A1ZozpCe+YDjjdgMTaGLq1KofK0rIe+3bvmV/+s7YKVBfHtGefhe167+72vmudwX U/dP+EvpBwfHcL1NGthztNhsr0jfjpsKnvpbxDt9L8rpygU4BJlYJ0I0xYUAazbfxEdl J0KWlq4BjhMOcGHhr4OpCVoHL4boTEZho+dIZAxVdgbu57nPZprBv5iXiGzWFJpOzsQb aR24TQwCcV8nuxU8C5YdOlD4iNPyz2yKbeOLtWwl5IsrT83EoTvb/nP61IcL55Aq8Dnm Pkyb94ilnKykL4oDqZWJChhxX5mUhri5jfjgPzVfk682L28mhKFRONAtCXtOEX+GhMhC XFKA== X-Gm-Message-State: AOJu0Yxy9LIndYksSfz1YgynJxlFrhswSSNaLvBx5CXOq2tw8T3n5OZp fdqqzI7Furv76gI1mKU5QZY= X-Google-Smtp-Source: AGHT+IGkEuaMtsMJEpkKEUMVZ4JFUo6BWDh7HgM+Rdg6xJ3sUgBglI0Cdx2KW2uHkPBgKkajdeMWDA== X-Received: by 2002:a17:902:ce92:b0:1bf:3378:6808 with SMTP id f18-20020a170902ce9200b001bf33786808mr2410620plg.56.1694166878099; Fri, 08 Sep 2023 02:54:38 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:37 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V11 21/23] mmc: sdhci-uhs2: add pre-detect_init hook Date: Fri, 8 Sep 2023 17:53:28 +0800 Message-Id: <20230908095330.12075-22-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Ben Chuang This "pre" hook for detect_init(), uhs2_pre_detect_init, will be required to enable UHS-II support, at least, on GL9755. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-uhs2.c | 3 +++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index add0eea55b24..517c497112f4 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -1267,6 +1267,9 @@ static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc) DBG("Begin do uhs2 detect init.\n"); + if (host->ops && host->ops->uhs2_pre_detect_init) + host->ops->uhs2_pre_detect_init(host); + if (sdhci_uhs2_interface_detect(host)) { pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc)); return -EIO; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 5235f2da6568..300108cc255d 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -724,6 +724,7 @@ struct sdhci_ops { struct mmc_request *mrq); void (*dump_vendor_regs)(struct sdhci_host *host); void (*dump_uhs2_regs)(struct sdhci_host *host); + void (*uhs2_pre_detect_init)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS From patchwork Fri Sep 8 09:53:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10A31EE57F1 for ; Fri, 8 Sep 2023 09:56:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240216AbjIHJ41 (ORCPT ); Fri, 8 Sep 2023 05:56:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242813AbjIHJzy (ORCPT ); Fri, 8 Sep 2023 05:55:54 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E3501FEE; Fri, 8 Sep 2023 02:55:05 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1bee82fad0fso16000025ad.2; Fri, 08 Sep 2023 02:55:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166881; x=1694771681; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kgbgwKrKjJpNlxXNT9qT4rfZ8mQ8laO3LorzcVf8E/s=; b=HcfmGrXe5sm5JD+EDFkl1/Vw0K+YUk3b1oSkHt9IFNkYYGNZIJu0ykAMuH6Y+ysMUj 8SAngU++xbTeWzpnavz5aYtVKOeM33HaVzW9RW2dfNLXoGn+HFOb9KOU5f/ac/ERPQgf bBvPmOvsLNlsFHeQDz95WXIkEE1WU976MwcjPKDpRbJnhEXJQC1WKBnVcLGLqKgrHDCm 5XSh47uM5dKbONUD8Dpv3nqM/zumHc31zdzRaMVqb9C+aIvBYZIMVndmbPhC9tSqUsv/ A3XOJz5/cGu9zKfLasAq3okXRExHq5Nc2e4nUR3q/FN9cquiyHPtA9mmC31dm69MQS+r pYEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166881; x=1694771681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kgbgwKrKjJpNlxXNT9qT4rfZ8mQ8laO3LorzcVf8E/s=; b=lvN5SyjDZILwzsj4B+1rZVt2WCPIHdoEMQFOKqSRbx+lAqlDmkXk/aRPcVtGEgl6zJ E6SqujSvwk1fCY6xXosDMX0n51J46eVT39ilu528fMjQKPNzfCgg1ZfSmt4CcfbzbJ58 s2tCMnDYK2i3BO3XaFf+BV0NoyvEA+UhCeViS+XqyIIAdbHIR6JTY0FKHJradxsklIUk JRdAN1VwI+JYi22kfHY07cCGU2dB5dijTf44ukbUSL23/9izVxoiwPdLJRvyTEgYvfbN NuIZjxNNteYSmWEZcJIbvTjyorHP2sUkj24peFBjQKvPEBrtjB6T3Cc2197aWQzdVFGX 4JkA== X-Gm-Message-State: AOJu0Yw9tgmCpSYiQeMV1Mj3iHizTg1Yvb3oYaruNIgokhaWruOzOxj7 rS0GhAakRWYawVyKwiGUNYos5eZpryM= X-Google-Smtp-Source: AGHT+IHHEM0yzRl9Ynnex0Ssv5x1an9diuFX4fUS6rq15VQjJOKlXVAEqhO8ic91B3fD82dyMeY6jg== X-Received: by 2002:a17:903:11c9:b0:1b9:e972:134d with SMTP id q9-20020a17090311c900b001b9e972134dmr1962721plh.3.1694166880842; Fri, 08 Sep 2023 02:54:40 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:40 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 22/23] mmc: sdhci-pci: add UHS-II support framework Date: Fri, 8 Sep 2023 17:53:29 +0800 Message-Id: <20230908095330.12075-23-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih This patch prepares for adding UHS-II support at a specific UHS-II capable sdhci-pci controller, GL9755 for now. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V8: - Add config select MMC_SDHCI_UHS2 in Kconfig. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-pci-core.c | 16 +++++++++++++++- drivers/mmc/host/sdhci-pci.h | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 215f1ab011dd..aa178384de16 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -111,6 +111,7 @@ config MMC_SDHCI_PCI tristate "SDHCI support on PCI bus" depends on MMC_SDHCI && PCI select MMC_CQHCI + select MMC_SDHCI_UHS2 select IOSF_MBI if X86 select MMC_SDHCI_IO_ACCESSORS help diff --git a/drivers/mmc/host/sdhci-pci-core.c b/drivers/mmc/host/sdhci-pci-core.c index 7c14feb5db77..22698119ecf2 100644 --- a/drivers/mmc/host/sdhci-pci-core.c +++ b/drivers/mmc/host/sdhci-pci-core.c @@ -40,6 +40,7 @@ #include "sdhci.h" #include "sdhci-cqhci.h" #include "sdhci-pci.h" +#include "sdhci-uhs2.h" static void sdhci_pci_hw_reset(struct sdhci_host *host); @@ -2160,7 +2161,10 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) if (scratch == (u32)-1) dead = 1; - sdhci_remove_host(slot->host, dead); + if (slot->chip->fixes && slot->chip->fixes->remove_host) + slot->chip->fixes->remove_host(slot, dead); + else + sdhci_remove_host(slot->host, dead); if (slot->chip->fixes && slot->chip->fixes->remove_slot) slot->chip->fixes->remove_slot(slot, dead); @@ -2168,6 +2172,16 @@ static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) sdhci_free_host(slot->host); } +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) +{ + return sdhci_uhs2_add_host(slot->host); +} + +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) +{ + sdhci_uhs2_remove_host(slot->host, dead); +} + static void sdhci_pci_runtime_pm_allow(struct device *dev) { pm_suspend_ignore_children(dev, 1); diff --git a/drivers/mmc/host/sdhci-pci.h b/drivers/mmc/host/sdhci-pci.h index 153704f812ed..e807c039a8b1 100644 --- a/drivers/mmc/host/sdhci-pci.h +++ b/drivers/mmc/host/sdhci-pci.h @@ -145,6 +145,7 @@ struct sdhci_pci_fixes { int (*probe_slot) (struct sdhci_pci_slot *); int (*add_host) (struct sdhci_pci_slot *); void (*remove_slot) (struct sdhci_pci_slot *, int); + void (*remove_host) (struct sdhci_pci_slot *, int); #ifdef CONFIG_PM_SLEEP int (*suspend) (struct sdhci_pci_chip *); @@ -189,6 +190,8 @@ static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot) return (void *)slot->private; } +int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot); +void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead); #ifdef CONFIG_PM_SLEEP int sdhci_pci_resume_host(struct sdhci_pci_chip *chip); #endif From patchwork Fri Sep 8 09:53:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 13377319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55B73EE57EF for ; Fri, 8 Sep 2023 09:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231450AbjIHJ4Z (ORCPT ); Fri, 8 Sep 2023 05:56:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242829AbjIHJzy (ORCPT ); Fri, 8 Sep 2023 05:55:54 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBCDE1FF0; Fri, 8 Sep 2023 02:55:06 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id 41be03b00d2f7-573ccec985dso1398728a12.2; Fri, 08 Sep 2023 02:55:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694166884; x=1694771684; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j3ImsKeVTdhxdpT+a4GoerWT4GQatv0MF5s5u1wyjzE=; b=YI4es/q/+XY0QMdTr8I4OR3XnOdrVSPqKk381ESeHVstCCQB9mj93CZw6PRs3qpySS 1yG433P7Df7JuvqSW7SKlVkW6IbJqfhfMjBrpEtfEbAmCbf00PDZrY0LBGY7nuSBwrpW jT8JkGXrkKMJErF9a4dNkpnyHfd0XyrnaWSI09V2/qpxH+6sn1pol6bk5BD4XHceT3DN g0XO7Ine59S4u74QOPadIkk92ZpTgXDW7kzXlTxe0aAMWDieSoEXV0VO34oN/i9XC+Dq XlWNA4M077Ejsf1hS3OtdMW0TFoDcY4qCdCPhydX/Ri7rNAFAad1gnNBujqqFbEqR0hO t8+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694166884; x=1694771684; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j3ImsKeVTdhxdpT+a4GoerWT4GQatv0MF5s5u1wyjzE=; b=mymHSNKUBAuNyv4IV7jXgRV1vyIZvglxi4g1Ea7WXgOkj5ldPZ6L2qUPWqDcbHKe9T 16HbZ/GJ3hRhhqg4UbqzEshmGHfiI+u0g0mQ2PFBnhvKSZX788l+Rb8/6dU4dKjls9vV FHk7tMh578V2SLAJqn94YXAQrLaB4ablpVbXNiu0GsPO9Xjy+GGsP9GceNzs3cSk5xRl TsgsXWuZrXa+/3H4I0L6PnpOEWmVy5tW4iglIaxxpOJ9V89UgaYnj9lV5FuVA+Kr1eQ5 +oE/DzwHYmkwdlviJuV4DQbIHyIo1azbAMC9Wsf2S7MLaTOA5SdHbFMYJE51BiS0Q+ei zOmQ== X-Gm-Message-State: AOJu0YxMQtup7Ag3NtI/kasH4M0z4haJmATquIvtWaD/b4geRV2cRb9a 0SUiUUxznxSe3wL1oSOebk8ecSEth3A= X-Google-Smtp-Source: AGHT+IE7PyS+gi9dJBmaRVmRk8VXgxfuv96Nf5fIauy+ohqqcL6Ouj3PojoYhFmLye3x1IHB1ntAyg== X-Received: by 2002:a05:6a20:3d03:b0:140:3aa:e2ce with SMTP id y3-20020a056a203d0300b0014003aae2cemr2506860pzi.42.1694166883695; Fri, 08 Sep 2023 02:54:43 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e3a1-00a4-a20b-46bc-ccec-3e79.emome-ip6.hinet.net. [2001:b400:e3a1:a4:a20b:46bc:ccec:3e79]) by smtp.gmail.com with ESMTPSA id c9-20020a170902d48900b001b892aac5c9sm1172178plg.298.2023.09.08.02.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 02:54:43 -0700 (PDT) From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang , Victor Shih Subject: [PATCH V11 23/23] mmc: sdhci-pci-gli: enable UHS-II mode for GL9755 Date: Fri, 8 Sep 2023 17:53:30 +0800 Message-Id: <20230908095330.12075-24-victorshihgli@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230908095330.12075-1-victorshihgli@gmail.com> References: <20230908095330.12075-1-victorshihgli@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Victor Shih Changes are: * Disable GL9755 overcurrent interrupt when power on/off on UHS-II. * Enable the internal clock when do reset on UHS-II mode. * Increase timeout value before detecting UHS-II interface. * Add vendor settings fro UHS-II mode. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro Signed-off-by: Victor Shih Acked-by: Adrian Hunter --- Updates in V9: - Rename gl9755_pre_detect_init() to sdhci_gli_pre_detect_init(). - Rename gl9755_uhs2_reset_sd_tran() to sdhci_gli_uhs2_reset_sd_tran(). Updates in V8: - Use sdhci_get_vdd_value() to simplify code in gl9755_set_power(). - Use read_poll_timeout_atomic() to simplify code in sdhci_wait_clock_stable(). - Use read_poll_timeout_atomic() to simplify code in sdhci_gl9755_reset(). Updates in V7: - Drop using gl9755_post_attach_sd(). --- drivers/mmc/host/sdhci-pci-gli.c | 233 ++++++++++++++++++++++++++++++- 1 file changed, 232 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index ae8c307b7aa7..e30e755a9974 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -18,6 +18,7 @@ #include "sdhci-cqhci.h" #include "sdhci-pci.h" #include "cqhci.h" +#include "sdhci-uhs2.h" /* Genesys Logic extra registers */ #define SDHCI_GLI_9750_WT 0x800 @@ -139,9 +140,36 @@ #define PCI_GLI_9755_PLLSSC 0x68 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) +#define PCI_GLI_9755_PLLSSC_RTL BIT(24) +#define GLI_9755_PLLSSC_RTL_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) +#define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 +#define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) +#define GLI_9755_PLLSSC_RECV_VALUE 0x3 +#define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) +#define GLI_9755_PLLSSC_TRAN_VALUE 0x3 + +#define PCI_GLI_9755_UHS2_PLL 0x6C +#define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) +#define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 +#define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) +#define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 +#define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) +#define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 #define PCI_GLI_9755_SerDes 0x70 +#define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) +#define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 +#define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) +#define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 +#define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) +#define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB +#define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 #define PCI_GLI_9755_SCP_DIS BIT(19) +#define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) +#define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC +#define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) +#define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF #define PCI_GLI_9755_MISC 0x78 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) @@ -759,6 +787,201 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) gl9755_wt_off(pdev); } +static void gl9755_vendor_init(struct sdhci_host *host) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct pci_dev *pdev = slot->chip->pdev; + u32 serdes; + u32 pllssc; + u32 uhs2_pll; + + gl9755_wt_on(pdev); + + pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, + GLI_9755_UHS2_SERDES_TRAN_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, + GLI_9755_UHS2_SERDES_RECV_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, + GLI_9755_UHS2_SERDES_INTR_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, + GLI_9755_UHS2_SERDES_ZC1_VALUE); + serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; + serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, + GLI_9755_UHS2_SERDES_ZC2_DEFAULT); + pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); + + pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, + GLI_9755_UHS2_PLL_SSC_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, + GLI_9755_UHS2_PLL_DELAY_VALUE); + uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; + uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, + GLI_9755_UHS2_PLL_PDRST_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); + + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); + pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, + GLI_9755_PLLSSC_RTL_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, + GLI_9755_PLLSSC_TRANS_PASS_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, + GLI_9755_PLLSSC_RECV_VALUE); + pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; + pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, + GLI_9755_PLLSSC_TRAN_VALUE); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); + + gl9755_wt_off(pdev); +} + +static void sdhci_gli_pre_detect_init(struct sdhci_host *host) +{ + /* Need more time on UHS2 detect flow */ + sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); +} + +static void gl9755_overcurrent_event_enable(struct sdhci_host *host, + bool enable) +{ + u32 mask; + + mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); + + mask = sdhci_readl(host, SDHCI_INT_ENABLE); + if (enable) + mask |= SDHCI_INT_BUS_POWER; + else + mask &= ~SDHCI_INT_BUS_POWER; + + sdhci_writel(host, mask, SDHCI_INT_ENABLE); +} + +static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + u8 pwr = 0; + + if (mode != MMC_POWER_OFF) { + pwr = sdhci_get_vdd_value(vdd); + if (!pwr) + WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); + pwr |= SDHCI_VDD2_POWER_180; + } + + if (host->pwr == pwr) + return; + + host->pwr = pwr; + + if (pwr == 0) { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + } else { + gl9755_overcurrent_event_enable(host, false); + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + + pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); + + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); + /* wait stable */ + mdelay(5); + gl9755_overcurrent_event_enable(host, true); + } +} + +static bool sdhci_wait_clock_stable(struct sdhci_host *host) +{ + u16 clk = 0; + + if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), + 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return false; + } + return true; +} + +static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) +{ + /* do this on UHS2 mode */ + if (host->mmc->flags & MMC_UHS2_SD_TRAN) { + sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + sdhci_uhs2_clear_set_irqs(host, + SDHCI_INT_ALL_MASK, + SDHCI_UHS2_INT_ERROR_MASK); + } +} + +static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) +{ + u16 clk_ctrl; + u16 ctrl2; + u8 rst; + + /* need internal clock */ + if (mask & SDHCI_RESET_ALL) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + clk_ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + if ((ctrl2 & SDHCI_CTRL_V4_MODE) && + (ctrl2 & SDHCI_CTRL_UHS2_ENABLE)) { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, + SDHCI_CLOCK_INT_EN, + SDHCI_CLOCK_CONTROL); + sdhci_wait_clock_stable(host); + sdhci_writew(host, + SDHCI_CTRL_V4_MODE, + SDHCI_HOST_CONTROL2); + } + } + + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + + /* reset sd-tran on UHS2 mode if need to reset cmd/data */ + if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) + sdhci_gli_uhs2_reset_sd_tran(host); + + if (mask & SDHCI_RESET_ALL) + host->clock = 0; + + /* hw clears the bit when it's done */ + if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), + 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { + pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); + sdhci_dumpregs(host); + /* manual clear */ + sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); + return; + } +} + static inline void gl9767_vhs_read(struct pci_dev *pdev) { u32 vhs_enable; @@ -1054,6 +1277,7 @@ static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) gli_pcie_enable_msi(slot); slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; sdhci_enable_v4_mode(host); + gl9755_vendor_init(host); return 0; } @@ -1472,17 +1696,24 @@ static const struct sdhci_ops sdhci_gl9755_ops = { .read_w = sdhci_gli_readw, .read_b = sdhci_gli_readb, .set_clock = sdhci_gl9755_set_clock, + .set_power = gl9755_set_power, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, + .reset = sdhci_gl9755_reset, .set_uhs_signaling = sdhci_set_uhs_signaling, .voltage_switch = sdhci_gli_voltage_switch, + .dump_uhs2_regs = sdhci_uhs2_dump_regs, + .set_timeout = sdhci_uhs2_set_timeout, + .irq = sdhci_uhs2_irq, + .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, }; const struct sdhci_pci_fixes sdhci_gl9755 = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, .probe_slot = gli_probe_slot_gl9755, + .add_host = sdhci_pci_uhs2_add_host, + .remove_host = sdhci_pci_uhs2_remove_host, .ops = &sdhci_gl9755_ops, #ifdef CONFIG_PM_SLEEP .resume = sdhci_pci_gli_resume,