From patchwork Thu Sep 14 06:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCEC3EDE983 for ; Thu, 14 Sep 2023 07:00:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232206AbjINHAf (ORCPT ); Thu, 14 Sep 2023 03:00:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229460AbjINHAe (ORCPT ); Thu, 14 Sep 2023 03:00:34 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48678CD8; Thu, 14 Sep 2023 00:00:30 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38E6SS2M006211; Thu, 14 Sep 2023 07:00:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=CFJMCiR1Bo0Zs0u0v0vhwfmpU2tjmHZnbZry9lOc/ak=; b=now9rawAAN+sLZgAW9v8PvRkCgPje0hdNiBlWHwkaC1PVwHm1gJmaXrNpF+ZwF/FX9HP mWVCCfy4ppIYXWjw6Bqk3O+1rvv/lLPZUZ0FyBIXhPBGQ/GZul/LqSqd0HXATM4gUt4r BMWfc9mizPUfGla62bonGC8YyG6IFwE5Wyv9CRNtEppe8cGcwNgLDjDBTc6L5fFR9tsT zs6ayPPMRNPTPvK83fHI37pQ2jjzpb03aXTzwadofThrbFJ3zqKAJMcOmlwQNroFsPs/ G2SNAR/q9opxRharGWffIQFbrMW5q5D6hP9rIoseFC2/5R4nnknQwLHBsflpUvk+k4AB SQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t3r15rnb4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 07:00:24 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38E70MNE016955 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 07:00:22 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 00:00:17 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:51 +0530 Subject: [PATCH v2 01/11] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" , X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=2123; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=et3sbNNIo4FjZBdgJ3tqzZdx4KTgZ9SvcoeqRTD+t+M=; b=a4zoKlRUweg4vBAcCp/aBCXpZJFNyRz1BS3djGaLExd3N4Np87yZLEWPHI5WqLNZyciyajzV5 rkDUDkLQd1tAl3UiTGxDm+AntDiN9wpTOba7X+OoBnqHL047CzUXFle X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1bF7F7q9bYES3-dm8AHcVlagZ83aWq3A X-Proofpoint-ORIG-GUID: 1bF7F7q9bYES3-dm8AHcVlagZ83aWq3A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_03,2023-09-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=920 bulkscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140061 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Cc: stable@vger.kernel.org Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Include the stable mailing list - Keep the CLK_SET_RATE_PARENT in UBI32 PLL, looks like these PLL rates can be changed. So don't drop the flag. --- drivers/clk/qcom/gcc-ipq8074.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 63ac2ced76bb..b7faf12a511a 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -75,7 +75,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -121,7 +120,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -154,7 +152,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -188,7 +185,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -201,7 +197,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -266,7 +261,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Thu Sep 14 06:59:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A00CEDE983 for ; Thu, 14 Sep 2023 07:00:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234381AbjINHAt (ORCPT ); Thu, 14 Sep 2023 03:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229589AbjINHAq (ORCPT ); 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Thu, 14 Sep 2023 07:00:29 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38E70S2h024534 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 07:00:28 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 00:00:22 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:52 +0530 Subject: [PATCH v2 02/11] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-2-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" , X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=2133; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=rsIYjMjr7l4hRP/TaRaz8xhUIe4rolVSZ1qvNyYYjEQ=; b=t/1AQcU7XZaufByt68IBdPr9TvzKEdidvZ2yTtqo4bdwmmYBU+2MRE81GEWdZGnCDwkgccbl/ gHFtBwGUn/ZAjQeWm09BvG2KAxEtGtr0F5XcGpfAXx0g2o6H5j38j5n X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: D-JTW6z4TJi9HkgY__X_DeTFlIsGMnVy X-Proofpoint-GUID: D-JTW6z4TJi9HkgY__X_DeTFlIsGMnVy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_03,2023-09-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=889 spamscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140062 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Cc: stable@vger.kernel.org Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - Include the stable mailing list - Keep the CLK_SET_RATE_PARENT in UBI32 PLL, looks like these PLL rates can be changed. So don't drop the flag. --- drivers/clk/qcom/gcc-ipq6018.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c index 6120fbbc5de0..f9494fa1b871 100644 --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c @@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -161,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -192,7 +189,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -243,7 +239,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -274,7 +269,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Thu Sep 14 06:59:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C53EDEDE988 for ; Thu, 14 Sep 2023 07:01:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235755AbjINHBH (ORCPT ); Thu, 14 Sep 2023 03:01:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235782AbjINHBE (ORCPT ); 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Thu, 14 Sep 2023 07:00:55 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38E70X4a017222 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 07:00:33 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 00:00:28 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:53 +0530 Subject: [PATCH v2 03/11] clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-3-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Kathiravan Thirumoorthy ---- Changes in V2: - New patch Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-ipq5018.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 19dc2b71cacf..2a3c0659b700 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -128,7 +128,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -143,7 +142,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -158,7 +156,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Thu Sep 14 06:59:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD5CEDE98A for ; Thu, 14 Sep 2023 07:00:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234521AbjINHAu (ORCPT ); Thu, 14 Sep 2023 03:00:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235337AbjINHAt (ORCPT ); Thu, 14 Sep 2023 03:00:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DE8BE58; Thu, 14 Sep 2023 00:00:44 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38E70YLh021904; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") Signed-off-by: Kathiravan Thirumoorthy ---- Changes in V2: - No changes Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-ipq9574.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 8f430367299e..e8190108e1ae 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { &gpll0_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_fixed_factor_ops, }, }; @@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = { &gpll0_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; @@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; @@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_ro_ops, }, }; From patchwork Thu Sep 14 06:59:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384695 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50BD0EDE98B for ; Thu, 14 Sep 2023 07:01:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232284AbjINHBI (ORCPT ); Thu, 14 Sep 2023 03:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235337AbjINHBC (ORCPT ); Thu, 14 Sep 2023 03:01:02 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CD25BD; Thu, 14 Sep 2023 00:00:58 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38E3ftLZ030421; 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Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - No change --- drivers/clk/qcom/gcc-ipq5332.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index b02026f8549b..6c74a117ef0b 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -114,7 +114,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -154,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; From patchwork Thu Sep 14 06:59:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384694 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2AEEEDE988 for ; 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Thu, 14 Sep 2023 00:00:44 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:56 +0530 Subject: [PATCH v2 06/11] dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-6-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" , Krzysztof Kozlowski X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1131; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=RJl8bxvvLk6GpCZveb20/nrwi1AzkUemX9HSqoBKd1o=; b=IHwFjXd4Qo+LlCRkw6H68m3aLbOlV4yO6PY5oKyvzy2bjOUXB/+b/WAYnzi/jdGS+4aXF5mQV iOdcirC0I+VCs/GbU1ccs+q4NeJo9eS+1D5v8Vw7CN19yFVU4AcN12k X-Developer-Key: i=quic_kathirav@quicinc.com; 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Document the same. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Pick up the R-b tag --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index d2e25ff6db7f..a38413f8d132 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -125,10 +125,12 @@ allOf: items: - description: primary pll parent of the clock driver - description: XO clock + - description: GCC GPLL0 clock source clock-names: items: - const: pll - const: xo + - const: gpll0 - if: properties: From patchwork Thu Sep 14 06:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27F70EDE983 for ; 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Thu, 14 Sep 2023 00:00:51 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:57 +0530 Subject: [PATCH v2 07/11] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" , Robert Marko X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1271; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=0WLXM7UqBZpsd0pHbjXLnJu/oCGwNfmF+vKO/PV2u8k=; b=fycx2BXyEF2j8rwWSoyeowB/WDt1d7i0/e6F/ZzF6MjPiruezY08l5sje0mGps2MWjtNyCboh K/puEx6hiooAuC61b9fZdGKgTY0FQ+XqOTnJez5ZbGOiY8nQOxEolf2 X-Developer-Key: i=quic_kathirav@quicinc.com; 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Once the cpufreq driver is available, APSS PLL will be configured and select the rate based on the opp table and the source will be changed to APSS_PLL_EARLY. Without this patch, CPU Freq driver reports that CPU is running at 24MHz instead of the 800MHz. Reviewed-by: Konrad Dybcio Tested-by: Robert Marko Signed-off-by: Kathiravan Thirumoorthy --- Changes in V2: - Pick up te R-b and T-b tags. Thanks Robert! --- drivers/clk/qcom/apss-ipq6018.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c index f2f502e2d5a4..4e13a085a857 100644 --- a/drivers/clk/qcom/apss-ipq6018.c +++ b/drivers/clk/qcom/apss-ipq6018.c @@ -20,16 +20,19 @@ enum { P_XO, + P_GPLL0, P_APSS_PLL_EARLY, }; static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { { .fw_name = "xo" }, + { .fw_name = "gpll0" }, { .fw_name = "pll" }, }; static const struct parent_map parents_apcs_alias0_clk_src_map[] = { { P_XO, 0 }, + { P_GPLL0, 4 }, { P_APSS_PLL_EARLY, 5 }, }; From patchwork Thu Sep 14 06:59:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F17DEDE98A for ; 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Thu, 14 Sep 2023 00:00:57 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:58 +0530 Subject: [PATCH v2 08/11] arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1255; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=1ug/sW+kzuMORC21mgnQOlnFEwUOksulPA68xrrHMRg=; b=G8S+bURsKhd4b3okT0iuutbUpLpoPigwAAzr1aK669ErDT/RX8ZBAcoQJddUb19yHbF6l8ua2 aOIrpsQf8gzCW8PQ9lp3hQ2KNRTns9YiqrTCOTHyYhkkWp7GD/MUKB2 X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hWmykwGiHMv2sAQezU959x2G9BRfJnBS X-Proofpoint-ORIG-GUID: hWmykwGiHMv2sAQezU959x2G9BRfJnBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_03,2023-09-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=845 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=2 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140062 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - Splitted the change into target specific file --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 00ed71936b47..0be19267bdcf 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -719,8 +719,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq8074-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #clock-cells = <1>; #mbox-cells = <1>; From patchwork Thu Sep 14 06:59:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0833EDE988 for ; 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Thu, 14 Sep 2023 00:01:03 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:59 +0530 Subject: [PATCH v2 09/11] arm64: dts: qcom: ipq6018: include the GPLL0 as clock provider for mailbox MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-9-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1226; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=0V7ycfieCR7gyMd8CbT+YHreQwaCQ4y1HnsMb/C1JmE=; b=F+6GRbFKbSfTRkzD2VAF21Y90M9zygGTvB1ZSbRelL94mZYJc6kHmMZ+d7N8+Q8dpwoODc3al vcEz3YbAgexCkjRm43ATwFQ5gVUSSwLOsHokpcEV3s1lgC+DdcL5B2Z X-Developer-Key: i=quic_kathirav@quicinc.com; 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Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - Splitted the change into target specific file --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 47b8b1d6730a..a30a5b893762 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -619,8 +619,8 @@ apcs_glb: mailbox@b111000 { compatible = "qcom,ipq6018-apcs-apps-global"; reg = <0x0 0x0b111000 0x0 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; From patchwork Thu Sep 14 07:00:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 442FDEDE988 for ; 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Thu, 14 Sep 2023 00:01:08 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:30:00 +0530 Subject: [PATCH v2 10/11] arm64: dts: qcom: ipq9574: include the GPLL0 as clock provider for mailbox MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-10-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1231; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=veUniM41mszJd7aRSOLoQFrZylo/OvtixnEi2jYQD+g=; b=YmuzWpY0/eLnQ8avGXiBUEaaMIW0z1Z/W9uWq0dWK6y1RfzlsnoHOA6ouEQC1mx1C8bLnBn/o l5Ggj1UQHTUA4Z0FgcoPTteTe/6/hJmSJKXagPbU0QoKbD/xXL7mQI+ X-Developer-Key: i=quic_kathirav@quicinc.com; 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Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - Splitted the change into target specific file --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 51aba071c1eb..89edb4b852df 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -652,8 +652,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a73pll>, <&xo_board_clk>; - clock-names = "pll", "xo"; + clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; }; From patchwork Thu Sep 14 07:00:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 13384701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6566EDE983 for ; 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Thu, 14 Sep 2023 00:01:13 -0700 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:30:01 +0530 Subject: [PATCH v2 11/11] arm64: dts: qcom: ipq5332: include the GPLL0 as clock provider for mailbox MIME-Version: 1.0 Message-ID: <20230913-gpll_cleanup-v2-11-c8ceb1a37680@quicinc.com> References: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> In-Reply-To: <20230913-gpll_cleanup-v2-0-c8ceb1a37680@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , "Sricharan Ramabadhran" , Gokul Sriram Palanisamy , Varadarajan Narayanan , Anusha Rao , Devi Priya , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1694674810; l=1223; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=aXroxBycIALRxsYiDXTUpvPyc+RSgTjo74t6paOuFH0=; b=48mqn/p5Fc7dWJyGe5Se2k9cTv/rMTwuHaLI8XeHBz8r9JW7ryN34H1SSYrBd7DRr68idmo83 z3QCZHFgbKcCFCBriV92IMZnMjZA4aVJrWFHHQJHaXZRS8NbprR5AD+ X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ftb7vQ2iUuzIAdshwAYuCC3Txne84cHt X-Proofpoint-ORIG-GUID: Ftb7vQ2iUuzIAdshwAYuCC3Txne84cHt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_04,2023-09-13_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 lowpriorityscore=0 adultscore=1 spamscore=0 impostorscore=0 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 mlxlogscore=803 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140062 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org While the kernel is booting up, APSS PLL will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- Changes in V2: - Splitted the change into target specific file --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..82761ae199a9 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -335,8 +335,8 @@ apcs_glb: mailbox@b111000 { "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; #clock-cells = <1>; - clocks = <&a53pll>, <&xo_board>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #mbox-cells = <1>; };