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Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 01/13] virtio: Add shared memory capability Date: Fri, 15 Sep 2023 19:11:18 +0800 Message-ID: <20230915111130.24064-2-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|SA1PR12MB6821:EE_ X-MS-Office365-Filtering-Correlation-Id: 97bd9e2f-f893-4c7b-ead0-08dbb5dca1fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 148f8cfTnr0zV2+MVq56MzKY/rrA52TUIxkrYXKRJedW1xegN+Y59iHW1xT0X2E684pdJRBsHpz3BQIs7XITbXL1GAjxJNehgDus85aNp/1NprjyZmHfpkUw6KxP5vCIXJtSoF0Cr2HHVYaFT3owlK9zshQI1w3yk3bQqzx3LriGu/mftprQvlKUCoT4wUwvAXQroTGdKJObT2mFF0TJxHFk2hEkImR8vFTNjEPP5hIDn63hwr/2wEGnqIA7GUWwKyVvrOy+UYZ5SxigaQtsqyFHv+ac4+c461Plzg08WG0+H6Xtj/8nH7sFuY3TSk08QZGtg8UHiZYzUIw0oFtesNuUE+H2OT6mSC/gM0LnpFXczbU/IO/jrlpWJoriyIeK7PvZCI7x4L1H20eWfsPo7fEbGPLMSXCVxRBl+uSL42PkLJuDTt8CkHmT+sBN3YCfFwGQS+gV+1k7aOmQtcGF4QC1ZbaHfxfNgdmVxav0+Wn6C4GMtkH5hu75NReD3vQWqFVyJbrOfNWPEJd6nGVFxGlpsDRuBtJVw6M4MB++KV634q82y5sQlADQEiLtw+9qg8y3fRHiXerl9g3wuI145wcd1kXQj0s2Y1aFw/bnXZ0IytyjHa/BRvxXqd7lyaOH9e/PE0Dy0p0nOsAEg9qXDkReKVKzxgw/+AoAW7tBrdC/vU7coPDpNgl3zWWg7BfCAEBRRCPs39Z5zK/eCqVsQr/Syc825udELPaCW7CFS3bQnjqSEQSv6RA2YjyaJaLLu2KbqYYBPHLBCX1NEPUYxy5QTK0OEogm1h6CdprpeYc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(376002)(396003)(136003)(451199024)(1800799009)(82310400011)(186009)(46966006)(36840700001)(40470700004)(110136005)(921005)(81166007)(7696005)(356005)(86362001)(36756003)(40460700003)(478600001)(47076005)(40480700001)(82740400003)(36860700001)(70206006)(2616005)(5660300002)(336012)(16526019)(426003)(41300700001)(316002)(8936002)(4326008)(8676002)(26005)(54906003)(2906002)(7416002)(70586007)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:21.7012 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97bd9e2f-f893-4c7b-ead0-08dbb5dca1fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6821 From: "Dr. David Alan Gilbert" Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow defining shared memory regions with sizes and offsets of 2^32 and more. Multiple instances of the capability are allowed and distinguished by a device-specific 'id'. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Antonio Caggiano Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Huang Rui Tested-by: Akihiko Odaki Acked-by: Huang Rui Reviewed-by: Gurchetan Singh Reviewed-by: Akihiko Odaki Signed-off-by: Huang Rui --- This patch is already under review as part of the "rutabaga_gfx + gfxstream" series (already in v13) and has been included here because of dependency. hw/virtio/virtio-pci.c | 18 ++++++++++++++++++ include/hw/virtio/virtio-pci.h | 4 ++++ 2 files changed, 22 insertions(+) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index edbc0daa18..da8c9ea12d 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1435,6 +1435,24 @@ static int virtio_pci_add_mem_cap(VirtIOPCIProxy *proxy, return offset; } +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, + uint8_t bar, uint64_t offset, uint64_t length, + uint8_t id) +{ + struct virtio_pci_cap64 cap = { + .cap.cap_len = sizeof cap, + .cap.cfg_type = VIRTIO_PCI_CAP_SHARED_MEMORY_CFG, + }; + + cap.cap.bar = bar; + cap.cap.length = cpu_to_le32(length); + cap.length_hi = cpu_to_le32(length >> 32); + cap.cap.offset = cpu_to_le32(offset); + cap.offset_hi = cpu_to_le32(offset >> 32); + cap.cap.id = id; + return virtio_pci_add_mem_cap(proxy, &cap.cap); +} + static uint64_t virtio_pci_common_read(void *opaque, hwaddr addr, unsigned size) { diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h index ab2051b64b..5a3f182f99 100644 --- a/include/hw/virtio/virtio-pci.h +++ b/include/hw/virtio/virtio-pci.h @@ -264,4 +264,8 @@ unsigned virtio_pci_optimal_num_queues(unsigned fixed_queues); void virtio_pci_set_guest_notifier_fd_handler(VirtIODevice *vdev, VirtQueue *vq, int n, bool assign, bool with_irqfd); + +int virtio_pci_add_shm_cap(VirtIOPCIProxy *proxy, uint8_t bar, uint64_t offset, + uint64_t length, uint8_t id); + #endif From patchwork Fri Sep 15 11:11:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21052EE6458 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [QEMU PATCH v5 02/13] virtio-gpu: CONTEXT_INIT feature Date: Fri, 15 Sep 2023 19:11:19 +0800 Message-ID: <20230915111130.24064-3-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|PH7PR12MB6468:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c6a94c9-4ec8-446c-fcd5-08dbb5dca5b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BNhb3Yb5fru9dUEURHmM4V70UEy7QC3JPfsvQSwv4Zc5olfd2kD84Th6v2l059mQwHlOyZm/gNtJ2keULlc1jna/6UDPqhy62BgjApCgkP49uTzjuaJLywrn2wSLVTNr3ve2OrPbyqD5AaiISp9ckyOc8vIfMFRUyDMG+vIojcVwXsRhcei/h7v2mCdxir4lHlEL+IcXtvWUeBLxvgiwmo83umSw5ChLtNJK+ImLVUF+EvQInnnClSOoD8IXx00vdxZhHd9iiBQdeelRS7xnK4E1ffbGSMfZo2A/TucQ1qByAeiPNtqQHZscsheOQZ7g8ybAL4GENSbJlMVO5Ms95f9cv7LhzOKcj/QmJJq2aF+Jb7NMntJ8vn6Kb0QmBaXGwBhJ9HD+UgJBCAVeoTeBOTUxwhH/woqaPyBAK+jLeFYgGwDOLbiYXk1S3lOFIZpyu+JXcr62LUPK2j/N0x/z0boUM/YeTVhE92nJGsap+WlV607ilF51MvwhPiL18WuAeZi6yMPm6GnlSQFjQBOuDenMD79LG35LVBXtTWJHH3JaXihfW3yPWXk0ImM8GiNVwzW5eyhI/i83U4kATHiCdNj+QyJnfZNjIeY24VTeZ4FEZslYad4zSio56ANT5L2ENpdC3W9FidoV5k/5TusO257D7uJUSrqkd13e6X78+0QRl4aaNgoFHUskfFAa4R42JRzM4uPg2dyYqKySq18RwYDAxcnVfT4WBZI7dnQYPsfU1VAI91QbJ9Gh2nlggT/gM+pSGTNMO7Sx/7phGd5Ab9osTbWwDP4D6eJJifcQCHs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(376002)(136003)(82310400011)(186009)(451199024)(1800799009)(36840700001)(46966006)(40470700004)(336012)(8676002)(356005)(8936002)(110136005)(4326008)(2906002)(921005)(40480700001)(316002)(16526019)(47076005)(36860700001)(54906003)(1076003)(70206006)(7696005)(426003)(26005)(70586007)(2616005)(41300700001)(40460700003)(82740400003)(5660300002)(81166007)(7416002)(86362001)(36756003)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:28.0138 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c6a94c9-4ec8-446c-fcd5-08dbb5dca5b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6468 From: Antonio Caggiano The feature can be enabled when a backend wants it. Signed-off-by: Antonio Caggiano Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Akihiko Odaki Tested-by: Huang Rui Acked-by: Huang Rui Reviewed-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Akihiko Odaki Signed-off-by: Huang Rui --- This patch is already under review as part of the "rutabaga_gfx + gfxstream" series (already in v13) and has been included here because of dependency. hw/display/virtio-gpu-base.c | 3 +++ include/hw/virtio/virtio-gpu.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index ca1fb7b16f..4f2b0ba1f3 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -232,6 +232,9 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features, if (virtio_gpu_blob_enabled(g->conf)) { features |= (1 << VIRTIO_GPU_F_RESOURCE_BLOB); } + if (virtio_gpu_context_init_enabled(g->conf)) { + features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT); + } return features; } diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 390c4642b8..8377c365ef 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -93,6 +93,7 @@ enum virtio_gpu_base_conf_flags { VIRTIO_GPU_FLAG_EDID_ENABLED, VIRTIO_GPU_FLAG_DMABUF_ENABLED, VIRTIO_GPU_FLAG_BLOB_ENABLED, + VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, }; #define virtio_gpu_virgl_enabled(_cfg) \ @@ -105,6 +106,8 @@ enum virtio_gpu_base_conf_flags { (_cfg.flags & (1 << VIRTIO_GPU_FLAG_DMABUF_ENABLED)) #define virtio_gpu_blob_enabled(_cfg) \ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED)) +#define virtio_gpu_context_init_enabled(_cfg) \ + (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED)) struct virtio_gpu_base_conf { uint32_t max_outputs; From patchwork Fri Sep 15 11:11:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC956EE6457 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 03/13] virtio-gpu: hostmem Date: Fri, 15 Sep 2023 19:11:20 +0800 Message-ID: <20230915111130.24064-4-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|PH7PR12MB8427:EE_ X-MS-Office365-Filtering-Correlation-Id: 92af8e65-8bb8-411a-4b71-08dbb5dca952 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T/8zGYpfvegyyEORgClCllv3L4xzWi2bSuOpAY2WctE2jxVaBKT38l8bzchHrtS3e0IHZe7ntiNk/1swDXj6BPEZYMJB8D5yXfL/ihdmctJXk9n9o5AMm5/oV+gjnHokzc0a35jYfqfe4Q6GlQYscp5DahQfNRRuZh0ggO3Yg1XLr35Npo4gQ74EtUXOd2tdUW+5DX1BlcUr6HHE+9vFK6C3jLPSik35lkH4quVYl0uC6YCUh7QY/6FpAi15+yz9/goAIbGGpwtlAWWpYiHW1OeW+uEqjR4PpLDhKUSD6GUoMM6iQ6LqYbrOemy6OeLNfSAXtrzJ6gV7iZHQNKTVg2Wy6YFuHsRhKj8YEdU2o8Yzc1JsajBFNDQeVYMH5F4AYS35tWeVJu4UutAK0jOcZmAyvm7cwf35jt2DT3G+4wTsS4OM35IetQC1GCdqlKRKoKAACgisXdJuJVtdZIsorle3noYRb88r2xxgEZRhYD66m3hy5kuTliqgSqdSmOs/1sP6ibySHzezn50qd2QIwfus0ek/sEQGnHdXEVv521MmkbOgfhaAvDNS3fPDWV0geehO+tNR3s3VY5ZYbKS5VmzuXFHq5rTIa/Qcdj79dCCrAUvlFa1kpcKANt5rZZ7CVRZKPQcBmeLx1hstX+8dQXKtkTa0nS9s/w9SDHUPafArPjqUYy/on1wRiIxlPufaNNNJJCs8oAKlpDJSfWnLpk4dWjosctFkJ/yidcmxKGZf7l75iZ/JfBbRRmTDxnMwa6o5x1O7kacj7vdaNvUvLVUE7cYnkbvVbEGU1CmtKrM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(346002)(376002)(39860400002)(82310400011)(1800799009)(451199024)(186009)(40470700004)(36840700001)(46966006)(8676002)(5660300002)(16526019)(316002)(54906003)(70586007)(110136005)(70206006)(4326008)(2616005)(7696005)(40480700001)(356005)(82740400003)(921005)(81166007)(8936002)(1076003)(83380400001)(426003)(336012)(6666004)(41300700001)(26005)(478600001)(7416002)(47076005)(2906002)(36860700001)(40460700003)(86362001)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:34.0451 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92af8e65-8bb8-411a-4b71-08dbb5dca952 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8427 From: Gerd Hoffmann Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu. Signed-off-by: Antonio Caggiano Tested-by: Alyssa Ross Tested-by: Akihiko Odaki Tested-by: Huang Rui Acked-by: Huang Rui Acked-by: Michael S. Tsirkin Reviewed-by: Akihiko Odaki Signed-off-by: Huang Rui --- This patch is already under review as part of the "rutabaga_gfx + gfxstream" series (already in v13) and has been included here because of dependency. hw/display/virtio-gpu-pci.c | 14 ++++++++++++++ hw/display/virtio-gpu.c | 1 + hw/display/virtio-vga.c | 33 ++++++++++++++++++++++++--------- include/hw/virtio/virtio-gpu.h | 5 +++++ 4 files changed, 44 insertions(+), 9 deletions(-) diff --git a/hw/display/virtio-gpu-pci.c b/hw/display/virtio-gpu-pci.c index 93f214ff58..da6a99f038 100644 --- a/hw/display/virtio-gpu-pci.c +++ b/hw/display/virtio-gpu-pci.c @@ -33,6 +33,20 @@ static void virtio_gpu_pci_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) DeviceState *vdev = DEVICE(g); int i; + if (virtio_gpu_hostmem_enabled(g->conf)) { + vpci_dev->msix_bar_idx = 1; + vpci_dev->modern_mem_bar_idx = 2; + memory_region_init(&g->hostmem, OBJECT(g), "virtio-gpu-hostmem", + g->conf.hostmem); + pci_register_bar(&vpci_dev->pci_dev, 4, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_PREFETCH | + PCI_BASE_ADDRESS_MEM_TYPE_64, + &g->hostmem); + virtio_pci_add_shm_cap(vpci_dev, 4, 0, g->conf.hostmem, + VIRTIO_GPU_SHM_ID_HOST_VISIBLE); + } + virtio_pci_force_virtio_1(vpci_dev); if (!qdev_realize(vdev, BUS(&vpci_dev->bus), errp)) { return; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index bbd5c6561a..48ef0d9fad 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1509,6 +1509,7 @@ static Property virtio_gpu_properties[] = { 256 * MiB), DEFINE_PROP_BIT("blob", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_BLOB_ENABLED, false), + DEFINE_PROP_SIZE("hostmem", VirtIOGPU, parent_obj.conf.hostmem, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index e6fb0aa876..c8552ff760 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -115,17 +115,32 @@ static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) pci_register_bar(&vpci_dev->pci_dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); - /* - * Configure virtio bar and regions - * - * We use bar #2 for the mmio regions, to be compatible with stdvga. - * virtio regions are moved to the end of bar #2, to make room for - * the stdvga mmio registers at the start of bar #2. - */ - vpci_dev->modern_mem_bar_idx = 2; - vpci_dev->msix_bar_idx = 4; vpci_dev->modern_io_bar_idx = 5; + if (!virtio_gpu_hostmem_enabled(g->conf)) { + /* + * Configure virtio bar and regions + * + * We use bar #2 for the mmio regions, to be compatible with stdvga. + * virtio regions are moved to the end of bar #2, to make room for + * the stdvga mmio registers at the start of bar #2. + */ + vpci_dev->modern_mem_bar_idx = 2; + vpci_dev->msix_bar_idx = 4; + } else { + vpci_dev->msix_bar_idx = 1; + vpci_dev->modern_mem_bar_idx = 2; + memory_region_init(&g->hostmem, OBJECT(g), "virtio-gpu-hostmem", + g->conf.hostmem); + pci_register_bar(&vpci_dev->pci_dev, 4, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_PREFETCH | + PCI_BASE_ADDRESS_MEM_TYPE_64, + &g->hostmem); + virtio_pci_add_shm_cap(vpci_dev, 4, 0, g->conf.hostmem, + VIRTIO_GPU_SHM_ID_HOST_VISIBLE); + } + if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) { /* * with page-per-vq=off there is no padding space we can use diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 8377c365ef..de4f624e94 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -108,12 +108,15 @@ enum virtio_gpu_base_conf_flags { (_cfg.flags & (1 << VIRTIO_GPU_FLAG_BLOB_ENABLED)) #define virtio_gpu_context_init_enabled(_cfg) \ (_cfg.flags & (1 << VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED)) +#define virtio_gpu_hostmem_enabled(_cfg) \ + (_cfg.hostmem > 0) struct virtio_gpu_base_conf { uint32_t max_outputs; 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Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Emmanouil Pitsidianakis , Huang Rui Subject: [QEMU PATCH v5 04/13] virtio-gpu: blob prep Date: Fri, 15 Sep 2023 19:11:21 +0800 Message-ID: <20230915111130.24064-5-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017097:EE_|SN7PR12MB8601:EE_ X-MS-Office365-Filtering-Correlation-Id: 01b82a7a-26d3-457d-5f72-08dbb5dcad12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:40.3370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01b82a7a-26d3-457d-5f72-08dbb5dcad12 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017097.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8601 From: Antonio Caggiano This adds preparatory functions needed to: - decode blob cmds - tracking iovecs Signed-off-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Tested-by: Akihiko Odaki Tested-by: Huang Rui Acked-by: Huang Rui Reviewed-by: Emmanouil Pitsidianakis Reviewed-by: Akihiko Odaki Signed-off-by: Huang Rui --- This patch is already under review as part of the "rutabaga_gfx + gfxstream" series (already in v13) and has been included here because of dependency. hw/display/virtio-gpu.c | 10 +++------- include/hw/virtio/virtio-gpu-bswap.h | 15 +++++++++++++++ include/hw/virtio/virtio-gpu.h | 5 +++++ 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 48ef0d9fad..3e658f1fef 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -33,15 +33,11 @@ #define VIRTIO_GPU_VM_VERSION 1 -static struct virtio_gpu_simple_resource* -virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id); static struct virtio_gpu_simple_resource * virtio_gpu_find_check_resource(VirtIOGPU *g, uint32_t resource_id, bool require_backing, const char *caller, uint32_t *error); -static void virtio_gpu_cleanup_mapping(VirtIOGPU *g, - struct virtio_gpu_simple_resource *res); static void virtio_gpu_reset_bh(void *opaque); void virtio_gpu_update_cursor_data(VirtIOGPU *g, @@ -116,7 +112,7 @@ static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor) cursor->resource_id ? 1 : 0); } -static struct virtio_gpu_simple_resource * +struct virtio_gpu_simple_resource * virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id) { struct virtio_gpu_simple_resource *res; @@ -904,8 +900,8 @@ void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, g_free(iov); } -static void virtio_gpu_cleanup_mapping(VirtIOGPU *g, - struct virtio_gpu_simple_resource *res) +void virtio_gpu_cleanup_mapping(VirtIOGPU *g, + struct virtio_gpu_simple_resource *res) { virtio_gpu_cleanup_mapping_iov(g, res->iov, res->iov_cnt); res->iov = NULL; diff --git a/include/hw/virtio/virtio-gpu-bswap.h b/include/hw/virtio/virtio-gpu-bswap.h index 637a0585d0..dd1975e2d4 100644 --- a/include/hw/virtio/virtio-gpu-bswap.h +++ b/include/hw/virtio/virtio-gpu-bswap.h @@ -70,6 +70,21 @@ virtio_gpu_create_blob_bswap(struct virtio_gpu_resource_create_blob *cblob) le64_to_cpus(&cblob->size); } +static inline void +virtio_gpu_map_blob_bswap(struct virtio_gpu_resource_map_blob *mblob) +{ + virtio_gpu_ctrl_hdr_bswap(&mblob->hdr); + le32_to_cpus(&mblob->resource_id); + le64_to_cpus(&mblob->offset); +} + +static inline void +virtio_gpu_unmap_blob_bswap(struct virtio_gpu_resource_unmap_blob *ublob) +{ + virtio_gpu_ctrl_hdr_bswap(&ublob->hdr); + le32_to_cpus(&ublob->resource_id); +} + static inline void virtio_gpu_scanout_blob_bswap(struct virtio_gpu_set_scanout_blob *ssb) { diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index de4f624e94..55973e112f 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -257,6 +257,9 @@ void virtio_gpu_base_fill_display_info(VirtIOGPUBase *g, void virtio_gpu_base_generate_edid(VirtIOGPUBase *g, int scanout, struct virtio_gpu_resp_edid *edid); /* virtio-gpu.c */ +struct virtio_gpu_simple_resource * +virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id); + void virtio_gpu_ctrl_response(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd, struct virtio_gpu_ctrl_hdr *resp, @@ -275,6 +278,8 @@ int virtio_gpu_create_mapping_iov(VirtIOGPU *g, uint32_t *niov); void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, struct iovec *iov, uint32_t count); +void virtio_gpu_cleanup_mapping(VirtIOGPU *g, + struct virtio_gpu_simple_resource *res); void virtio_gpu_process_cmdq(VirtIOGPU *g); void virtio_gpu_device_realize(DeviceState *qdev, Error **errp); void virtio_gpu_reset(VirtIODevice *vdev); From patchwork Fri Sep 15 11:11:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 537A5EE6456 for ; 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Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui , Antonio Caggiano Subject: [QEMU PATCH v5 05/13] virtio-gpu: Configure context init for virglrenderer Date: Fri, 15 Sep 2023 19:11:22 +0800 Message-ID: <20230915111130.24064-6-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|DM4PR12MB5184:EE_ X-MS-Office365-Filtering-Correlation-Id: 20d0b8a9-9383-443d-eda5-08dbb5dcb4e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zNzUyIS7lbmsGprOBH+aQOLUy9boun/CoU4y6FrogIYHsE4X8AVBum4TvLn2E0ci82dp08OgAz0PxZAb000gBV5MBJTwKCQHppAmpkcxaZlEaCIwo7Uu5LA6O+lufULfMOT5ttUi/q0JdLd1NtHM/OqQvB4ZUrl7U7teVK2v95J0f71JJ5KxM3bbYTTqI0P48/KB4jfI2EYkOATQTThcxj4qpIcnLUl7iRWiKIFhAizRVt7mmBjLeTO0tZvU2+B2+VmBwyMI/IgKopeYWeyzfO6Ky2e2dnnZdf2Ip/xqKNBc++yAGRQV8wLblxIFcYt0mDDgLz8xoNa14KitI8ThNJAOjbDVjB8IKA95yw8S3qx+GUVRiDNTKazDtpcos8GoDLKEc2NeTT9UgV08Oa96dyyoy9AryFocixq/QPYMAJJlrVSRZcERAnTjlQvCSFQtmufEL/S5lULeWnjjXEkHKeYpq89hrXsDJvLHVEWHjZZhwQmUPQr74Jz/yT8T1zFqtgUNP3oIOekIJ3V0wtMdo5dLYzr8dOVNFcA7zKtgIINEzxMs0QIPLqODN2CTF7YK17S7hf2bqke7h2Ny2+TtpfShAbAvTI+Jvo1acH/+2HTOBvgcX59igwQWIQKaz9eAsTgc6aW17paF0y7zgEUxx6uLWIiQr/A7BE3yR7lEF/u7+lrWlHbzSxH4vt3UwJq9tk/KfMQWqPVtMxH8T8r6UNKKcN1FDwbswAQsDiUJ9/yV3q7fTbPiyPn3dWkbN2dChR1sCh9S0qVVI+SBD5zdD/vyVQ4LxIk1Hy4hpQHl3zo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(136003)(39860400002)(376002)(186009)(1800799009)(82310400011)(451199024)(36840700001)(46966006)(40470700004)(16526019)(5660300002)(26005)(8936002)(1076003)(4326008)(8676002)(40460700003)(2906002)(4744005)(7416002)(86362001)(81166007)(356005)(921005)(82740400003)(83380400001)(36860700001)(47076005)(36756003)(336012)(426003)(40480700001)(7696005)(6666004)(110136005)(2616005)(54906003)(70586007)(70206006)(478600001)(41300700001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:53.4454 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20d0b8a9-9383-443d-eda5-08dbb5dcb4e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5184 Configure context init feature flag for virglrenderer. Originally-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Inverted patch 5 and 6 because we should configure HAVE_VIRGL_CONTEXT_INIT firstly. (Philippe) meson.build | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/meson.build b/meson.build index 98e68ef0b1..ff20d3c249 100644 --- a/meson.build +++ b/meson.build @@ -1068,6 +1068,10 @@ if not get_option('virglrenderer').auto() or have_system or have_vhost_user_gpu prefix: '#include ', dependencies: virgl)) endif + config_host_data.set('HAVE_VIRGL_CONTEXT_INIT', + cc.has_function('virgl_renderer_context_create_with_flags', + prefix: '#include ', + dependencies: virgl)) endif blkio = not_found if not get_option('blkio').auto() or have_block From patchwork Fri Sep 15 11:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 36331EE6457 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui , Antonio Caggiano Subject: [QEMU PATCH v5 06/13] virtio-gpu: Support context init feature with virglrenderer Date: Fri, 15 Sep 2023 19:11:23 +0800 Message-ID: <20230915111130.24064-7-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|SA1PR12MB8095:EE_ X-MS-Office365-Filtering-Correlation-Id: f959d7d3-ab8a-47d0-b842-08dbb5dcb87d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SLkza3en713N31+EauxcBDcLOQh5WV8bcKGM6CUb/p7oyPtKr5SwnQ1cebelQJSR8ANTBgst2uzminkL5ZKCL1MTEvBHezY3lknfrUeYzLfA+umnfDpEO8q7S4zdJdB6h9R9x1dBrdlBcFeSg2XihWOOL7J/KTlYUI6J7PBfBiRcEsTFPfJ0unRvVh+KSCIn7RQ1zlwUF+Qugf/7KwYiRvCZAGjmuGtW/eKX/P8lGziS3cBD82mJlt/9ezoSFuruiFdtGLt0AT8byVJ9+JmDW5BQPMBD3wy2Zw8EnBub5roiD29J2GSNrQhIO1sQDeZvYHOcihWrDRvgEuYZLsgWE0PIDNneXgLp0RM9P+BmWNJZPgWz4Puf10feDCRVmXuouM5Fr3jYkdgf2boMS/Kic7iq7Au0v8VPb3CTkD5TiEKRy8VZSFtmYbNJIMkjpC3XwdpWCqvEkEjtGL9n5am/pYHUfvHuhBZKdj9iX89sWvTasvayQ4LFrM+qZ6axDpmDei5bdZnLGVOqJ0DC53K9fYLiuS1B74Xi/9H/3/l7losGGrsIyPdDiJQHcsf/xPnUCY5nesAgZrScC2YNTuuLq04TQl1appEbFn9hB6fkcofg5f6zPVTGsVwWRrs6C63+QmFT9E5vFpUGTCB2KGw8TZjux3GU5YCQdiMsks1hjmgAfG2O8+wxZLtiJA7G/8Vu5NeLRRLhHuctfix8gYkVqux3erpN/vWsZD2Y+gMTNGzxtMXJgDflK3A3N91PmErJZ54EpU9qg9H6g2NgG00sEN0QNXR6wb15vojeftfUcCs= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199024)(1800799009)(186009)(82310400011)(46966006)(40470700004)(36840700001)(40460700003)(36756003)(86362001)(40480700001)(5660300002)(316002)(7696005)(26005)(70206006)(8676002)(426003)(70586007)(336012)(110136005)(2616005)(8936002)(54906003)(921005)(41300700001)(4326008)(2906002)(16526019)(6666004)(47076005)(81166007)(36860700001)(478600001)(356005)(1076003)(82740400003)(83380400001)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:12:59.4955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f959d7d3-ab8a-47d0-b842-08dbb5dcb87d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8095 Patch "virtio-gpu: CONTEXT_INIT feature" has added the context_init feature flags. We would like to enable the feature with virglrenderer, so add to create virgl renderer context with flags using context_id when valid. Originally-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Inverted patch 5 and 6 because we should configure HAVE_VIRGL_CONTEXT_INIT firstly. (Philippe) hw/display/virtio-gpu-virgl.c | 13 +++++++++++-- hw/display/virtio-gpu.c | 2 ++ 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 8bb7a2c21f..312953ec16 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -106,8 +106,17 @@ static void virgl_cmd_context_create(VirtIOGPU *g, trace_virtio_gpu_cmd_ctx_create(cc.hdr.ctx_id, cc.debug_name); - virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, - cc.debug_name); + if (cc.context_init) { +#ifdef HAVE_VIRGL_CONTEXT_INIT + virgl_renderer_context_create_with_flags(cc.hdr.ctx_id, + cc.context_init, + cc.nlen, + cc.debug_name); + return; +#endif + } + + virgl_renderer_context_create(cc.hdr.ctx_id, cc.nlen, cc.debug_name); } static void virgl_cmd_context_destroy(VirtIOGPU *g, diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 3e658f1fef..a66cbd9930 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1506,6 +1506,8 @@ static Property virtio_gpu_properties[] = { DEFINE_PROP_BIT("blob", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_BLOB_ENABLED, false), DEFINE_PROP_SIZE("hostmem", VirtIOGPU, parent_obj.conf.hostmem, 0), + DEFINE_PROP_BIT("context_init", VirtIOGPU, parent_obj.conf.flags, + VIRTIO_GPU_FLAG_CONTEXT_INIT_ENABLED, false), DEFINE_PROP_END_OF_LIST(), }; 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bh=SviVy3p1SaMQZ+DeOFS4BSuC7/Crlp0rXdVO1dxpWdg=; b=U2/ZhPC/2ePWFg5hIRScJactE8ncxRRs9C+OBYg1YTtPoN9c/LzJRxmIxPfv3o1zzmdcE23BlQPwIt/oDhuf4fBKhk0xNjsdey+JcnCtO5y7AK/y+F8s4AzZVDt4SXVQT8S56yHtjCiA4tOzR/4I7cDI/mVe0BOZ6cZkVNJXKgA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [QEMU PATCH v5 07/13] softmmu/memory: enable automatic deallocation of memory regions Date: Fri, 15 Sep 2023 19:11:24 +0800 Message-ID: <20230915111130.24064-8-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017096:EE_|BL1PR12MB5240:EE_ X-MS-Office365-Filtering-Correlation-Id: f9ce3266-f3d1-4ed5-5736-08dbb5dcbc0d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /ySd+YhWxbNTYgniZ4QXeOr6tTNtpYQG3G+qcl9EULXzKb19YRxV/MwdM0YbvpBtN+44yQSiyTI8dP75jZp4euY/kwsOGNDPo/Mm5D0/8zcp5oQceMZgi673aLZpYfrAMOlUni6L5b0w3e0MKy9Y/SDrVRsB5/0/PD7dF9O6q/bCJgb8CFxQOabZ2g8fIUII75yWYjwXBbLNJ2AIVG6WaLELKUNHWvSSWl6dhzVa17qwRfNfaL6+RWddepti3ebtD7+tsF74/zG24qvEBB/6kEMpmSTnlGglmPiFlB8gHooa+lnVlKycvVwHBd2PUd7eQGbNkt1G4JwWRMB2CCPzMjSa6z+piaGQ4J1JLpaxFdI/G4Lze9Z0DYk96NJxoCG7wey6UOry7alEZS7Yv1Tpyio89TewFZRDhMYIr7AAYWzYQ5Y6iEG5fx803LEzXTQAAUqSxRi3tpuF1FehqoGRf0G/AxBnwFT1cXiSbmFpSq97DvfUJMp84hLoel0u6PpquwlB0fOebkXmQgM7sMpZXBXGO35r+FYjDUnUcNbMUS4FvRXqnVuPoODGum4HLBeQMiSXfgNbFNUKdKhdvCSXJPS3yvjpC8Q1aAdYT4bfnV3PhbreX+rVLHvSCyJhHSqDNYsYVzHHjDNqefewa8rqX94Ka843nEMspdHvu1owZBKrN321qpY1X3uRfwcXD+Ti3+zQvns8Z0PI06oyiZsXEFmLIF20FwhCdJGQL/kWDMESl0XMxC6w+js6zYHyH3BSei2qgu1VdXFUGm/YBmub82+xAa6ROD8vwZ1+5MwCmw8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(451199024)(1800799009)(186009)(82310400011)(46966006)(36840700001)(40470700004)(110136005)(54906003)(6666004)(70586007)(70206006)(40480700001)(7696005)(41300700001)(316002)(478600001)(8676002)(4326008)(2616005)(66899024)(1076003)(8936002)(40460700003)(5660300002)(16526019)(26005)(47076005)(36756003)(921005)(356005)(36860700001)(82740400003)(81166007)(336012)(426003)(2906002)(7416002)(86362001)(83380400001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:05.4699 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9ce3266-f3d1-4ed5-5736-08dbb5dcbc0d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017096.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5240 From: Xenia Ragiadakou When the memory region has a different life-cycle from that of her parent, could be automatically released, once has been unparent and once all of her references have gone away, via the object's free callback. However, currently, references to the memory region are held by its owner without first incrementing the memory region object's reference count. As a result, the automatic deallocation of the object, not taking into account those references, results in use-after-free memory corruption. This patch increases the reference count of an owned memory region object on each memory_region_ref() and decreases it on each memory_region_unref(). Signed-off-by: Xenia Ragiadakou Signed-off-by: Huang Rui --- V4 -> V5: - ref/unref only owned memory regions (Akihiko) softmmu/memory.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/softmmu/memory.c b/softmmu/memory.c index 7d9494ce70..15e1699750 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1800,6 +1800,9 @@ void memory_region_ref(MemoryRegion *mr) /* MMIO callbacks most likely will access data that belongs * to the owner, hence the need to ref/unref the owner whenever * the memory region is in use. + * Likewise, the owner keeps references to the memory region, + * hence the need to ref/unref the memory region object to prevent + * its automatic deallocation while still referenced by its owner. * * The memory region is a child of its owner. As long as the * owner doesn't call unparent itself on the memory region, @@ -1808,6 +1811,7 @@ void memory_region_ref(MemoryRegion *mr) * we do not ref/unref them because it slows down DMA sensibly. */ if (mr && mr->owner) { + object_ref(OBJECT(mr)); object_ref(mr->owner); } } @@ -1816,6 +1820,7 @@ void memory_region_unref(MemoryRegion *mr) { if (mr && mr->owner) { object_unref(mr->owner); + object_unref(OBJECT(mr)); } } From patchwork Fri Sep 15 11:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 596FCEE6459 for ; Fri, 15 Sep 2023 11:18:25 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.603059.939972 (Exim 4.92) (envelope-from ) id 1qh6px-0002jK-Ln; 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Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 08/13] virtio-gpu: Don't require udmabuf when blobs and virgl are enabled Date: Fri, 15 Sep 2023 19:11:25 +0800 Message-ID: <20230915111130.24064-9-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|CH3PR12MB8658:EE_ X-MS-Office365-Filtering-Correlation-Id: 8be00e1c-b91c-4655-1b7f-08dbb5dcbf9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rQ668DS+d2z/m8khygL8WzMnGRx/euIBph+tfKQbCIIF0JRjzq1ITu4MWToO2K8yA3Z6URhJnvvt+cCNJSa/ZhAkYX5aYK6367h/+jZ5d31xs2ulgdoNkaON7jpxB5iPece3QX6AYjsYqbx9ted6+VAF4zwS74HHUdXB8nQHvv9Qctds7of0PFzIPfpYFhOsQ7B44TZsKxkGd8IgyUwOvZtUZC196i8yg1Zw5y5+sRq9Glx8DBwRADMoynZR4AvCubH2Gc2UV8ea7lSCoJBvaab6ubsKGyVJb+8/VH9d7qaXwMFhynWQuEQr7jasz4KFY4Kj7zTTO4QgHtGyjtJcLq0/AtdbdQDStXs3zxPXWE/Bp2TwqbuuhkBMuIKH8MfCDdYSvdbO+yDCXwv8E/5W8ngJpiXUzPMbraVuspXOpcLxhzgBYHZ5/iQN6qRGqzkHJxmNb2Nv+TwhaomeqzQn7RRloCTYXeV9ojw0yv0KPzJAYf8XnqCtI8PAaWeeygrPD4YaePorHF7Xm72C66TvCa3pyCKixLBD36K5IjM0ke49BflWIt/bv36x9ChvmWCO2BCCL0oRnHAVuWTRQM1rds8ZS8ivQ55gVogBNn/UplJG1A/SOGkkQ6ZiyItzdhftkBK5tLVcz8B9/+Zrcn30TTtL6PLhGmNHbh71oDw5tV9twMQNmYJz0mUo6VftudtAUzBzwnIw+4Ip0TSoT3yX1k2KoOSRay+9YZsVqcXy1N6ft/aMi5WYFoXPhePNDe45jv4RjzvHne/055/MSRb46CBk5rSuFQ3+snaF+TwzuEM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(39860400002)(376002)(136003)(451199024)(1800799009)(186009)(82310400011)(36840700001)(46966006)(40470700004)(8936002)(4326008)(8676002)(16526019)(26005)(83380400001)(5660300002)(1076003)(2616005)(336012)(47076005)(40480700001)(36860700001)(426003)(2906002)(40460700003)(7416002)(7696005)(41300700001)(70206006)(6666004)(70586007)(54906003)(478600001)(316002)(921005)(86362001)(356005)(110136005)(82740400003)(81166007)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:11.4674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8be00e1c-b91c-4655-1b7f-08dbb5dcbf9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8658 From: Dmitry Osipenko The udmabuf usage is mandatory when virgl is disabled and blobs feature enabled in the Qemu machine configuration. If virgl and blobs are enabled, then udmabuf requirement is optional. Since udmabuf isn't widely supported by a popular Linux distros today, let's relax the udmabuf requirement for blobs=on,virgl=on. Now, a full-featured virtio-gpu acceleration is available to Qemu users without a need to have udmabuf available in the system. Reviewed-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Huang Rui --- hw/display/virtio-gpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index a66cbd9930..5b7a7eab4f 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1361,7 +1361,8 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) VirtIOGPU *g = VIRTIO_GPU(qdev); if (virtio_gpu_blob_enabled(g->parent_obj.conf)) { - if (!virtio_gpu_have_udmabuf()) { + if (!virtio_gpu_virgl_enabled(g->parent_obj.conf) && + !virtio_gpu_have_udmabuf()) { error_setg(errp, "cannot enable blob resources without udmabuf"); return; } From patchwork Fri Sep 15 11:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7625CEE6457 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 09/13] virtio-gpu: Handle resource blob commands Date: Fri, 15 Sep 2023 19:11:26 +0800 Message-ID: <20230915111130.24064-10-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|IA1PR12MB6042:EE_ X-MS-Office365-Filtering-Correlation-Id: 0300cffa-5fff-4d28-2bae-08dbb5dcc359 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v7qdDHk5L27yREFo/7Dk/agbSv41FuHTXBO4Bc0YctxexUJ6DL/lUo8Mom9czBoQDOIBORzUXAnNDmETHqepZsMRwtiFu3/fJwwGOoPW/kgkO7NsUPi2D9iuelRtDhFjCfnx70AZ0zVPGYZRoPEFcKtXONXQ1/MWHIRFDQQSpzon4fiiDiiyZzUEq9cwaXFbd6u1tX9UpEiB323WMmltADNm/dH8w2peeanCLdVNl1NTjN5ccopmkyY71u9dBbtrDMVcvjtcpoHAmdPuSWxxgHmZVMHo21YhzsOwyZTONRvqSSZK8GGkhEsXSDlCvs+rQjjqCanMu8abefM7JPLGkTKMpXKiaAJV7vc9BjyVnfc0mPxSkegIH0NRUeNd5qEYzuOsxsBD4GdimcHMkFAvbrqP0avjvFmiFMbYPoD46wG34qsJjjSALOkR2W4tgohqEi8R3pufzzZ3elMDT/z+khqQ3lJZWcvFRE/BmCoK+3TuqRALYOTI231HzutUJBNWqglLguCCp74dliRBzJzpb4aa0kfAtSXFC5eQyoizSlZj/nZK4RRYI1V8SaWGKaoVqbj8hXVhNeyCiD+c5dvUaVLVV4dI/HgINDI7PlVwpe4FsdfbsC5biVdI8jk9w/fsoA2XUjjqcuGX/DvG4uTjfQrnStYbtgVNwAc3wtb4vPu4u878OLonoCWytBlS/s+dyl1BqZH9U9v6DMY77m1eMh/EVSFEg9nU+ljd6yLQQzxAiwk2Xjnbm6rIepCz+YL5qchf2DCdvi3h6y70CZriSYMS8Zp3gxgrpruJ2tlTFIo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(451199024)(186009)(1800799009)(82310400011)(46966006)(40470700004)(36840700001)(40480700001)(83380400001)(2906002)(5660300002)(36756003)(7416002)(8936002)(86362001)(82740400003)(356005)(4326008)(40460700003)(921005)(8676002)(81166007)(316002)(6666004)(54906003)(47076005)(41300700001)(36860700001)(1076003)(70586007)(110136005)(16526019)(7696005)(26005)(70206006)(478600001)(426003)(2616005)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:17.7109 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0300cffa-5fff-4d28-2bae-08dbb5dcc359 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6042 From: Antonio Caggiano Support BLOB resources creation, mapping and unmapping by calling the new stable virglrenderer 0.10 interface. Only enabled when available and via the blob config. E.g. -device virtio-vga-gl,blob=true Signed-off-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Xenia Ragiadakou Signed-off-by: Huang Rui --- V4 -> V5: - Use memory_region_init_ram_ptr() instead of memory_region_init_ram_device_ptr() (Akihiko) hw/display/virtio-gpu-virgl.c | 213 +++++++++++++++++++++++++++++++++ hw/display/virtio-gpu.c | 4 +- include/hw/virtio/virtio-gpu.h | 5 + meson.build | 4 + 4 files changed, 225 insertions(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 312953ec16..563a6f2f58 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -17,6 +17,7 @@ #include "trace.h" #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-gpu.h" +#include "hw/virtio/virtio-gpu-bswap.h" #include "ui/egl-helpers.h" @@ -78,9 +79,24 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g, virgl_renderer_resource_create(&args, NULL, 0); } +static void virgl_resource_destroy(VirtIOGPU *g, + struct virtio_gpu_simple_resource *res) +{ + if (!res) + return; + + QTAILQ_REMOVE(&g->reslist, res, next); + + virtio_gpu_cleanup_mapping_iov(g, res->iov, res->iov_cnt); + g_free(res->addrs); + + g_free(res); +} + static void virgl_cmd_resource_unref(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { + struct virtio_gpu_simple_resource *res; struct virtio_gpu_resource_unref unref; struct iovec *res_iovs = NULL; int num_iovs = 0; @@ -88,13 +104,22 @@ static void virgl_cmd_resource_unref(VirtIOGPU *g, VIRTIO_GPU_FILL_CMD(unref); trace_virtio_gpu_cmd_res_unref(unref.resource_id); + res = virtio_gpu_find_resource(g, unref.resource_id); + virgl_renderer_resource_detach_iov(unref.resource_id, &res_iovs, &num_iovs); if (res_iovs != NULL && num_iovs != 0) { virtio_gpu_cleanup_mapping_iov(g, res_iovs, num_iovs); + if (res) { + res->iov = NULL; + res->iov_cnt = 0; + } } + virgl_renderer_resource_unref(unref.resource_id); + + virgl_resource_destroy(g, res); } static void virgl_cmd_context_create(VirtIOGPU *g, @@ -426,6 +451,183 @@ static void virgl_cmd_get_capset(VirtIOGPU *g, g_free(resp); } +#ifdef HAVE_VIRGL_RESOURCE_BLOB + +static void virgl_cmd_resource_create_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_create_blob cblob; + struct virgl_renderer_resource_create_blob_args virgl_args = { 0 }; + int ret; + + VIRTIO_GPU_FILL_CMD(cblob); + virtio_gpu_create_blob_bswap(&cblob); + trace_virtio_gpu_cmd_res_create_blob(cblob.resource_id, cblob.size); + + if (cblob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + res = virtio_gpu_find_resource(g, cblob.resource_id); + if (res) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already exists %d\n", + __func__, cblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + res = g_new0(struct virtio_gpu_simple_resource, 1); + if (!res) { + cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + + res->resource_id = cblob.resource_id; + res->blob_size = cblob.size; + + if (cblob.blob_mem != VIRTIO_GPU_BLOB_MEM_HOST3D) { + ret = virtio_gpu_create_mapping_iov(g, cblob.nr_entries, sizeof(cblob), + cmd, &res->addrs, &res->iov, + &res->iov_cnt); + if (!ret) { + g_free(res); + cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; + return; + } + } + + QTAILQ_INSERT_HEAD(&g->reslist, res, next); + + virgl_args.res_handle = cblob.resource_id; + virgl_args.ctx_id = cblob.hdr.ctx_id; + virgl_args.blob_mem = cblob.blob_mem; + virgl_args.blob_id = cblob.blob_id; + virgl_args.blob_flags = cblob.blob_flags; + virgl_args.size = cblob.size; + virgl_args.iovecs = res->iov; + virgl_args.num_iovs = res->iov_cnt; + + ret = virgl_renderer_resource_create_blob(&virgl_args); + if (ret) { + virgl_resource_destroy(g, res); + qemu_log_mask(LOG_GUEST_ERROR, "%s: virgl blob create error: %s\n", + __func__, strerror(-ret)); + cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; + } +} + +static void virgl_cmd_resource_map_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_map_blob mblob; + int ret; + void *data; + uint64_t size; + struct virtio_gpu_resp_map_info resp; + VirtIOGPUBase *b = VIRTIO_GPU_BASE(g); + + VIRTIO_GPU_FILL_CMD(mblob); + virtio_gpu_map_blob_bswap(&mblob); + + if (mblob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + res = virtio_gpu_find_resource(g, mblob.resource_id); + if (!res) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource does not exist %d\n", + __func__, mblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + if (res->region) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already mapped %d\n", + __func__, mblob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + ret = virgl_renderer_resource_map(res->resource_id, &data, &size); + if (ret) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource map error: %s\n", + __func__, strerror(-ret)); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + res->region = g_new0(MemoryRegion, 1); + if (!res->region) { + virgl_renderer_resource_unmap(res->resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + memory_region_init_ram_ptr(res->region, OBJECT(g), NULL, size, data); + OBJECT(res->region)->free = g_free; + memory_region_add_subregion(&b->hostmem, mblob.offset, res->region); + memory_region_set_enabled(res->region, true); + + memset(&resp, 0, sizeof(resp)); + resp.hdr.type = VIRTIO_GPU_RESP_OK_MAP_INFO; + virgl_renderer_resource_get_map_info(mblob.resource_id, &resp.map_info); + virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); +} + +static int virtio_gpu_virgl_resource_unmap(VirtIOGPU *g, + struct virtio_gpu_simple_resource + *res) +{ + VirtIOGPUBase *b = VIRTIO_GPU_BASE(g); + + if (!res) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource already unmapped %d\n", + __func__, res->resource_id); + return VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + } + + memory_region_set_enabled(res->region, false); + memory_region_del_subregion(&b->hostmem, res->region); + object_unparent(OBJECT(res->region)); + res->region = NULL; + + return virgl_renderer_resource_unmap(res->resource_id); +} + +static void virgl_cmd_resource_unmap_blob(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_unmap_blob ublob; + VIRTIO_GPU_FILL_CMD(ublob); + virtio_gpu_unmap_blob_bswap(&ublob); + + if (ublob.resource_id == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource id 0 is not allowed\n", + __func__); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + res = virtio_gpu_find_resource(g, ublob.resource_id); + if (!res) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: resource does not exist %d\n", + __func__, ublob.resource_id); + cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID; + return; + } + + virtio_gpu_virgl_resource_unmap(g, res); +} + +#endif /* HAVE_VIRGL_RESOURCE_BLOB */ + void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { @@ -492,6 +694,17 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_GET_EDID: virtio_gpu_get_edid(g, cmd); break; +#ifdef HAVE_VIRGL_RESOURCE_BLOB + case VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB: + virgl_cmd_resource_create_blob(g, cmd); + break; + case VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB: + virgl_cmd_resource_map_blob(g, cmd); + break; + case VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB: + virgl_cmd_resource_unmap_blob(g, cmd); + break; +#endif /* HAVE_VIRGL_RESOURCE_BLOB */ default: cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; break; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 5b7a7eab4f..cc4c1f81bb 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1367,10 +1367,12 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) return; } +#ifndef HAVE_VIRGL_RESOURCE_BLOB if (virtio_gpu_virgl_enabled(g->parent_obj.conf)) { - error_setg(errp, "blobs and virgl are not compatible (yet)"); + error_setg(errp, "Linked virglrenderer does not support blob resources"); return; } +#endif } if (!virtio_gpu_base_device_realize(qdev, diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index 55973e112f..b9adc28071 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -58,6 +58,11 @@ struct virtio_gpu_simple_resource { int dmabuf_fd; uint8_t *remapped; +#ifdef HAVE_VIRGL_RESOURCE_BLOB + /* only blob resource needs this region to be mapped as guest mmio */ + MemoryRegion *region; +#endif + QTAILQ_ENTRY(virtio_gpu_simple_resource) next; }; diff --git a/meson.build b/meson.build index ff20d3c249..f7b744ab82 100644 --- a/meson.build +++ b/meson.build @@ -1072,6 +1072,10 @@ if not get_option('virglrenderer').auto() or have_system or have_vhost_user_gpu cc.has_function('virgl_renderer_context_create_with_flags', prefix: '#include ', dependencies: virgl)) + config_host_data.set('HAVE_VIRGL_RESOURCE_BLOB', + cc.has_function('virgl_renderer_resource_create_blob', + prefix: '#include ', + dependencies: virgl)) endif blkio = not_found if not get_option('blkio').auto() or have_block From patchwork Fri Sep 15 11:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Rui X-Patchwork-Id: 13386931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6926BEE6457 for ; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 10/13] virtio-gpu: Resource UUID Date: Fri, 15 Sep 2023 19:11:27 +0800 Message-ID: <20230915111130.24064-11-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|LV8PR12MB9406:EE_ X-MS-Office365-Filtering-Correlation-Id: 415fb7bd-8e7f-4477-9200-08dbb5dcc70e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TV7L0dSpc9+RG+zqytEuk2ScpZm3DXBUQonJ2iaXkpWuhczfNspy7BsdSUdRI4nnrMEPue6Xp3XSSG9eY1aL47xF2ZaEF/J1UhbxnLHDa+wx8cKqiYqs0521J50AkqQ3Dp/+OyDsEpkOLCeviCMBJJHk3Pj1ONYuv98//7F+EDRpGmdrsns9E4Onoa11GfAIKm/B9AACjN0UoFapPhDTSxor02GoPxNJhHzwm4oYcXFrEi8s0ikNunK2eGYlBbAFZIU94Hr2lGc14stTtbqLXGsjQRihBY92WJy3GFOgfh0zhiUuKN4nLUHv5baSoIC3iFoSvCvZ6gRyvMW06Rv4/smoGHirI8d7UkgokS8H0s8lAgtsmiPQuYFzkWKmP+hxCGYocN11swQkQpjrGvZSmcGLKqnO482Tf8MeyNM4Qvx9N71N0myB3aFY/mqbZj0jQ7Q5e8fsToBE8GE7W/xmPEvjJ3Qx2yzDYQd7ISGAX/VEY03HYZTc1PTFrnKc0t/guVUwuRxV1qXfGB2NVLJ/72yX4qlH6DCuzWgSj9fXxkdVIsrkkGJU9iVH3k8+LxC28JLxQAS7kE+Kh5XTK3XQcGOxhKv1pJvUrxat3QekymlfGj6sPSq/Vnh30b8aANrBrxILU1LoHssZOLoVCjQP+OmW/VnxHEMts/HoBEOEtLlSzrNHi/GgRKrUau9wefLUbwF6vxf1c+xwKlDFntSZB5kBz8kveMNAec8LmbiqBnuOxNWE9pVg0u90Qe1y+jnTAYaBnv3lOQu659nGNkBIZF6hBi4ddV8qmiqdxkyb+eY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(396003)(376002)(186009)(451199024)(82310400011)(1800799009)(40470700004)(36840700001)(46966006)(83380400001)(70206006)(2906002)(6666004)(36756003)(7416002)(4326008)(54906003)(70586007)(8676002)(8936002)(40460700003)(41300700001)(5660300002)(86362001)(47076005)(81166007)(110136005)(2616005)(356005)(921005)(478600001)(7696005)(336012)(36860700001)(316002)(426003)(26005)(16526019)(82740400003)(1076003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:23.9329 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 415fb7bd-8e7f-4477-9200-08dbb5dcc70e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9406 From: Antonio Caggiano Enable resource UUID feature and implement command resource assign UUID. This is done by introducing a hash table to map resource IDs to their UUIDs. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Add virtio migration handling for uuid (Akihiko) - Adjust sequence to allocate gpu resource before virglrender resource creation (Akihiko) - Clean up (Akihiko) hw/display/trace-events | 1 + hw/display/virtio-gpu-base.c | 2 ++ hw/display/virtio-gpu-virgl.c | 21 ++++++++++++ hw/display/virtio-gpu.c | 58 ++++++++++++++++++++++++++++++++++ include/hw/virtio/virtio-gpu.h | 6 ++++ 5 files changed, 88 insertions(+) diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca15..54d6894c59 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -41,6 +41,7 @@ virtio_gpu_cmd_res_create_blob(uint32_t res, uint64_t size) "res 0x%x, size %" P virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x" +virtio_gpu_cmd_res_assign_uuid(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x" virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x" diff --git a/hw/display/virtio-gpu-base.c b/hw/display/virtio-gpu-base.c index 4f2b0ba1f3..f44388715c 100644 --- a/hw/display/virtio-gpu-base.c +++ b/hw/display/virtio-gpu-base.c @@ -236,6 +236,8 @@ virtio_gpu_base_get_features(VirtIODevice *vdev, uint64_t features, features |= (1 << VIRTIO_GPU_F_CONTEXT_INIT); } + features |= (1 << VIRTIO_GPU_F_RESOURCE_UUID); + return features; } diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 563a6f2f58..8a017dbeb4 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -36,11 +36,20 @@ static void virgl_cmd_create_resource_2d(VirtIOGPU *g, { struct virtio_gpu_resource_create_2d c2d; struct virgl_renderer_resource_create_args args; + struct virtio_gpu_simple_resource *res; VIRTIO_GPU_FILL_CMD(c2d); trace_virtio_gpu_cmd_res_create_2d(c2d.resource_id, c2d.format, c2d.width, c2d.height); + res = g_new0(struct virtio_gpu_simple_resource, 1); + if (!res) { + cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + res->resource_id = c2d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, res, next); + args.handle = c2d.resource_id; args.target = 2; args.format = c2d.format; @@ -60,11 +69,20 @@ static void virgl_cmd_create_resource_3d(VirtIOGPU *g, { struct virtio_gpu_resource_create_3d c3d; struct virgl_renderer_resource_create_args args; + struct virtio_gpu_simple_resource *res; VIRTIO_GPU_FILL_CMD(c3d); trace_virtio_gpu_cmd_res_create_3d(c3d.resource_id, c3d.format, c3d.width, c3d.height, c3d.depth); + res = g_new0(struct virtio_gpu_simple_resource, 1); + if (!res) { + cmd->error = VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY; + return; + } + res->resource_id = c3d.resource_id; + QTAILQ_INSERT_HEAD(&g->reslist, res, next); + args.handle = c3d.resource_id; args.target = c3d.target; args.format = c3d.format; @@ -682,6 +700,9 @@ void virtio_gpu_virgl_process_cmd(VirtIOGPU *g, /* TODO add security */ virgl_cmd_ctx_detach_resource(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; case VIRTIO_GPU_CMD_GET_CAPSET_INFO: virgl_cmd_get_capset_info(g, cmd); break; diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index cc4c1f81bb..44414c1c5e 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -966,6 +966,38 @@ virtio_gpu_resource_detach_backing(VirtIOGPU *g, virtio_gpu_cleanup_mapping(g, res); } +void virtio_gpu_resource_assign_uuid(VirtIOGPU *g, + struct virtio_gpu_ctrl_command *cmd) +{ + struct virtio_gpu_simple_resource *res; + struct virtio_gpu_resource_assign_uuid assign; + struct virtio_gpu_resp_resource_uuid resp; + QemuUUID *uuid; + + VIRTIO_GPU_FILL_CMD(assign); + virtio_gpu_bswap_32(&assign, sizeof(assign)); + trace_virtio_gpu_cmd_res_assign_uuid(assign.resource_id); + + res = virtio_gpu_find_check_resource(g, assign.resource_id, false, __func__, &cmd->error); + if (!res) { + return; + } + + memset(&resp, 0, sizeof(resp)); + resp.hdr.type = VIRTIO_GPU_RESP_OK_RESOURCE_UUID; + + uuid = g_hash_table_lookup(g->resource_uuids, GUINT_TO_POINTER(assign.resource_id)); + if (!uuid) { + uuid = g_new(QemuUUID, 1); + qemu_uuid_generate(uuid); + g_hash_table_insert(g->resource_uuids, GUINT_TO_POINTER(assign.resource_id), uuid); + res->has_uuid = true; + } + + memcpy(resp.uuid, uuid, sizeof(QemuUUID)); + virtio_gpu_ctrl_response(g, cmd, &resp.hdr, sizeof(resp)); +} + void virtio_gpu_simple_process_cmd(VirtIOGPU *g, struct virtio_gpu_ctrl_command *cmd) { @@ -1014,6 +1046,9 @@ void virtio_gpu_simple_process_cmd(VirtIOGPU *g, case VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING: virtio_gpu_resource_detach_backing(g, cmd); break; + case VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID: + virtio_gpu_resource_assign_uuid(g, cmd); + break; default: cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC; break; @@ -1208,6 +1243,7 @@ static int virtio_gpu_save(QEMUFile *f, void *opaque, size_t size, VirtIOGPU *g = opaque; struct virtio_gpu_simple_resource *res; int i; + QemuUUID *uuid; /* in 2d mode we should never find unprocessed commands here */ assert(QTAILQ_EMPTY(&g->cmdq)); @@ -1224,9 +1260,17 @@ static int virtio_gpu_save(QEMUFile *f, void *opaque, size_t size, } qemu_put_buffer(f, (void *)pixman_image_get_data(res->image), pixman_image_get_stride(res->image) * res->height); + + qemu_put_byte(f, res->has_uuid); + if (res->has_uuid) { + uuid = g_hash_table_lookup(g->resource_uuids, GUINT_TO_POINTER(res->resource_id)); + qemu_put_buffer(f, (void *)uuid, sizeof(QemuUUID)); + } } qemu_put_be32(f, 0); /* end of list */ + g_hash_table_destroy(g->resource_uuids); + return vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL); } @@ -1239,9 +1283,12 @@ static int virtio_gpu_load(QEMUFile *f, void *opaque, size_t size, uint32_t resource_id, pformat; void *bits = NULL; int i; + QemuUUID *uuid = NULL; g->hostmem = 0; + g->resource_uuids = g_hash_table_new_full(NULL, NULL, NULL, g_free); + resource_id = qemu_get_be32(f); while (resource_id != 0) { res = virtio_gpu_find_resource(g, resource_id); @@ -1292,6 +1339,12 @@ static int virtio_gpu_load(QEMUFile *f, void *opaque, size_t size, qemu_get_buffer(f, (void *)pixman_image_get_data(res->image), pixman_image_get_stride(res->image) * res->height); + res->has_uuid = qemu_get_byte(f); + if (res->has_uuid) { + qemu_get_buffer(f, (void *)uuid, sizeof(QemuUUID)); + g_hash_table_insert(g->resource_uuids, GUINT_TO_POINTER(res->resource_id), uuid); + } + /* restore mapping */ for (i = 0; i < res->iov_cnt; i++) { hwaddr len = res->iov[i].iov_len; @@ -1393,12 +1446,15 @@ void virtio_gpu_device_realize(DeviceState *qdev, Error **errp) QTAILQ_INIT(&g->reslist); QTAILQ_INIT(&g->cmdq); QTAILQ_INIT(&g->fenceq); + + g->resource_uuids = g_hash_table_new_full(NULL, NULL, NULL, g_free); } static void virtio_gpu_device_unrealize(DeviceState *qdev) { VirtIOGPU *g = VIRTIO_GPU(qdev); + g_hash_table_destroy(g->resource_uuids); g_clear_pointer(&g->ctrl_bh, qemu_bh_delete); g_clear_pointer(&g->cursor_bh, qemu_bh_delete); g_clear_pointer(&g->reset_bh, qemu_bh_delete); @@ -1452,6 +1508,8 @@ void virtio_gpu_reset(VirtIODevice *vdev) g_free(cmd); } + g_hash_table_remove_all(g->resource_uuids); + virtio_gpu_base_reset(VIRTIO_GPU_BASE(vdev)); } diff --git a/include/hw/virtio/virtio-gpu.h b/include/hw/virtio/virtio-gpu.h index b9adc28071..67b39fccec 100644 --- a/include/hw/virtio/virtio-gpu.h +++ b/include/hw/virtio/virtio-gpu.h @@ -63,6 +63,8 @@ struct virtio_gpu_simple_resource { MemoryRegion *region; #endif + bool has_uuid; + QTAILQ_ENTRY(virtio_gpu_simple_resource) next; }; @@ -208,6 +210,8 @@ struct VirtIOGPU { QTAILQ_HEAD(, VGPUDMABuf) bufs; VGPUDMABuf *primary[VIRTIO_GPU_MAX_SCANOUTS]; } dmabuf; + + GHashTable *resource_uuids; }; struct VirtIOGPUClass { @@ -285,6 +289,8 @@ void virtio_gpu_cleanup_mapping_iov(VirtIOGPU *g, struct iovec *iov, uint32_t count); void virtio_gpu_cleanup_mapping(VirtIOGPU *g, struct virtio_gpu_simple_resource *res); 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Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 11/13] virtio-gpu: Support Venus capset Date: Fri, 15 Sep 2023 19:11:28 +0800 Message-ID: <20230915111130.24064-12-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709A:EE_|DM4PR12MB6397:EE_ X-MS-Office365-Filtering-Correlation-Id: 5039c86c-aa90-42dc-6932-08dbb5dccad2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Np+ABieQKRZO+JP9XsbX9lGtb0zKljyWnPn2FzRMyuJdfXU0eBaiukM5QolIazTrD84oTld5MzeUpPkFz/XU0/zNKkqsh4CzFK4f5Im1pD0qzM2PBJM5WfXZ0svTga/1cyLfvPuk3HfwUTdvw8JZ6lq5MyQorp9CCcHyvtPMhzadgKOkEGHtBEouX+wLNJrfiiMpQ+5Y1qevxJ3Yvsfmzrjh1kLmYf/Q3Nd9VnLFfKUhOF5n1pZi6AKTaAvgOkMuDoqdEmxaRVkhHq84FbB+OyWxXGN7x3zQ3F2ArsNlkTtXBNyumsOceQyPRO/YBiycULgm4xTkJerHFlJ8wKWmj2L5K3x/PZOJryI8SNwAIDCAnHJBHdUY99lNRkQ/kxrQvpysJOvvOAv2M8UvzueEsaTSGgGGQWbu78+Fm2w40vjTm7djDHLIdkLl2pp2cQKNhaj+9WeVi8eF3Wdj8x7CJkXY/4hoC5pzegRZUciB3nGz7ZWVTREHr6ysewCGLCTLnjawl3GtgFtgnWq2t7Ek3k8unlfa/dket8kJQK8iATy4QVNqM+z+wFwwSB/p+RHDxyId/6N0abEKdfncadFB+8V4MWn7iQfUtq0nEVgUSqF3GhmE94qZ/Q5JDeUKLUoxfWvIijGZXd3iddVr+m7pvOiCR/c+yYxsJ4Yr+gU8xNZBCftqrGvIZ5TG58qYRmmeHfvQpFEVTM9J5v6HdNPhBEV4RNmMGWC4YmyQ3qq6V+vXnbzRG2kb3U12B4zqcVlTE3Dlq5gJxP935sLWTFJKkg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199024)(1800799009)(186009)(82310400011)(46966006)(40470700004)(36840700001)(40460700003)(36756003)(86362001)(40480700001)(5660300002)(316002)(7696005)(26005)(966005)(70206006)(8676002)(426003)(70586007)(336012)(110136005)(2616005)(8936002)(54906003)(921005)(41300700001)(4326008)(2906002)(16526019)(47076005)(81166007)(36860700001)(478600001)(356005)(1076003)(82740400003)(83380400001)(7416002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:30.2495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5039c86c-aa90-42dc-6932-08dbb5dccad2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6397 From: Antonio Caggiano Add support for the Venus capset, which enables Vulkan support through the Venus Vulkan driver for virtio-gpu. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Send kernel patch to define VIRTIO_GPU_CAPSET_VENUS and will use another patch to sync up linux headers. (Akihiko) - https://lore.kernel.org/lkml/20230915105918.3763061-1-ray.huang@amd.com/ hw/display/virtio-gpu-virgl.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 8a017dbeb4..7f95490e90 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -437,6 +437,11 @@ static void virgl_cmd_get_capset_info(VirtIOGPU *g, virgl_renderer_get_cap_set(resp.capset_id, &resp.capset_max_version, &resp.capset_max_size); + } else if (info.capset_index == 2) { + resp.capset_id = VIRTIO_GPU_CAPSET_VENUS; + virgl_renderer_get_cap_set(resp.capset_id, + &resp.capset_max_version, + &resp.capset_max_size); } else { resp.capset_max_version = 0; resp.capset_max_size = 0; @@ -901,10 +906,18 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) int virtio_gpu_virgl_get_num_capsets(VirtIOGPU *g) { - uint32_t capset2_max_ver, capset2_max_size; + uint32_t capset2_max_ver, capset2_max_size, num_capsets; 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mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=redhat.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yCctA/d+0Gb5My8OmDqUHYDaathKDBLi1NA3E1Lrd/M=; b=0wvapmN22PNedA7ekcUvo+6kBbWXNKRMMOiVlbMW8/aLLSumEcZSn/rWJUnYF/4z1YEwK2wmwBL7rj2zG0vIMoDd1m3YV9aGIwMbJ+Sepgg7xh7bmIQ+VAGlPU61fvoOAsC5aDzbAdUA7W+XXShOKHJo+YlQAwQDmvYFXtvfzHg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Antonio Caggiano , Huang Rui Subject: [QEMU PATCH v5 12/13] virtio-gpu: Initialize Venus Date: Fri, 15 Sep 2023 19:11:29 +0800 Message-ID: <20230915111130.24064-13-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017097:EE_|BL1PR12MB5362:EE_ X-MS-Office365-Filtering-Correlation-Id: ab3bcf85-b9a0-4d55-326f-08dbb5dcce60 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bxWOhEETmGAmwcLPrzGe/Y27jc3iadxvHmWlqljMAJlOKoSk811V0f+FhFIPnY+BH+xI+xZzU2h7vMaT5UUTB0PhGBzw8RngwmUTJUpgT1vXeAf+VX1lZnR18ChGrgjDgisoe2lkbMEjx+0z9ggPwlQdkNUHj6+PHQglN5zQyWBGAt1LK5nBwsw9Sy/MJqmuv+L2HsHshRTqfb4enocayIQcyjgpdLQHPchVZjhGvjBOe2bCd1lJdmACd+nf3XWHEE/9Sew2d+P2ljIvZ4i9/rVbhjzzgysmRHLY9TIcer+GpPwqiAZX6duLlEY2dX0MgIaCcbleHWm2pMmLvG5vQ2aB8e2PuO4bIo/jwKR3uW4FRxvNzNnOKZoLQdNDqpoK7n3Dvd0esHjsxgEDbnNY9pvJ0Ehf+cLd+3ri39Fqi0lZxS+9jcj1kTXRvvh/1XdxXMI0Fd73uRN2zNQfk/beuJ0aII8/ccISeRcpXUFoA7EPBzUe7Ou/6gxSrWf1tefcAGjx74u9wkBeMRsdDK00x+Vg6L4VQMD532mHO13pNpNlzGSpq7fmvCIiO2VcClm+jOo5VGPfkBBpyGETt9U+55McBC39Y5xl3DJVT4WkxwDi1iWyF8+SAao4LLkziWxxGbWJL6LIXlvAUbMUIcFGR1BQINd3oXCkVmNJOUwLSE0saDkOMazbFlIaMrfXEs0bdZPLEPe4eQgmM4AMPuQXXYpwVwGOirEIPaukeg1XAmOdOTJIRO4TmVAL6fXS9vAVW4pklcgDcEBgCspnIBYwEtCFAPa62+jskw7cbkIiLAU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(396003)(346002)(376002)(82310400011)(186009)(1800799009)(451199024)(36840700001)(40470700004)(46966006)(5660300002)(8936002)(26005)(16526019)(8676002)(1076003)(4326008)(40460700003)(2616005)(2906002)(83380400001)(7416002)(86362001)(47076005)(81166007)(921005)(356005)(82740400003)(36860700001)(36756003)(426003)(336012)(40480700001)(7696005)(110136005)(54906003)(70586007)(70206006)(478600001)(41300700001)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:36.2119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ab3bcf85-b9a0-4d55-326f-08dbb5dcce60 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017097.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5362 From: Antonio Caggiano Request Venus when initializing VirGL. Signed-off-by: Antonio Caggiano Signed-off-by: Huang Rui --- V4 -> V5: - Add meson check to make sure unstable APIs defined from 0.9.0. (Antonio) hw/display/virtio-gpu-virgl.c | 4 ++++ meson.build | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 7f95490e90..39c04d730c 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -887,6 +887,10 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) } #endif +#ifdef VIRGL_RENDERER_VENUS + flags |= VIRGL_RENDERER_VENUS; +#endif + ret = virgl_renderer_init(g, flags, &virtio_gpu_3d_cbs); if (ret != 0) { error_report("virgl could not be initialized: %d", ret); diff --git a/meson.build b/meson.build index f7b744ab82..e4004d05b1 100644 --- a/meson.build +++ b/meson.build @@ -1076,6 +1076,11 @@ if not get_option('virglrenderer').auto() or have_system or have_vhost_user_gpu cc.has_function('virgl_renderer_resource_create_blob', prefix: '#include ', dependencies: virgl)) + if virgl.version().version_compare('>= 0.9.0') and virgl.version().version_compare('< 1.0.0') + message('Enabling virglrenderer unstable APIs') + virgl = declare_dependency(compile_args: '-DVIRGL_RENDERER_UNSTABLE_APIS', + dependencies: virgl) + endif endif blkio = not_found if not get_option('blkio').auto() or have_block From patchwork Fri Sep 15 11:11:30 2023 Content-Type: text/plain; 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bh=doHo9C4Pm4Ui7n/4etAaiF8HheLBr5YOGc5k2SvIw1c=; b=D3PWJi7T/AJUYP96Gj1muvD/6xCuUnj2MEnB4x8OUf7WydYDbr/KN1V3b490Bxx36YJau32N4NYLRYzOWnXpCCYsmcGPIyK4y5648+meZI84baq+PFP9RxVBt5TIUCIDBC/G5o/VYWMjE/O53ChEJokWpZ22vD6brBY/K5LPbvg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Huang Rui To: Gerd Hoffmann , "Michael S . Tsirkin" , Akihiko Odaki , Stefano Stabellini , Anthony PERARD , "Antonio Caggiano" , "Dr . David Alan Gilbert" , Robert Beckett , "Dmitry Osipenko" , =?utf-8?q?Alex_Benn?= =?utf-8?q?=C3=A9e?= , CC: , Gurchetan Singh , Albert Esteve , , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Alyssa Ross , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xenia Ragiadakou , Pierre-Eric Pelloux-Prayer , "Honglei Huang" , Julia Zhang , "Chen Jiqian" , Huang Rui Subject: [QEMU PATCH v5 13/13] virtio-gpu: Enable virglrenderer render server flag for venus Date: Fri, 15 Sep 2023 19:11:30 +0800 Message-ID: <20230915111130.24064-14-ray.huang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915111130.24064-1-ray.huang@amd.com> References: <20230915111130.24064-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|BL1PR12MB5827:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c85e6bb-27ab-488e-994d-08dbb5dcd1de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /IjleQEDOaKMtBI3MXvY/fI4YUpE7kXeauzblPqd7AZnPMIjJM+QL6aC57xcn6AQZF0SlUkyvEZrhGDKGQUmTdDS6zsZA7hUwxKvhTlntp+ZC74S9GpSbuXMmihfGft2m3QkQZN5Yh+dJDgPRcjwasfg+Q26i4754kTweyM6EtfabuwpamwPNNj3lVoe8Zof32UzQ5DMpjZBjf3Xd0r7wvjferfPLiusx8iOdPQgxtkwvEAyFRZWhUebIAcjmF9V62707lXBIL9JPdtLSVZUfvJYbtVRsGMYQ9pZ0f5fchJCM+ACFVOLIHZbd5v9c+4TsaFaLqldsy+5CE1EDgSeEAZJEDU/whDfh6ILuPmwXYG3yM9FBifpIsgrhSu0L+ozRvdWdsAeTIv/+xA7r55mJZyQebttDzEu/Umre09XTf8F5nnuWQ07aymHDvmmObTR0x1FTOKv8h6XuURYMLgYh6FhMoZGKk+t9Fm1Tu3BtBAPfQWREZsKvS/acgH+YVcHTfzv4MP5pVQOP8MncUZrq+Nv8GRSeG3ytY+hr7nqISaykeorng/cR1lnkcuXCj2GQcBOaYyYjrBWKA1DbpQSvqSMANEZTzAD2/9lq380F8sQTCbzy4D+zC9JtTQ6U8cjRNAXQSArOKlgPXDC0vcJnRzEN6+V+CwqX/9GAOUfqwB8n3C3a59jRKQDE63/4y9698dYNEP826MRUq9CID9L4W7EdCyWhAqAgCwoXieCmetaQM4N9v/GBUGdbmSeOjAQKHHUPg9J3Ddj1nuSdPqZRsHpL65rS5/nEOEip1xkDQE= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(82310400011)(1800799009)(451199024)(186009)(36840700001)(40470700004)(46966006)(426003)(1076003)(2616005)(336012)(40480700001)(26005)(83380400001)(16526019)(40460700003)(82740400003)(86362001)(110136005)(7696005)(70586007)(921005)(478600001)(356005)(81166007)(8676002)(4744005)(7416002)(2906002)(8936002)(36756003)(5660300002)(4326008)(36860700001)(41300700001)(70206006)(54906003)(6666004)(316002)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2023 11:13:42.0734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c85e6bb-27ab-488e-994d-08dbb5dcd1de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5827 Venus in virglrenderer has required render server support. Signed-off-by: Huang Rui --- hw/display/virtio-gpu-virgl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c index 39c04d730c..65ffce85a8 100644 --- a/hw/display/virtio-gpu-virgl.c +++ b/hw/display/virtio-gpu-virgl.c @@ -888,7 +888,7 @@ int virtio_gpu_virgl_init(VirtIOGPU *g) #endif #ifdef VIRGL_RENDERER_VENUS - flags |= VIRGL_RENDERER_VENUS; + flags |= VIRGL_RENDERER_VENUS | VIRGL_RENDERER_RENDER_SERVER; #endif ret = virgl_renderer_init(g, flags, &virtio_gpu_3d_cbs);