From patchwork Mon Sep 18 07:31:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34B67CD13D2 for ; Mon, 18 Sep 2023 07:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240360AbjIRHo0 (ORCPT ); Mon, 18 Sep 2023 03:44:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240461AbjIRHoK (ORCPT ); Mon, 18 Sep 2023 03:44:10 -0400 X-Greylist: delayed 540 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Sep 2023 00:41:52 PDT Received: from mail-m121151.qiye.163.com (mail-m121151.qiye.163.com [115.236.121.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C791CF9; Mon, 18 Sep 2023 00:41:51 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=ZwXs1GBSjZwKqg5hCo8UmM8vhdPvEKScYskKbClAKbM69+rHkSipOVX1bZ5rwf04cZh5WM9QBIUraUuJpENVMO6HMsqvDQ3wYP8umDX2JY0yM5iymBOfd2KA5V0H2xHuRSM6OGCseOMObrN0tv30CZ9v/YchAXQTXa4hbRlND+M=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=FVjj8wFV8jwGPF8t4GJPuriYLO1LL7PtUtc22EoDAPI=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 0E5E1680587; Mon, 18 Sep 2023 15:31:53 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 1/8] clk: clk-fractional-divider: Export clk_fractional_divider_general_approximation API Date: Mon, 18 Sep 2023 15:31:44 +0800 Message-Id: <20230918073151.7660-2-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUgZGVYeH0JOTkgaQx0aGklVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa733efbe2eb5kusn0e5e1680587 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OjI6Mjo*Lj1NDUoPIg1CSUgC KQ0wFC9VSlVKTUJOS0lJSEpPS0tLVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUlPSE83Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module. Signed-off-by: Elaine Zhang --- drivers/clk/clk-fractional-divider.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 479297763e70..44bf21c97034 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -142,6 +142,7 @@ void clk_fractional_divider_general_approximation(struct clk_hw *hw, GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), m, n); } +EXPORT_SYMBOL_GPL(clk_fractional_divider_general_approximation); static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) From patchwork Mon Sep 18 07:31:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389083 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA2FCC46CA1 for ; Mon, 18 Sep 2023 07:44:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240202AbjIRHoX (ORCPT ); Mon, 18 Sep 2023 03:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240446AbjIRHoG (ORCPT ); Mon, 18 Sep 2023 03:44:06 -0400 X-Greylist: delayed 538 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Sep 2023 00:41:49 PDT Received: from mail-m127160.xmail.ntesmail.com (mail-m127160.xmail.ntesmail.com [115.236.127.160]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE1AA130; Mon, 18 Sep 2023 00:41:49 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=OVBVYR//m2GOTeqi6qbpjcHpfx0LAIPHufHrPyHGpugR30OthtIJY5L0htqTYiuizLQlrm3RZwhNFJU0Kyy1msBy66LlKq58eJf9tN/fcCz6yptJjb0T7Pc7DI+EflLLvviOCgr3wnL4ayluSF3/8LKF7YAljAkE1TlTpq2yD6c=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=DvBFYt+jqVEQKs9UGgC5VD5M1NXx2xvswehqQpfi6qw=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 5F67C6805DF; Mon, 18 Sep 2023 15:31:55 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 3/8] dt-bindings: clock: rk3188: Add binding id for ACLK_CPU_PRE Date: Mon, 18 Sep 2023 15:31:46 +0800 Message-Id: <20230918073151.7660-4-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhgfTlZLSR9IHR0aH0lDGEJVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa733f8f92eb5kusn5f67c6805df X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OCI6Shw5CD0CSkodIg4xSUMj KD0wC09VSlVKTUJOS0lJSEpNSUNPVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUlKTEw3Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org export clk id ACLK_CPU_PRE. Signed-off-by: Elaine Zhang Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/rk3188-cru-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index afad90680fce..e728ed076c5b 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -67,6 +67,7 @@ #define ACLK_PERI 204 #define ACLK_VEPU 205 #define ACLK_VDPU 206 +#define ACLK_CPU_PRE 207 /* pclk gates */ #define PCLK_GRF 320 From patchwork Mon Sep 18 07:31:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17D0DCD13D8 for ; Mon, 18 Sep 2023 07:45:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240407AbjIRHo5 (ORCPT ); Mon, 18 Sep 2023 03:44:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240506AbjIRHoi (ORCPT ); Mon, 18 Sep 2023 03:44:38 -0400 X-Greylist: delayed 534 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Sep 2023 00:41:58 PDT Received: from mail-m118217.qiye.163.com (mail-m118217.qiye.163.com [115.236.118.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6F961712; Mon, 18 Sep 2023 00:41:58 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=cXEWAkHDGmPNtGC+zH+jyoBPt7dPM9KsVgmnzEBn0jyy2hTmCGXO4KMx63UGn44MBkBAw6HVQx/Fo/rFTLQIynJtqTdvt4mmKdzady47Q5cR2ZO6LKGu/v1MeGnxI1Q633zKdJCt9/BaNnwrsPwjqpHJaILhXblF5XjKXfOYCUU=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=mCDlcmIjlYz7OGqXcpdzFmbIrrA6AUp7wdiTWKwutVk=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 529FF6805C3; Mon, 18 Sep 2023 15:31:56 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 4/8] clk: rockchip: Avoid __clk_lookup() calls Date: Mon, 18 Sep 2023 15:31:47 +0800 Message-Id: <20230918073151.7660-5-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGk0aT1YfGE1LHUtMTUMZHR5VEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa733fc8c2eb5kusn529ff6805c3 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6MAw6CDo6ND1RI0oXMgIISCNC LkswCTlVSlVKTUJOS0lJSEpMT01LVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhKQ0pPNwY+ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. clk provider clk_data.clks[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-cpu.c | 18 +++++++++++++----- drivers/clk/rockchip/clk-px30.c | 17 +++++++++++------ drivers/clk/rockchip/clk-rk3036.c | 5 +++-- drivers/clk/rockchip/clk-rk3128.c | 5 +++-- drivers/clk/rockchip/clk-rk3188.c | 22 +++++++++++----------- drivers/clk/rockchip/clk-rk3228.c | 5 +++-- drivers/clk/rockchip/clk-rk3288.c | 5 +++-- drivers/clk/rockchip/clk-rk3308.c | 5 +++-- drivers/clk/rockchip/clk-rk3328.c | 4 +++- drivers/clk/rockchip/clk-rk3368.c | 8 ++++---- drivers/clk/rockchip/clk-rk3399.c | 14 ++++---------- drivers/clk/rockchip/clk-rk3568.c | 5 +++-- drivers/clk/rockchip/clk-rk3588.c | 8 +++++--- drivers/clk/rockchip/clk-rv1108.c | 5 +++-- drivers/clk/rockchip/clk-rv1126.c | 8 +++++++- drivers/clk/rockchip/clk.c | 6 ++++-- drivers/clk/rockchip/clk.h | 17 ++++++++++------- 17 files changed, 93 insertions(+), 64 deletions(-) diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 6ea7fba9f9e5..9429d4f1fe41 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -298,7 +298,8 @@ static int rockchip_cpuclk_notifier_cb(struct notifier_block *nb, } struct clk *rockchip_clk_register_cpuclk(const char *name, - const char *const *parent_names, u8 num_parents, + u8 num_parents, + struct clk *parent, struct clk *alt_parent, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock) @@ -306,6 +307,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, struct rockchip_cpuclk *cpuclk; struct clk_init_data init; struct clk *clk, *cclk; + const char *parent_name; int ret; if (num_parents < 2) { @@ -313,12 +315,18 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, return ERR_PTR(-EINVAL); } + if (IS_ERR(parent) || IS_ERR(alt_parent)) { + pr_err("%s: invalid parent clock(s)\n", __func__); + return ERR_PTR(-EINVAL); + } + cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); if (!cpuclk) return ERR_PTR(-ENOMEM); + parent_name = clk_hw_get_name(__clk_get_hw(parent)); init.name = name; - init.parent_names = &parent_names[reg_data->mux_core_main]; + init.parent_names = &parent_name; init.num_parents = 1; init.ops = &rockchip_cpuclk_ops; @@ -336,7 +344,7 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb; cpuclk->hw.init = &init; - cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]); + cpuclk->alt_parent = alt_parent; if (!cpuclk->alt_parent) { pr_err("%s: could not lookup alternate parent: (%d)\n", __func__, reg_data->mux_core_alt); @@ -351,11 +359,11 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, goto free_cpuclk; } - clk = __clk_lookup(parent_names[reg_data->mux_core_main]); + clk = parent; if (!clk) { pr_err("%s: could not lookup parent clock: (%d) %s\n", __func__, reg_data->mux_core_main, - parent_names[reg_data->mux_core_main]); + parent_name); ret = -EINVAL; goto free_alt_parent; } diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 02fdb6273f4a..011b8bd89253 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -136,7 +136,6 @@ static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m"}; PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" }; PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" }; @@ -979,6 +978,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = { GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS), }; +static struct rockchip_clk_provider *cru_ctx; static void __init px30_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; @@ -1003,17 +1003,14 @@ static void __init px30_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, px30_clk_branches, ARRAY_SIZE(px30_clk_branches)); - rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), - &px30_cpuclk_data, px30_cpuclk_rates, - ARRAY_SIZE(px30_cpuclk_rates)); - rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0), ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_register_restart_notifier(ctx, PX30_GLB_SRST_FST, NULL); rockchip_clk_of_add_provider(np, ctx); + + cru_ctx = ctx; } CLK_OF_DECLARE(px30_cru, "rockchip,px30-cru", px30_clk_init); @@ -1021,6 +1018,7 @@ static void __init px30_pmu_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **pmucru_clks, **cru_clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1033,10 +1031,17 @@ static void __init px30_pmu_clk_init(struct device_node *np) pr_err("%s: rockchip pmu clk init failed\n", __func__); return; } + pmucru_clks = ctx->clk_data.clks; + cru_clks = cru_ctx->clk_data.clks; rockchip_clk_register_plls(ctx, px30_pmu_pll_clks, ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0); + rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", + 2, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL], + &px30_cpuclk_data, px30_cpuclk_rates, + ARRAY_SIZE(px30_cpuclk_rates)); + rockchip_clk_register_branches(ctx, px30_clk_pmu_branches, ARRAY_SIZE(px30_clk_pmu_branches)); diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 7cba188d9b01..a0089c89f143 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -114,7 +114,6 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m", "xin24m" }; -PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; @@ -431,6 +430,7 @@ static void __init rk3036_clk_init(struct device_node *np) struct rockchip_clk_provider *ctx; void __iomem *reg_base; struct clk *clk; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -451,6 +451,7 @@ static void __init rk3036_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1); if (IS_ERR(clk)) @@ -464,7 +465,7 @@ static void __init rk3036_clk_init(struct device_node *np) ARRAY_SIZE(rk3036_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3036_cpuclk_data, rk3036_cpuclk_rates, ARRAY_SIZE(rk3036_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 09931fc7dadc..f9c78b26f973 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -130,7 +130,6 @@ static const struct rockchip_cpuclk_reg_data rk3128_cpuclk_data = { PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" }; PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" }; @@ -566,6 +565,7 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -579,6 +579,7 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device iounmap(reg_base); return ERR_PTR(-ENOMEM); } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3128_pll_clks, ARRAY_SIZE(rk3128_pll_clks), @@ -587,7 +588,7 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device ARRAY_SIZE(common_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL_DIV2], &rk3128_cpuclk_data, rk3128_cpuclk_rates, ARRAY_SIZE(rk3128_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 455245815a11..d905299e5f4b 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -196,7 +196,6 @@ static const struct rockchip_cpuclk_reg_data rk3188_cpuclk_data = { }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -PNAME(mux_armclk_p) = { "apll", "gpll_armclk" }; PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" }; PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" }; PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" }; @@ -678,7 +677,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS), /* do not source aclk_cpu_pre from the apll, to keep complexity down */ - COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, + COMPOSITE_NOGATE(ACLK_CPU_PRE, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT, RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS), DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0, RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), @@ -778,10 +777,12 @@ static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device static void __init rk3066a_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + struct clk **clks; ctx = rk3188_common_clk_init(np); if (IS_ERR(ctx)) return; + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3066_pll_clks, ARRAY_SIZE(rk3066_pll_clks), @@ -789,7 +790,7 @@ static void __init rk3066a_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3066a_clk_branches, ARRAY_SIZE(rk3066a_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3066_cpuclk_data, rk3066_cpuclk_rates, ARRAY_SIZE(rk3066_cpuclk_rates)); rockchip_clk_of_add_provider(np, ctx); @@ -799,13 +800,14 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); static void __init rk3188a_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; - struct clk *clk1, *clk2; + struct clk **clks; unsigned long rate; int ret; ctx = rk3188_common_clk_init(np); if (IS_ERR(ctx)) return; + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3188_pll_clks, ARRAY_SIZE(rk3188_pll_clks), @@ -813,22 +815,20 @@ static void __init rk3188a_clk_init(struct device_node *np) rockchip_clk_register_branches(ctx, rk3188_clk_branches, ARRAY_SIZE(rk3188_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3188_cpuclk_data, rk3188_cpuclk_rates, ARRAY_SIZE(rk3188_cpuclk_rates)); /* reparent aclk_cpu_pre from apll */ - clk1 = __clk_lookup("aclk_cpu_pre"); - clk2 = __clk_lookup("gpll"); - if (clk1 && clk2) { - rate = clk_get_rate(clk1); + if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) { + rate = clk_get_rate(clks[ACLK_CPU_PRE]); - ret = clk_set_parent(clk1, clk2); + ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]); if (ret < 0) pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n", __func__); - clk_set_rate(clk1, rate); + clk_set_rate(clks[ACLK_CPU_PRE], rate); } else { pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n", __func__); diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index bcbf8f901965..6f185d65123a 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -132,7 +132,6 @@ static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = { PNAME(mux_pll_p) = { "clk_24m", "xin24m" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" }; PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" }; PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" }; @@ -660,6 +659,7 @@ static void __init rk3228_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -673,6 +673,7 @@ static void __init rk3228_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3228_pll_clks, ARRAY_SIZE(rk3228_pll_clks), @@ -681,7 +682,7 @@ static void __init rk3228_clk_init(struct device_node *np) ARRAY_SIZE(rk3228_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 3, clks[PLL_APLL], clks[PLL_GPLL], &rk3228_cpuclk_data, rk3228_cpuclk_rates, ARRAY_SIZE(rk3228_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 89db93c46403..81ab67716906 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -190,7 +190,6 @@ static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = { }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_core" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; @@ -922,6 +921,7 @@ static void __init rk3288_common_init(struct device_node *np, enum rk3288_variant soc) { struct rockchip_clk_provider *ctx; + struct clk **clks; rk3288_cru_base = of_iomap(np, 0); if (!rk3288_cru_base) { @@ -935,6 +935,7 @@ static void __init rk3288_common_init(struct device_node *np, iounmap(rk3288_cru_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3288_pll_clks, ARRAY_SIZE(rk3288_pll_clks), @@ -950,7 +951,7 @@ static void __init rk3288_common_init(struct device_node *np, ARRAY_SIZE(rk3288_hclkvio_branch)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3288_cpuclk_data, rk3288_cpuclk_rates, ARRAY_SIZE(rk3288_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 16a4dbd74146..b02154767a4e 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -121,7 +121,6 @@ static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m" }; PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" }; -PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" }; PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" }; PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" }; PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" }; @@ -905,6 +904,7 @@ static void __init rk3308_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -918,6 +918,7 @@ static void __init rk3308_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3308_pll_clks, ARRAY_SIZE(rk3308_pll_clks), @@ -926,7 +927,7 @@ static void __init rk3308_clk_init(struct device_node *np) ARRAY_SIZE(rk3308_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 3, clks[PLL_APLL], clks[PLL_VPLL0], &rk3308_cpuclk_data, rk3308_cpuclk_rates, ARRAY_SIZE(rk3308_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index a8686db20f0a..e6f86e460640 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -840,6 +840,7 @@ static void __init rk3328_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -853,6 +854,7 @@ static void __init rk3328_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3328_pll_clks, ARRAY_SIZE(rk3328_pll_clks), @@ -861,7 +863,7 @@ static void __init rk3328_clk_init(struct device_node *np) ARRAY_SIZE(rk3328_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 4, clks[PLL_APLL], clks[PLL_GPLL], &rk3328_cpuclk_data, rk3328_cpuclk_rates, ARRAY_SIZE(rk3328_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 3594454e3f45..17df0933c8cb 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -88,8 +88,6 @@ static struct rockchip_pll_rate_table rk3368_pll_rates[] = { }; PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" }; -PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" }; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" }; PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"}; PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" }; @@ -856,6 +854,7 @@ static void __init rk3368_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -869,6 +868,7 @@ static void __init rk3368_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3368_pll_clks, ARRAY_SIZE(rk3368_pll_clks), @@ -877,12 +877,12 @@ static void __init rk3368_clk_init(struct device_node *np) ARRAY_SIZE(rk3368_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", - mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), + 2, clks[PLL_APLLB], clks[PLL_GPLL], &rk3368_cpuclkb_data, rk3368_cpuclkb_rates, ARRAY_SIZE(rk3368_cpuclkb_rates)); rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", - mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + 2, clks[PLL_APLLL], clks[PLL_GPLL], &rk3368_cpuclkl_data, rk3368_cpuclkl_rates, ARRAY_SIZE(rk3368_cpuclkl_rates)); diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 619950265e8d..ee3bda968574 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -108,14 +108,6 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { /* CRU parents */ PNAME(mux_pll_p) = { "xin24m", "xin32k" }; -PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src", - "clk_core_l_bpll_src", - "clk_core_l_dpll_src", - "clk_core_l_gpll_src" }; -PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", - "clk_core_b_bpll_src", - "clk_core_b_dpll_src", - "clk_core_b_gpll_src" }; PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", "clk_ddrc_bpll_src", "clk_ddrc_dpll_src", @@ -1507,6 +1499,7 @@ static void __init rk3399_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1520,6 +1513,7 @@ static void __init rk3399_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3399_pll_clks, ARRAY_SIZE(rk3399_pll_clks), -1); @@ -1528,12 +1522,12 @@ static void __init rk3399_clk_init(struct device_node *np) ARRAY_SIZE(rk3399_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl", - mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + 4, clks[PLL_APLLL], clks[PLL_GPLL], &rk3399_cpuclkl_data, rk3399_cpuclkl_rates, ARRAY_SIZE(rk3399_cpuclkl_rates)); rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb", - mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), + 4, clks[PLL_APLLB], clks[PLL_GPLL], &rk3399_cpuclkb_data, rk3399_cpuclkb_rates, ARRAY_SIZE(rk3399_cpuclkb_rates)); diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index b1d173ef7da3..64d2278825ab 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -211,7 +211,6 @@ static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m" }; PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; -PNAME(mux_armclk_p) = { "apll", "gpll" }; PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_osc0_half" }; PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_osc0_half" }; PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_osc0_half" }; @@ -1616,6 +1615,7 @@ static void __init rk3568_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1629,13 +1629,14 @@ static void __init rk3568_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3568_pll_clks, ARRAY_SIZE(rk3568_pll_clks), RK3568_GRF_SOC_STATUS0); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 2, clks[PLL_APLL], clks[PLL_GPLL], &rk3568_cpuclk_data, rk3568_cpuclk_rates, ARRAY_SIZE(rk3568_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6994165e0395..6f0db8ce3ba9 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -2459,6 +2459,7 @@ static void __init rk3588_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -2472,21 +2473,22 @@ static void __init rk3588_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rk3588_pll_clks, ARRAY_SIZE(rk3588_pll_clks), RK3588_GRF_SOC_STATUS0); rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", - mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + 3, clks[PLL_LPLL], clks[PLL_GPLL], &rk3588_cpulclk_data, rk3588_cpulclk_rates, ARRAY_SIZE(rk3588_cpulclk_rates)); rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01", - mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p), + 3, clks[PLL_B0PLL], clks[PLL_GPLL], &rk3588_cpub0clk_data, rk3588_cpub0clk_rates, ARRAY_SIZE(rk3588_cpub0clk_rates)); rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23", - mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p), + 3, clks[PLL_B1PLL], clks[PLL_GPLL], &rk3588_cpub1clk_data, rk3588_cpub1clk_rates, ARRAY_SIZE(rk3588_cpub1clk_rates)); diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c index d290a4cf68b5..394eaf0198bb 100644 --- a/drivers/clk/rockchip/clk-rv1108.c +++ b/drivers/clk/rockchip/clk-rv1108.c @@ -118,7 +118,6 @@ static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m", "xin24m"}; PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" }; -PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" }; PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" }; PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" }; PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" }; @@ -772,6 +771,7 @@ static void __init rv1108_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -785,6 +785,7 @@ static void __init rv1108_clk_init(struct device_node *np) iounmap(reg_base); return; } + clks = ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rv1108_pll_clks, ARRAY_SIZE(rv1108_pll_clks), @@ -793,7 +794,7 @@ static void __init rv1108_clk_init(struct device_node *np) ARRAY_SIZE(rv1108_clk_branches)); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 3, clks[PLL_APLL], clks[PLL_GPLL], &rv1108_cpuclk_data, rv1108_cpuclk_rates, ARRAY_SIZE(rv1108_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c index 8eb0e2dfcb28..afd5c67cf244 100644 --- a/drivers/clk/rockchip/clk-rv1126.c +++ b/drivers/clk/rockchip/clk-rv1126.c @@ -1056,6 +1056,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { RV1126_CLKGATE_CON(23), 0, GFLAGS), }; +static struct rockchip_clk_provider *pmucru_ctx; static void __init rv1126_pmu_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; @@ -1084,12 +1085,15 @@ static void __init rv1126_pmu_clk_init(struct device_node *np) ROCKCHIP_SOFTRST_HIWORD_MASK); rockchip_clk_of_add_provider(np, ctx); + + pmucru_ctx = ctx; } static void __init rv1126_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; void __iomem *reg_base; + struct clk **cru_clks, **pmucru_clks; reg_base = of_iomap(np, 0); if (!reg_base) { @@ -1103,13 +1107,15 @@ static void __init rv1126_clk_init(struct device_node *np) iounmap(reg_base); return; } + cru_clks = ctx->clk_data.clks; + pmucru_clks = pmucru_ctx->clk_data.clks; rockchip_clk_register_plls(ctx, rv1126_pll_clks, ARRAY_SIZE(rv1126_pll_clks), RV1126_GRF_SOC_STATUS0); rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", - mux_armclk_p, ARRAY_SIZE(mux_armclk_p), + 3, cru_clks[PLL_APLL], pmucru_clks[PLL_GPLL], &rv1126_cpuclk_data, rv1126_cpuclk_rates, ARRAY_SIZE(rv1126_cpuclk_rates)); diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 9f23bd5ee22d..73b89dd3ca7d 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -575,15 +575,17 @@ EXPORT_SYMBOL_GPL(rockchip_clk_register_branches); void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, unsigned int lookup_id, - const char *name, const char *const *parent_names, + const char *name, u8 num_parents, + struct clk *parent, struct clk *alt_parent, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates) { struct clk *clk; - clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, + clk = rockchip_clk_register_cpuclk(name, num_parents, + parent, alt_parent, reg_data, rates, nrates, ctx->reg_base, &ctx->lock); if (IS_ERR(clk)) { diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 4fd3036817f4..a9937fc5804a 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -473,7 +473,8 @@ struct rockchip_cpuclk_reg_data { }; struct clk *rockchip_clk_register_cpuclk(const char *name, - const char *const *parent_names, u8 num_parents, + u8 num_parents, + struct clk *parent, struct clk *alt_parent, const struct rockchip_cpuclk_reg_data *reg_data, const struct rockchip_cpuclk_rate_table *rates, int nrates, void __iomem *reg_base, spinlock_t *lock); @@ -979,12 +980,14 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx, void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx, struct rockchip_pll_clock *pll_list, unsigned int nr_pll, int grf_lock_offset); -void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, - unsigned int lookup_id, const char *name, - const char *const *parent_names, u8 num_parents, - const struct rockchip_cpuclk_reg_data *reg_data, - const struct rockchip_cpuclk_rate_table *rates, - int nrates); +void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx, + unsigned int lookup_id, + const char *name, + u8 num_parents, + struct clk *parent, struct clk *alt_parent, + const struct rockchip_cpuclk_reg_data *reg_data, + const struct rockchip_cpuclk_rate_table *rates, + int nrates); void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx, unsigned int reg, void (*cb)(void)); From patchwork Mon Sep 18 07:31:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 893CDC46CA1 for ; Mon, 18 Sep 2023 07:43:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240270AbjIRHnW (ORCPT ); Mon, 18 Sep 2023 03:43:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240496AbjIRHnM (ORCPT ); Mon, 18 Sep 2023 03:43:12 -0400 X-Greylist: delayed 544 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Sep 2023 00:41:58 PDT Received: from mail-m49251.qiye.163.com (mail-m49251.qiye.163.com [45.254.49.251]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16E741B5; Mon, 18 Sep 2023 00:41:56 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=acOd2ke57QbjXIpr8WEZCRZSAYNGHf1HbxM9U1aGgLGr9PLnd+ACr878zLkd6X952/kTisl1H5l+X/5JEBTo0iYQ09aTdV94GKaJ0dM7q5b2nXv12U5Cmlk5QR8AZU80E4GXJ+0q11TBfZXMiS8UWgN2wqx5pqAI9PZYUXFBTOY=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=vyECsO4uy90lTUrx8mOBqqu8I+jSj4HmGYI/qGQDg4o=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 801BC680358; Mon, 18 Sep 2023 15:31:57 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 5/8] clk: rockchip: rk3399: Support module build Date: Mon, 18 Sep 2023 15:31:48 +0800 Message-Id: <20230918073151.7660-6-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRoaTlZCTE9CSh1IGUgdTk9VEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa73401362eb5kusn801bc680358 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OlE6Tjo5Qz1KN0oJIgwvSBA6 MysKCUJVSlVKTUJOS0lJSEpDT0NIVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhJS0g3Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org support CLK_OF_DECLARE and module_platform_driver double clk init method. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3399.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index ee3bda968574..dcc794dbb190 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1571,6 +1571,7 @@ static void __init rk3399_pmu_clk_init(struct device_node *np) } CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init); +#ifdef MODULE struct clk_rk3399_inits { void (*inits)(struct device_node *np); }; @@ -1593,8 +1594,9 @@ static const struct of_device_id clk_rk3399_match_table[] = { }, { } }; +MODULE_DEVICE_TABLE(of, clk_rk3399_match_table); -static int __init clk_rk3399_probe(struct platform_device *pdev) +static int clk_rk3399_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct of_device_id *match; @@ -1612,10 +1614,16 @@ static int __init clk_rk3399_probe(struct platform_device *pdev) } static struct platform_driver clk_rk3399_driver = { + .probe = clk_rk3399_probe, .driver = { .name = "clk-rk3399", .of_match_table = clk_rk3399_match_table, .suppress_bind_attrs = true, }, }; -builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe); +module_platform_driver(clk_rk3399_driver); + +MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clk-rk3399"); +#endif /* MODULE */ From patchwork Mon Sep 18 07:31:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA59BCD13D9 for ; Mon, 18 Sep 2023 07:45:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240422AbjIRHo7 (ORCPT ); Mon, 18 Sep 2023 03:44:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240487AbjIRHoi (ORCPT ); Mon, 18 Sep 2023 03:44:38 -0400 Received: from mail-m49226.qiye.163.com (mail-m49226.qiye.163.com [45.254.49.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2C4F18E; Mon, 18 Sep 2023 00:42:01 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=T9yjZlm7HyhCsWHXpRZQ0PVqlymuih1rHp3kM2Xsqf50HYG5brDEkzqRHx6hMnYqwegM4oaEaoxrLKpfkJ/Lk0p+xWkMMquwFnO1UnYlwtiZS7txcqAhuh5KCyVpgbedQuTeCoT5nNSrFNj0WOTkr3ma/Yukfm2LbQgohf3OS+w=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=R+b+U05rjVQsHcLYYo7FvRmUm3DUdEyeUtl3J6etFps=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 83310680600; Mon, 18 Sep 2023 15:31:58 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 6/8] clk: rockchip: rk3568: Support module build Date: Mon, 18 Sep 2023 15:31:49 +0800 Message-Id: <20230918073151.7660-7-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGhpCGFZCGkwfSUlCHR4YGhpVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa73405372eb5kusn83310680600 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6OBA6ATo*Tz1IHUoCFAxPSA8Q LhMaCRJVSlVKTUJOS0lJSEpCT0hLVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhKQk43Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org support CLK_OF_DECLARE and module_platform_driver double clk init method. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3568.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 64d2278825ab..5907f7e14201 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1653,6 +1653,7 @@ static void __init rk3568_clk_init(struct device_node *np) CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init); +#ifdef MODULE struct clk_rk3568_inits { void (*inits)(struct device_node *np); }; @@ -1675,8 +1676,9 @@ static const struct of_device_id clk_rk3568_match_table[] = { }, { } }; +MODULE_DEVICE_TABLE(of, clk_rk3568_match_table); -static int __init clk_rk3568_probe(struct platform_device *pdev) +static int clk_rk3568_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; const struct clk_rk3568_inits *init_data; @@ -1692,10 +1694,16 @@ static int __init clk_rk3568_probe(struct platform_device *pdev) } static struct platform_driver clk_rk3568_driver = { + .probe = clk_rk3568_probe, .driver = { .name = "clk-rk3568", .of_match_table = clk_rk3568_match_table, .suppress_bind_attrs = true, }, }; -builtin_platform_driver_probe(clk_rk3568_driver, clk_rk3568_probe); +module_platform_driver(clk_rk3568_driver); + +MODULE_DESCRIPTION("Rockchip RK3568 Clock Driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:clk-rk3568"); +#endif /* MODULE */ From patchwork Mon Sep 18 07:31:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B00CD37B0 for ; Mon, 18 Sep 2023 07:45:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240349AbjIRHo5 (ORCPT ); Mon, 18 Sep 2023 03:44:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240455AbjIRHoh (ORCPT ); Mon, 18 Sep 2023 03:44:37 -0400 Received: from mail-m49244.qiye.163.com (mail-m49244.qiye.163.com [45.254.49.244]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3945619A; Mon, 18 Sep 2023 00:42:00 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=anc0sa+d8rpcjzKssV90aHXJyouUoX4sa6cc8E8GkpuIFNV2UgBziV5zXdOumVXNie+eDu/bmQ4IPESh2l81HhgsQdUp5WxAnqlMS+pnuKRtY+gs4NW7QBZ1UHBjv19lGZ94/OW2LK+O9HG6NRt9gfsVVFb2vYlVu55GmxOOvIE=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=rQXmJM8WZ2P7TQ/NkWuRBycU5T8lBHAqSLpNdp/37dc=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 769C7680357; Mon, 18 Sep 2023 15:31:59 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 7/8] clk: rockchip: rk3588: Support module build Date: Mon, 18 Sep 2023 15:31:50 +0800 Message-Id: <20230918073151.7660-8-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQk1LT1YYQh1CSh5MH0pMGEpVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa73408c92eb5kusn769c7680357 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PBg6URw6AT1OSkoSSQERSA0I AyhPFENVSlVKTUJOS0lJSElLSEhPVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhKT0g3Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org support CLK_OF_DECLARE and module_platform_driver double clk init method. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3588.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3588.c b/drivers/clk/rockchip/clk-rk3588.c index 6f0db8ce3ba9..70ced70a3559 100644 --- a/drivers/clk/rockchip/clk-rk3588.c +++ b/drivers/clk/rockchip/clk-rk3588.c @@ -2504,6 +2504,7 @@ static void __init rk3588_clk_init(struct device_node *np) CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init); +#ifdef MODULE struct clk_rk3588_inits { void (*inits)(struct device_node *np); }; @@ -2519,8 +2520,9 @@ static const struct of_device_id clk_rk3588_match_table[] = { }, { } }; +MODULE_DEVICE_TABLE(of, clk_rk3588_match_table); -static int __init clk_rk3588_probe(struct platform_device *pdev) +static int clk_rk3588_probe(struct platform_device *pdev) { const struct clk_rk3588_inits *init_data; struct device *dev = &pdev->dev; @@ -2536,10 +2538,15 @@ static int __init clk_rk3588_probe(struct platform_device *pdev) } static struct platform_driver clk_rk3588_driver = { + .probe = clk_rk3588_probe, .driver = { .name = "clk-rk3588", .of_match_table = clk_rk3588_match_table, .suppress_bind_attrs = true, }, }; -builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe); +module_platform_driver(clk_rk3588_driver); + +MODULE_DESCRIPTION("Rockchip RK3588 Clock Driver"); +MODULE_LICENSE("GPL"); +#endif /* MODULE */ From patchwork Mon Sep 18 07:31:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elaine Zhang X-Patchwork-Id: 13389085 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 255FBCD13D1 for ; Mon, 18 Sep 2023 07:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240336AbjIRHoY (ORCPT ); Mon, 18 Sep 2023 03:44:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51298 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240488AbjIRHoR (ORCPT ); Mon, 18 Sep 2023 03:44:17 -0400 X-Greylist: delayed 533 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 18 Sep 2023 00:41:51 PDT Received: from m177126.mail.qiye.163.com (m177126.mail.qiye.163.com [123.58.177.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0DDFCE8; Mon, 18 Sep 2023 00:41:51 -0700 (PDT) DKIM-Signature: a=rsa-sha256; b=Dx/i0c+8V9/7en//12Jz5c5gBRAnA8seIFegWNqTloJQOPfPosEIAnxJ1nBsv+tCOpQGQCpkO+lYIuC78m77ZmKAjoLc/754Y4JguuMLbdU4uEus9lhZ8++WIk9IK1EHT6o4fxKHB5bOa6uEL0UmZCgFwQY0OyBrVcqhRHUdll8=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=FkT1/NwLGJhJV/2v8LOqPw2GTHqfJkCBrpYsiomQWlQ=; h=date:mime-version:subject:message-id:from; Received: from localhost.localdomain (unknown [58.22.7.114]) by mail-m11879.qiye.163.com (Hmail) with ESMTPA id 5EF406804E8; Mon, 18 Sep 2023 15:32:00 +0800 (CST) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, kever.yang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com Subject: [PATCH v1 8/8] clk: rockchip: fix the clk config to support module build Date: Mon, 18 Sep 2023 15:31:51 +0800 Message-Id: <20230918073151.7660-9-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230918073151.7660-1-zhangqing@rock-chips.com> References: <20230918073151.7660-1-zhangqing@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGRgZTVZKS0JISRoaHh5PHhpVEwETFh oSFyQUDg9ZV1kYEgtZQVlOQ1VJSVVMVUpKT1lXWRYaDxIVHRRZQVlPS0hVSk1PSU5JVUpLS1VKQl kG X-HM-Tid: 0a8aa7340c5a2eb5kusn5ef406804e8 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Ngg6NBw5OT1CL0oWIgwPSBMy QkxPFBVVSlVKTUJOS0lJSElKSE9CVTMWGhIXVQETGhUcChIVHDsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhLQ003Bg++ Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Mark COMMON_CLK_ROCKCHIP\CONFIG_CLK_RK3399\CONFIG_CLK_RK3568\ CONFIG_CLK_RK3588 to "tristate", to support building Rk3399\Rk3568\Rk3588 SoC clock driver as module. Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 9aad86925cd2..8574c2f6ecf6 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -2,7 +2,7 @@ # common clock support for ROCKCHIP SoC family. config COMMON_CLK_ROCKCHIP - bool "Rockchip clock controller common support" + tristate "Rockchip clock controller common support" depends on ARCH_ROCKCHIP default ARCH_ROCKCHIP help @@ -87,21 +87,21 @@ config CLK_RK3368 Build the driver for RK3368 Clock Driver. config CLK_RK3399 - bool "Rockchip RK3399 clock controller support" + tristate "Rockchip RK3399 clock controller support" depends on ARM64 || COMPILE_TEST default y help Build the driver for RK3399 Clock Driver. config CLK_RK3568 - bool "Rockchip RK3568 clock controller support" + tristate "Rockchip RK3568 clock controller support" depends on ARM64 || COMPILE_TEST default y help Build the driver for RK3568 Clock Driver. config CLK_RK3588 - bool "Rockchip RK3588 clock controller support" + tristate "Rockchip RK3588 clock controller support" depends on ARM64 || COMPILE_TEST default y help