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b=ozp+njqRZ1F9/kqX5V+lzsLS40Kum2xXIlI1NOK2t6MfzOZrfbzpKxpMi1vFg1kCv3Lt/EkEjmfNnPLyrtHkT0jGS9AKsWH8dW+9egl1F3DVEkVhUdSxlyzTl9F7xZJ+KYAezIJOKV7KkxihKiVCivb3dlc3ntzZen/byD1jko398AVxMuHh05Zd1Pq0h2cs/6n8FZ7fslKNPKmFn/JcgX+A+04CXtfOGq18/8e8nrgL0vCSSV0QVW9163iGg2jaoZ9yN5igr9Joxrzth7ga5Mx3w2KcLdlapiHHVGfc/qTgXD8Hz+fnAPO8TSYwpbX257NJq1X+EiymE4qrrrYg6Q== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Stewart Hildebrand , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v1 1/3] ARM: GICv3 ITS: issue INVALL command after mapping host events Thread-Topic: [PATCH v1 1/3] ARM: GICv3 ITS: issue INVALL command after mapping host events Thread-Index: AQHZ6ux4J+vpvrMLBESLD/bhCu4NsQ== Date: Tue, 19 Sep 2023 11:28:53 +0000 Message-ID: <20230919112827.1001484-2-volodymyr_babchuk@epam.com> References: <20230919112827.1001484-1-volodymyr_babchuk@epam.com> In-Reply-To: <20230919112827.1001484-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.42.0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: VI1PR03MB3710:EE_|AS8PR03MB10084:EE_ x-ms-office365-filtering-correlation-id: 6577df2f-e85d-4595-c12f-08dbb9039aef x-ld-processed: b41b72d0-4e9f-4c26-8a69-f949f367c91d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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It is working on real HW, so there is no sense in not doing this. Signed-off-by: Volodymyr Babchuk --- xen/arch/arm/gic-v3-its.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 3aa4edda10..a9c971a55f 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -236,6 +236,19 @@ static int its_send_cmd_inv(struct host_its *its, return its_send_command(its, cmd); } +static int its_send_cmd_invall(struct host_its *its, + uint32_t collection_id) +{ + uint64_t cmd[4]; + + cmd[0] = GITS_CMD_INVALL; + cmd[1] = 0x00; + cmd[2] = collection_id; + cmd[3] = 0x00; + + return its_send_command(its, cmd); +} + /* Set up the (1:1) collection mapping for the given host CPU. */ int gicv3_its_setup_collection(unsigned int cpu) { @@ -593,7 +606,9 @@ static int gicv3_its_map_host_events(struct host_its *its, return ret; } - /* TODO: Consider using INVALL here. Didn't work on the model, though. */ + ret = its_send_cmd_invall(its, 0); + if ( ret ) + return ret; ret = its_send_cmd_sync(its, 0); if ( ret ) From patchwork Tue Sep 19 11:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Volodymyr Babchuk X-Patchwork-Id: 13391260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A8E3CD54B5 for ; Tue, 19 Sep 2023 11:29:29 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.604612.942096 (Exim 4.92) (envelope-from ) id 1qiYuo-00012E-LL; Tue, 19 Sep 2023 11:29:14 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 604612.942096; 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b=c9yqxS4Tl6DWe3GO/inslCtsAAxHaLY4/mB5hRpQ6o69sYrNuFZbJ7lUQbSSri44xU/J9IqFtA1vHEOHTAboKU2+ewaoCq6twWQdKyo/9z+fVdqQUC2iZ4qldXt7gIlCZTiGzea2D4gK+lStECidHA41c5S9WrOyPZBDnU8HmHqHHMZ/kqnnop4i/kzTV6tUNRBjS/8OxVYuAHQrXNAcdQhx70jExeKb84RneNsdcQ4tExGp01d+85c7Z9z7otO9IQdMtAJ/vPro2a7Zpc3A8ieLrr7pvg25BU35EfIPcEj56HQbrmpFuNnxobSsiL6H2vGqJLO3/mBG2PVgY9fMRQ== From: Volodymyr Babchuk To: "xen-devel@lists.xenproject.org" CC: Stewart Hildebrand , Volodymyr Babchuk , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk Subject: [PATCH v1 2/3] ARM: GICv3 ITS: do not invalidate memory while sending a command Thread-Topic: [PATCH v1 2/3] ARM: GICv3 ITS: do not invalidate memory while sending a command Thread-Index: AQHZ6ux4LpE3chDIj0mOPudUv9951Q== Date: Tue, 19 Sep 2023 11:28:54 +0000 Message-ID: <20230919112827.1001484-3-volodymyr_babchuk@epam.com> References: <20230919112827.1001484-1-volodymyr_babchuk@epam.com> In-Reply-To: <20230919112827.1001484-1-volodymyr_babchuk@epam.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.42.0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: VI1PR03MB3710:EE_|AS8PR03MB10084:EE_ x-ms-office365-filtering-correlation-id: e72eac27-de73-4ec2-5afe-08dbb9039b2b x-ld-processed: b41b72d0-4e9f-4c26-8a69-f949f367c91d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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Writing itself guarantees that cache entry is valid. But we still need to flush cache line to be sure that ITS sees a command written into a queue. Signed-off-by: Volodymyr Babchuk --- xen/arch/arm/gic-v3-its.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index a9c971a55f..72cf318810 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -108,8 +108,7 @@ static int its_send_command(struct host_its *hw_its, const void *its_cmd) memcpy(hw_its->cmd_buf + writep, its_cmd, ITS_CMD_SIZE); if ( hw_its->flags & HOST_ITS_FLUSH_CMD_QUEUE ) - clean_and_invalidate_dcache_va_range(hw_its->cmd_buf + writep, - ITS_CMD_SIZE); + clean_dcache_va_range(hw_its->cmd_buf + writep, ITS_CMD_SIZE); else dsb(ishst); From patchwork Tue Sep 19 11:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Volodymyr Babchuk X-Patchwork-Id: 13391259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E02BCD54B5 for ; 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But there is one exception: ITS requires that DT and ITT must be initialized with zeroes. If ITS belongs to the Inner Cacheability domain there is no problem at all. But in all other cases we need to do clean CPU caches manually, or otherwise CPU can overwrite DT and ITT entries. From user perspective this looks like interrupts are not delivered from a device. Also, we will rename HOST_ITS_FLUSH_CMD_QUEUE flag to HOST_ITS_FLUSH_BUFFERS because now this flag controls not only command queue. Signed-off-by: Volodymyr Babchuk Tested-by: Stewart Hildebrand --- xen/arch/arm/gic-v3-its.c | 7 +++++-- xen/arch/arm/include/asm/gic_v3_its.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 72cf318810..63e28a7706 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -107,7 +107,7 @@ static int its_send_command(struct host_its *hw_its, const void *its_cmd) } memcpy(hw_its->cmd_buf + writep, its_cmd, ITS_CMD_SIZE); - if ( hw_its->flags & HOST_ITS_FLUSH_CMD_QUEUE ) + if ( hw_its->flags & HOST_ITS_FLUSH_BUFFERS ) clean_dcache_va_range(hw_its->cmd_buf + writep, ITS_CMD_SIZE); else dsb(ishst); @@ -335,7 +335,7 @@ static void *its_map_cbaser(struct host_its *its) */ if ( !(reg & GITS_BASER_INNER_CACHEABILITY_MASK) ) { - its->flags |= HOST_ITS_FLUSH_CMD_QUEUE; + its->flags |= HOST_ITS_FLUSH_BUFFERS; printk(XENLOG_WARNING "using non-cacheable ITS command queue\n"); } @@ -699,6 +699,9 @@ int gicv3_its_map_guest_device(struct domain *d, if ( !itt_addr ) goto out_unlock; + if ( hw_its->flags & HOST_ITS_FLUSH_BUFFERS ) + clean_dcache_va_range(itt_addr, nr_events * hw_its->itte_size); + dev = xzalloc(struct its_device); if ( !dev ) goto out_unlock; diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h index c24d4752d0..460b008db5 100644 --- a/xen/arch/arm/include/asm/gic_v3_its.h +++ b/xen/arch/arm/include/asm/gic_v3_its.h @@ -107,7 +107,7 @@ #include #include -#define HOST_ITS_FLUSH_CMD_QUEUE (1U << 0) +#define HOST_ITS_FLUSH_BUFFERS (1U << 0) #define HOST_ITS_USES_PTA (1U << 1) /* We allocate LPIs on the hosts in chunks of 32 to reduce handling overhead. */