From patchwork Tue Sep 19 11:47:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nirmoy Das X-Patchwork-Id: 13391271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C4ADCD54B9 for ; Tue, 19 Sep 2023 11:47:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A63A10E139; Tue, 19 Sep 2023 11:47:45 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B4DD10E10F; Tue, 19 Sep 2023 11:47:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695124062; x=1726660062; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=EZCE6lNO/5ZK4xDLwMtsiXiVPZzBD8iQ9YtFYhFBliY=; b=KT8AnnenBLFWYdhFhwRvZ+/ehwxyNt4kpKvVbnEOQQlPWZIhetsTnOKo w/Jw6MzfmShh4Q+PEFOL1pKe/ScJVqYMBA+PSNbY46aMWwrcHvP+FQq8N vG5GuSHwAc1BtZVc/Lr1hAsBzADOMj/9bZdAVkg6iaOxDyti9eB8VNlUb UN6SZzVTvMGnfxqnphLYZZZ0VN2GM6o4djMID9r3lRwX+xDJwxTitw/Za /h+nL7n1QT8e4/2saFN+ga5iyMmEbT6dSh0Kb1IOmfQQ1CrRfpPIMbYCf H64fcljSCqkffNehgRr3t8O9hs3NLbN5c5c+SRH+9+6T0ERbtkXqRgTHu w==; X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="410847282" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="410847282" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 04:47:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="861506893" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="861506893" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 04:47:38 -0700 From: Nirmoy Das To: intel-gfx@lists.freedesktop.org Subject: [PATCH] drm/i915: Fix aux invalidation with proper pipe_control flag Date: Tue, 19 Sep 2023 13:47:16 +0200 Message-ID: <20230919114716.19378-1-nirmoy.das@intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andi Shyti , Tvrtko Ursulin , Lucas De Marchi , Tejas Upadhyay , Jonathan Cavitt , stable@vger.kernel.org, dri-devel@lists.freedesktop.org, Andrzej Hajda , Matt Roper , Prathap Kumar Valsan , Nirmoy Das Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The suggestion from the spec is to do l3 fabric flush not L3 flush. Fixes: 78a6ccd65fa3 ("drm/i915/gt: Ensure memory quiesced before invalidation") Cc: Jonathan Cavitt Cc: Andi Shyti Cc: # v5.8+ Cc: Nirmoy Das Cc: Andrzej Hajda Cc: Tvrtko Ursulin Cc: Matt Roper Cc: Lucas De Marchi Cc: Tejas Upadhyay Cc: Prathap Kumar Valsan Signed-off-by: Nirmoy Das Reviewed-by: Andi Shyti Tested-by: Tapani Pälli Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 0143445dba83..a4b241d502c8 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -272,7 +272,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; - bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + if (mode & EMIT_FLUSH) + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + else if (gen12_needs_ccs_aux_inv(engine)) + bit_group_1 |= PIPE_CONTROL_L3_FABRIC_FLUSH; + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; /* Wa_1409600907:tgl,adl-p */ diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 2bd8d98d2110..12e8dc481c53 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -284,6 +284,7 @@ #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) +#define PIPE_CONTROL_L3_FABRIC_FLUSH (1<<30) #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) /* gen11+ */ #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) /* gen11+ */ #define PIPE_CONTROL_FLUSH_L3 (1<<27)