From patchwork Tue Sep 19 17:50:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13391699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAA08CE79A8 for ; Tue, 19 Sep 2023 17:50:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232084AbjISRus (ORCPT ); Tue, 19 Sep 2023 13:50:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232997AbjISRum (ORCPT ); Tue, 19 Sep 2023 13:50:42 -0400 Received: from mail-pf1-x44a.google.com (mail-pf1-x44a.google.com [IPv6:2607:f8b0:4864:20::44a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBB1D132 for ; Tue, 19 Sep 2023 10:50:26 -0700 (PDT) Received: by mail-pf1-x44a.google.com with SMTP id d2e1a72fcca58-690bbc5fabaso1596966b3a.1 for ; Tue, 19 Sep 2023 10:50:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1695145826; x=1695750626; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=Nc9IhLzKfLsRQeYUmIOlUXC0AFKZ1OL0TidKJ4UxU6g=; b=tc7UppjrMPGvlTNR5c+mNW/bklLZmi4LXq4pvUJs6TCWTA6vxQWrGr4bxBJn9J2sU9 l5cT2hUkqijNBsGqFjdNVhG5rW8z0U9X24/gBJIuzHXMw9IfG0JdJyM/LuGsNsW47o70 DSW9SQuy51gD6BD7VMIVAd+24u+s4DuDwbATlkncwaAReFgE0LhL6r9jkfv7LHxA7zWW qu/mLy4f+ycZYxtcFjGHlbFr4xeFywaGFTV7ZJyRLytmESweerWSvGeXpcPQ1Pg/X7vy +RbzFWgRniqSVNGbOLtZ1JUw2bZ0rVsBVW/J3Y2Owr297q7F7/Q+o/ALl7ANNrKB6Om2 wAnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695145826; x=1695750626; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Nc9IhLzKfLsRQeYUmIOlUXC0AFKZ1OL0TidKJ4UxU6g=; b=huxmsioixZm5UOClwi6AtlrdF3HVdlPxxh3MLDw1whsgusl+QJgzUalflQLExy3VCn pMUuvh+7qOiDiu4W3+q0mhjSWhkER+UZKJ/N3q/w4hhBLTsR9aQwcXI85rVMqPCaLGfR 6lmEPhc3+y7CAIqD5N5JSpw789/NbaCloUaXjNfNCghUhrnQ1ztaErlExMhZo0rGcQbE OX7ZBnPXAbo5lYLSbpvS40uAlogGKUJPJ5KDBZAH897sMyN4F0cSYZT+UIt/iX+MIB8q u1nVPYmHOmtWaVQKrOTD3s7MW8LEP2R+PVhrLuwlYkQ5XfDWZGZI8QvASBWElYIYzc9g YrRg== X-Gm-Message-State: AOJu0YyGGGRi8Zzo0S5kC3kAkgyFh9/lJ9cyxXPsL6ynwz/zX89Lq0Jw B2A4xoHplbbZ9HQRDeh50jy6oFXXNYiT388FRwA9nfXdQ+8UnvUPOPvqVxIivihPeLiK7v40+Sj jmeRiAI+Yu33bFEkcZBLigW1vLdoReGKJQRGkVFR4rhSxlm7NvNhGU3g3m87YXrsMJ5ol4Ms= X-Google-Smtp-Source: AGHT+IEzgFYHWoI5Y3ME7mliKGcMaRUOApa6TvADiOKyCMaHRzNyZfIVjUxH+iPvlizVJNpMNCc2HZAFY/N/OxlUeQ== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a05:6a00:2289:b0:68f:fa41:4e94 with SMTP id f9-20020a056a00228900b0068ffa414e94mr9025pfe.0.1695145825464; Tue, 19 Sep 2023 10:50:25 -0700 (PDT) Date: Tue, 19 Sep 2023 10:50:13 -0700 In-Reply-To: <20230919175017.538312-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230919175017.538312-1-jingzhangos@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175017.538312-2-jingzhangos@google.com> Subject: [PATCH v1 1/4] KVM: arm64: Allow userspace to get the writable masks for feature ID registers From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org While the Feature ID range is well defined and pretty large, it isn't inconceivable that the architecture will eventually grow some other ranges that will need to similarly be described to userspace. Add a VM ioctl to allow userspace to get writable masks for feature ID registers in below system register space: op0 = 3, op1 = {0, 1, 3}, CRn = 0, CRm = {0 - 7}, op2 = {0 - 7} This is used to support mix-and-match userspace and kernels for writable ID registers, where userspace may want to know upfront whether it can actually tweak the contents of an idreg or not. Add a new capability (KVM_CAP_ARM_SUPPORTED_FEATURE_ID_RANGES) that returns a bitmap of the valid ranges, which can subsequently be retrieved, one at a time by setting the index of the set bit as the range identifier. Suggested-by: Marc Zyngier Suggested-by: Cornelia Huck Signed-off-by: Jing Zhang --- arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/include/uapi/asm/kvm.h | 32 +++++++++++++++ arch/arm64/kvm/arm.c | 10 +++++ arch/arm64/kvm/sys_regs.c | 66 +++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 2 + 5 files changed, 112 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index af06ccb7ee34..5e3f778f81db 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1078,6 +1078,8 @@ int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm, struct kvm_arm_copy_mte_tags *copy_tags); int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, struct kvm_arm_counter_offset *offset); +int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, + struct reg_mask_range *range); /* Guest/host FPSIMD coordination helpers */ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index f7ddd73a8c0f..01242274db87 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -505,6 +505,38 @@ struct kvm_smccc_filter { #define KVM_HYPERCALL_EXIT_SMC (1U << 0) #define KVM_HYPERCALL_EXIT_16BIT (1U << 1) +/* + * Get feature ID registers userspace writable mask. + * + * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model + * Feature Register 2"): + * + * "The Feature ID space is defined as the System register space in + * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, + * op2=={0-7}." + * + * This covers all currently known R/O registers that indicate + * anything useful feature wise, including the ID registers. + * + * If we ever need to introduce a new range, it will be described as + * such in the range field. + */ +#define ARM64_FEATURE_ID_SPACE_IDX(op0, op1, crn, crm, op2) \ + ({ \ + __u64 __op1 = (op1) & 3; \ + __op1 -= (__op1 == 3); \ + (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \ + }) + +#define ARM64_FEATURE_ID_SPACE_SIZE (3 * 8 * 8) +#define ARM64_FEATURE_ID_RANGE_IDREGS BIT(0) + +struct reg_mask_range { + __u64 addr; /* Pointer to mask array */ + __u32 range; /* Requested range */ + __u32 reserved[13]; +}; + #endif #endif /* __ARM_KVM_H__ */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 4866b3f7b4ea..1c4017a253fd 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -317,6 +317,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES: r = kvm_supported_block_sizes(); break; + case KVM_CAP_ARM_SUPPORTED_FEATURE_ID_RANGES: + r = ARM64_FEATURE_ID_RANGE_IDREGS; + break; default: r = 0; } @@ -1629,6 +1632,13 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg) return kvm_vm_set_attr(kvm, &attr); } + case KVM_ARM_GET_REG_WRITABLE_MASKS: { + struct reg_mask_range range; + + if (copy_from_user(&range, argp, sizeof(range))) + return -EFAULT; + return kvm_vm_ioctl_get_reg_writable_masks(kvm, &range); + } default: return -EINVAL; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e92ec810d449..cdb9976d8091 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1373,6 +1373,13 @@ static inline bool is_id_reg(u32 id) sys_reg_CRm(id) < 8); } +static inline bool is_aa32_id_reg(u32 id) +{ + return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 && + sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 && + sys_reg_CRm(id) <= 3); +} + static unsigned int id_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -3572,6 +3579,65 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) return write_demux_regids(uindices); } +#define ARM64_FEATURE_ID_SPACE_INDEX(r) \ + ARM64_FEATURE_ID_SPACE_IDX(sys_reg_Op0(r), \ + sys_reg_Op1(r), \ + sys_reg_CRn(r), \ + sys_reg_CRm(r), \ + sys_reg_Op2(r)) + +static bool is_feature_id_reg(u32 encoding) +{ + return (sys_reg_Op0(encoding) == 3 && + (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) && + sys_reg_CRn(encoding) == 0 && + sys_reg_CRm(encoding) <= 7); +} + +int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range) +{ + const void *zero_page = page_to_virt(ZERO_PAGE(0)); + u64 __user *masks = (u64 __user *)range->addr; + + /* Only feature id range is supported, reserved[13] must be zero. */ + if (range->range != ARM64_FEATURE_ID_RANGE_IDREGS || + memcmp(range->reserved, zero_page, sizeof(range->reserved))) + return -EINVAL; + + /* Wipe the whole thing first */ + if (clear_user(masks, ARM64_FEATURE_ID_SPACE_SIZE * sizeof(__u64))) + return -EFAULT; + + for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) { + const struct sys_reg_desc *reg = &sys_reg_descs[i]; + u32 encoding = reg_to_encoding(reg); + u64 val; + + if (!is_feature_id_reg(encoding) || !reg->set_user) + continue; + + /* + * For ID registers, we return the writable mask. Other feature + * registers return a full 64bit mask. That's not necessary + * compliant with a given revision of the architecture, but the + * RES0/RES1 definitions allow us to do that. + */ + if (is_id_reg(encoding)) { + if (!reg->val || + (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) + continue; + val = reg->val; + } else { + val = ~0UL; + } + + if (put_user(val, (masks + ARM64_FEATURE_ID_SPACE_INDEX(encoding)))) + return -EFAULT; + } + + return 0; +} + int __init kvm_sys_reg_table_init(void) { struct sys_reg_params params; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 13065dd96132..2102df261f1b 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1192,6 +1192,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_COUNTER_OFFSET 227 #define KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE 228 #define KVM_CAP_ARM_SUPPORTED_BLOCK_SIZES 229 +#define KVM_CAP_ARM_SUPPORTED_FEATURE_ID_RANGES 230 #ifdef KVM_CAP_IRQ_ROUTING @@ -1562,6 +1563,7 @@ struct kvm_s390_ucas_mapping { #define KVM_ARM_MTE_COPY_TAGS _IOR(KVMIO, 0xb4, struct kvm_arm_copy_mte_tags) /* Available with KVM_CAP_COUNTER_OFFSET */ #define KVM_ARM_SET_COUNTER_OFFSET _IOW(KVMIO, 0xb5, struct kvm_arm_counter_offset) +#define KVM_ARM_GET_REG_WRITABLE_MASKS _IOR(KVMIO, 0xb6, struct reg_mask_range) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) From patchwork Tue Sep 19 17:50:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13391700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6B3ACE79AF for ; Tue, 19 Sep 2023 17:50:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232959AbjISRut (ORCPT ); Tue, 19 Sep 2023 13:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233001AbjISRum (ORCPT ); Tue, 19 Sep 2023 13:50:42 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DC24D6 for ; Tue, 19 Sep 2023 10:50:28 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-59b6a51f360so67437087b3.1 for ; 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Tue, 19 Sep 2023 10:50:27 -0700 (PDT) Date: Tue, 19 Sep 2023 10:50:14 -0700 In-Reply-To: <20230919175017.538312-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230919175017.538312-1-jingzhangos@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175017.538312-3-jingzhangos@google.com> Subject: [PATCH v1 2/4] KVM: arm64: Document KVM_ARM_GET_REG_WRITABLE_MASKS From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add some basic documentation on how to get feature ID register writable masks from userspace. Signed-off-by: Jing Zhang --- Documentation/virt/kvm/api.rst | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 21a7578142a1..2defb5e198ce 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6070,6 +6070,48 @@ writes to the CNTVCT_EL0 and CNTPCT_EL0 registers using the SET_ONE_REG interface. No error will be returned, but the resulting offset will not be applied. +4.139 KVM_ARM_GET_REG_WRITABLE_MASKS +------------------------------------------- + +:Capability: KVM_CAP_ARM_SUPPORTED_FEATURE_ID_RANGES +:Architectures: arm64 +:Type: vm ioctl +:Parameters: struct reg_mask_range (in/out) +:Returns: 0 on success, < 0 on error + + +:: + + #define ARM64_FEATURE_ID_SPACE_SIZE (3 * 8 * 8) + #define ARM64_FEATURE_ID_RANGE_IDREGS BIT(0) + + struct reg_mask_range { + __u64 addr; /* Pointer to mask array */ + __u32 range; /* Requested range */ + __u32 reserved[13]; + }; + +This ioctl copies the writable masks for Feature ID registers to userspace. +The Feature ID space is defined as the AArch64 System register space with +op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7}, op2=={0-7}. + +The mask array pointed to by ``addr`` is indexed by the macro +``ARM64_FEATURE_ID_SPACE_IDX(op0, op1, crn, crm, op2)``, allowing userspace +to know what bits can be changed for the system register described by ``op0, +op1, crn, crm, op2``. + +The ``range`` field describes the requested range of registers. The valid +ranges can be retrieved by checking the return value of +KVM_CAP_CHECK_EXTENSION_VM for the KVM_CAP_ARM_SUPPORTED_FEATURE_ID_RANGES +capability, which will return a bitmask of the supported ranges. Each bit +set in the return value represents a possible value for the ``range`` +field. At the time of writing, only bit 0 is returned set by the +capability, meaning that only the value ``ARM64_FEATURE_ID_RANGE_IDREGS`` +is valid for ``range``. + +The ``reserved[13]`` array is reserved for future use and should be 0, or +KVM may return an error. + 5. The kvm_run structure ======================== From patchwork Tue Sep 19 17:50:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13391701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD467CE79AD for ; Tue, 19 Sep 2023 17:50:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233205AbjISRuv (ORCPT ); Tue, 19 Sep 2023 13:50:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232871AbjISRuo (ORCPT ); Tue, 19 Sep 2023 13:50:44 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA87E1A6 for ; Tue, 19 Sep 2023 10:50:30 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-59e758d6236so36179397b3.1 for ; Tue, 19 Sep 2023 10:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1695145830; x=1695750630; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=+FfNGTxjW46m0vYg5JQZcFmeN0Q+crU/shufIChYdkI=; b=lsYPgEaENJhAm/UT5arGKGNsFrmMu/a+T4Iaske1Ha9/Pj93EjdFRl9MyclD93KjgT sRm11wGSCshnwi32Sgu4jccnYWIwP0WuOKN9OkkSCFesBc3ocaW8Ru5PH2jhuiUb1dG0 LBk7Xp+igTWjCzGrfK7TKCHzpcIXZ9zIz8h+iMCeY8KivXLboAd1qtc+iHniZZp69+RM 5vPpzz140NZVCRKDUpihvLZreKPBR56Ar+ESKPqvEi+TMqf91HoX8EyFE/AaITAhq0nd c5/xokj9hIIOr/FcWGXRdPcel6DDpKBAAAfXb9ewc3xCRGh0y13HlZn+mR/c6Nybuboh wCQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695145830; x=1695750630; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+FfNGTxjW46m0vYg5JQZcFmeN0Q+crU/shufIChYdkI=; b=eRzh6Aoyq9nzRJmpSUAc/bh2Dxj95ERgymJuBAuiPMMsIqF3lYXfS4d8mYLQ36c4eU F7JAlh6HV1Pi2GobWkxafx0nT4bZ9IwGgY05jopBpr8w2WH9eCP45DoVryAJJZLEoqrw Mla0Z0jFkjBk0Dv8YF8Sf9r5ddy9WrxKzAU0Wi9uelR8rGMYWdp3L/1NcgLSbqfcKlsM wL/AxYGr41CLjS2SnIrY+dL4ByT6iqv949D7fCRDgdCqdnLvNd7eleam8Z0ZajB6Yuu5 PYOX4R+ncNvVf9IQ9mpLuaClMccQOI1s3zbeq2u3ITU6j2wbSDybjwaMTodYswG61vXH V6wA== X-Gm-Message-State: AOJu0Yys6MyDa1Wmfl+EDkQ2su0NC4YRKGGLcHG539zizCcVh77hoGDN ZS9mCwzwt3oN2G925+AABLuOTrenBbBB88jfSfJ6nZTtz/7PC8IPBbILWIx27B/9FBDuSWTSq1Y bWzL8ijKnTHDB3XOXRDQPJcOYTh+Zxio9pR+g2DhfeERMUE677jZ7aVguobRQQrLIltn12cI= X-Google-Smtp-Source: AGHT+IHzfDyzqT0qS3LWIHvfZz7RLjnCjuKsmPhD/Jh5rsxGnZ1+liEskGzE0UZSm4JarDPcCE5W4ld3r7CjK2ykmA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:db07:0:b0:d81:78ec:c403 with SMTP id g7-20020a25db07000000b00d8178ecc403mr5069ybf.12.1695145829452; Tue, 19 Sep 2023 10:50:29 -0700 (PDT) Date: Tue, 19 Sep 2023 10:50:15 -0700 In-Reply-To: <20230919175017.538312-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230919175017.538312-1-jingzhangos@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175017.538312-4-jingzhangos@google.com> Subject: [PATCH v1 3/4] KVM: arm64: Use guest ID register values for the sake of emulation From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Since KVM now supports per-VM ID registers, use per-VM ID register values for the sake of emulation for DBGDIDR and LORegion. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index cdb9976d8091..4dcc9272fbb8 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -379,7 +379,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) { - u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + u64 val = IDREG(vcpu->kvm, SYS_ID_AA64MMFR1_EL1); u32 sr = reg_to_encoding(r); if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) { @@ -2445,8 +2445,8 @@ static bool trap_dbgdidr(struct kvm_vcpu *vcpu, if (p->is_write) { return ignore_write(vcpu, p); } else { - u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + u64 dfr = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); + u64 pfr = IDREG(vcpu->kvm, SYS_ID_AA64PFR0_EL1); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT); p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) | From patchwork Tue Sep 19 17:50:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13391702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6EBDCE79A9 for ; Tue, 19 Sep 2023 17:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232290AbjISRu6 (ORCPT ); Tue, 19 Sep 2023 13:50:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232935AbjISRuq (ORCPT ); Tue, 19 Sep 2023 13:50:46 -0400 Received: from mail-pj1-x104a.google.com (mail-pj1-x104a.google.com [IPv6:2607:f8b0:4864:20::104a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60062CC3 for ; Tue, 19 Sep 2023 10:50:33 -0700 (PDT) Received: by mail-pj1-x104a.google.com with SMTP id 98e67ed59e1d1-2746ce771f7so4264116a91.1 for ; Tue, 19 Sep 2023 10:50:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1695145833; x=1695750633; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=WDqS9gCK2hWJbMjalAxBpmnQXFt//tHeeybGxVMKHYk=; b=lMTmNEnz2Ppt85oaRrXLphKyQu2r6rLKdcC4x/r9LmdMoKBb145+agyYkwSmW4MxXg kG9werJRuD8xvp5bfmA2SuJUDrnvB3lblEwJ7ivQBoBQi52PbzxIOlLkolkTqj1ztdj/ Z9A45hZpQNDSRxxOXUb/4YLoL6mptHvja7XfmCcyWpz0j3n4N40ULygNVlTENPD0uASL /4xIxdo6Pyi5f5CyAQ0d4BkMNwXpjOplg0y7/DKWCWu1oQ6Zk5u22LFiLYHnttnj7CW3 t+shNYhdheLx4MP9mwTzESJUmpCejYV4KIGsI7Z+hvCAKhCSoOslxg4V1x4iYuDmvi3V 8jig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695145833; x=1695750633; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WDqS9gCK2hWJbMjalAxBpmnQXFt//tHeeybGxVMKHYk=; b=KgJxBvdVL/XL3pHPdYNUcahMHqNwCWMSYnqzPkH/ya1cThUF2LVKTOrLJsZsjNo+XB RGUZBOi0dSc3EOOYvWwZ41ALGN011DLvktUST1IozMmj5G1MBaKoYkFLyHvlQTciIJed hQhVaRfFuTC3rXc7Us4Asv1AgultDVUAr1HeF9J27VnuWuLXm7Mom9RNMUEk2W/Y784Y 4komMcEfj2ND+m5LLshfvEf+JgafWstu1diSX0V6D+X7kwx5X8ybW6gaSrxyCuO1a7tW C7K2KarKpK5mlBV8dvdobp3MTsCtgkvlXr66dfPRtHmnPI8BDq2eBjNZSSTYBhl0RKuY Uo0Q== X-Gm-Message-State: AOJu0YxReS7ap5kYLN7BnSnxc/ZFoVoEM6eDlH55o+8JO7Uwq+kp46tz mGgdJTgmH0febjgQc9ier64J/S4rtDngHXbKiZq6If2E+xw4mFd0PYo+DN99xA3ytY8vAlema7r 0rrOBZNV4NJ/SuhRZ19SdJlKQmFfJ26SkKwQG4qoOr18CVzyHiO3rg/HddVML9Oc03hiXZIs= X-Google-Smtp-Source: AGHT+IFN34HCsWwHcm0VPaYd7vZlKFFWGc9Vo3Vmh+MXi2TsekzYPzoQupklZxM0iu6EWzoGRPjs/bXawpslssLVYQ== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:90a:fa12:b0:268:1d63:b9ae with SMTP id cm18-20020a17090afa1200b002681d63b9aemr8189pjb.3.1695145831933; Tue, 19 Sep 2023 10:50:31 -0700 (PDT) Date: Tue, 19 Sep 2023 10:50:16 -0700 In-Reply-To: <20230919175017.538312-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230919175017.538312-1-jingzhangos@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175017.538312-5-jingzhangos@google.com> Subject: [PATCH v1 4/4] KVM: arm64: Reject attempts to set invalid debug arch version From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Suraj Jitindar Singh , Cornelia Huck , Shaoqin Huang , Jing Zhang Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Oliver Upton The debug architecture is mandatory in ARMv8, so KVM should not allow userspace to configure a vCPU with less than that. Of course, this isn't handled elegantly by the generic ID register plumbing, as the respective ID register fields have a nonzero starting value. Add an explicit check for debug versions less than v8 of the architecture. Signed-off-by: Oliver Upton Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 32 +++++++++++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 4dcc9272fbb8..fdebd9d042c3 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1216,8 +1216,14 @@ static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp, /* Some features have different safe value type in KVM than host features */ switch (id) { case SYS_ID_AA64DFR0_EL1: - if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT) + switch (kvm_ftr.shift) { + case ID_AA64DFR0_EL1_PMUVer_SHIFT: kvm_ftr.type = FTR_LOWER_SAFE; + break; + case ID_AA64DFR0_EL1_DebugVer_SHIFT: + kvm_ftr.type = FTR_LOWER_SAFE; + break; + } break; case SYS_ID_DFR0_EL1: if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT) @@ -1476,14 +1482,22 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, return val; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); /* Limit debug to ARMv8.0 */ - val &= ~ID_AA64DFR0_EL1_DebugVer_MASK; - val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, IMP); /* * Only initialize the PMU version if the vCPU was configured with one. @@ -1503,6 +1517,7 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 val) { + u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); /* @@ -1522,6 +1537,13 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) val &= ~ID_AA64DFR0_EL1_PMUVer_MASK; + /* + * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a + * nonzero minimum safe value. + */ + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + return -EINVAL; + return set_id_reg(vcpu, rd, val); } @@ -1543,6 +1565,7 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val) { u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val); + u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val); if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) { val &= ~ID_DFR0_EL1_PerfMon_MASK; @@ -1558,6 +1581,9 @@ static int set_id_dfr0_el1(struct kvm_vcpu *vcpu, if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3) return -EINVAL; + if (copdbg < ID_DFR0_EL1_CopDbg_Armv8) + return -EINVAL; + return set_id_reg(vcpu, rd, val); }