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Wed, 20 Sep 2023 06:55:43 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:34 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 1/5] dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc Date: Wed, 20 Sep 2023 14:54:55 +0800 Message-ID: <20230920065459.12738-2-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Veo2agWxmQWmvtKtOmi_uA5I-WMDMTpy X-Proofpoint-GUID: Veo2agWxmQWmvtKtOmi_uA5I-WMDMTpy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 mlxlogscore=880 impostorscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235608_623189_4CA5A656 X-CRM114-Status: GOOD ( 14.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add SM4450 PDC, which will used in SM4450 DTS. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan --- .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index 4847b04be1a1..86d61896f591 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -35,6 +35,7 @@ properties: - qcom,sdm845-pdc - qcom,sdx55-pdc - qcom,sdx65-pdc + - qcom,sm4450-pdc - qcom,sm6350-pdc - qcom,sm8150-pdc - qcom,sm8250-pdc From patchwork Wed Sep 20 06:54:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tengfei Fan X-Patchwork-Id: 13392225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC4D3CE79AC for ; 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Wed, 20 Sep 2023 06:55:51 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38K6toaO013672 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:55:50 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:41 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 2/5] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node Date: Wed, 20 Sep 2023 14:54:56 +0800 Message-ID: <20230920065459.12738-3-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: -F2BBsCD5l4LI3T4YYKOGJKshrqoe-Ql X-Proofpoint-GUID: -F2BBsCD5l4LI3T4YYKOGJKshrqoe-Ql X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 mlxscore=0 mlxlogscore=958 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235610_472317_9867D455 X-CRM114-Status: GOOD ( 15.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ajit Pandey Add apps_rsc node and cmd_db memory region for sm4450. Signed-off-by: Ajit Pandey Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index c4e5b33f5169..3d9d3b5e9510 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -328,6 +329,18 @@ }; }; + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + aop_cmd_db_mem: cmd-db@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -419,6 +432,28 @@ status = "disabled"; }; }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; 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Wed, 20 Sep 2023 06:55:56 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:48 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 3/5] arm64: dts: qcom: sm4450: Add RPMH and Global clock Date: Wed, 20 Sep 2023 14:54:57 +0800 Message-ID: <20230920065459.12738-4-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jutnzbhqGLtZpCdKf8SekOCbyOVBrz5G X-Proofpoint-ORIG-GUID: jutnzbhqGLtZpCdKf8SekOCbyOVBrz5G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 suspectscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=861 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235617_247509_55FFD77F X-CRM114-Status: GOOD ( 15.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device node for RPMH and Global clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 3d9d3b5e9510..c27f17a41699 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include #include #include #include @@ -348,6 +350,20 @@ dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; + gcc: clock-controller@100000 { + compatible = "qcom,sm4450-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -452,6 +468,13 @@ apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; + + rpmhcc: clock-controller { + compatible = "qcom,sm4450-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; }; }; From patchwork Wed Sep 20 06:54:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tengfei Fan X-Patchwork-Id: 13392226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFD6CCE79AC for ; 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Wed, 20 Sep 2023 06:56:04 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38K6u3Gc013587 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:56:03 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:54 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 4/5] arm64: dts: qcom: add uart console support for SM4450 Date: Wed, 20 Sep 2023 14:54:58 +0800 Message-ID: <20230920065459.12738-5-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bjlnyuLNUE96nO3ILyLea7OUJPEtkmGh X-Proofpoint-ORIG-GUID: bjlnyuLNUE96nO3ILyLea7OUJPEtkmGh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 mlxlogscore=878 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235622_020555_A4CD5382 X-CRM114-Status: GOOD ( 16.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add base description of UART and TLMM nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++- arch/arm64/boot/dts/qcom/sm4450.dtsi | 50 ++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts index 00a1c81ca397..0f253a2ba170 100644 --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts @@ -10,9 +10,23 @@ model = "Qualcomm Technologies, Inc. SM4450 QRD"; compatible = "qcom,sm4450-qrd", "qcom,sm4450"; - aliases { }; + aliases { + serial0 = &uart7; + }; chosen { - bootargs = "console=hvc0"; + stdout-path = "serial0:115200n8"; }; }; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <136 1>; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index c27f17a41699..727d6f7cf220 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -364,6 +364,29 @@ <0>; }; + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + uart7: serial@a88000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + status = "disabled"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -380,6 +403,32 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm4450-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 137>; + wakeup-parent = <&pdc>; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio23"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio22"; + function = "qup1_se2_l2"; + drive-strength = <2>; + bias-disable; + }; + }; + intc: interrupt-controller@17200000 { compatible = "arm,gic-v3"; reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ @@ -476,7 +525,6 @@ clocks = <&xo_board>; }; }; - }; timer { From patchwork Wed Sep 20 06:54:59 2023 Content-Type: text/plain; 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Wed, 20 Sep 2023 06:56:10 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:56:01 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 5/5] arm64: defconfig: enable clock controller and pinctrl for SM4450 Date: Wed, 20 Sep 2023 14:54:59 +0800 Message-ID: <20230920065459.12738-6-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230920065459.12738-1-quic_tengfan@quicinc.com> References: <20230920065459.12738-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BBoMmDX8I1JBsjmVZIpfWaXpuDBCblBS X-Proofpoint-ORIG-GUID: BBoMmDX8I1JBsjmVZIpfWaXpuDBCblBS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 suspectscore=0 mlxlogscore=660 mlxscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230919_235627_902012_3C2A995F X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable global clock controller and pinctrl for support the Qualcomm SM4450 platform to boot to UART console. The serial engine depends on some global clock controller and pinctrl, but as the serial console driver is only available as built-in, so the global clock controller and pinctrl also needs be built-in for the UART device to probe and register the console. Signed-off-by: Tengfei Fan --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 77c63c24b3a0..5bc9e9e94cf6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -598,6 +598,7 @@ CONFIG_PINCTRL_SC8280XP=y CONFIG_PINCTRL_SDM660=y CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y +CONFIG_PINCTRL_SM4450=y CONFIG_PINCTRL_SM6115=y CONFIG_PINCTRL_SM6125=y CONFIG_PINCTRL_SM6350=y @@ -1242,6 +1243,7 @@ CONFIG_SM_DISPCC_6115=m CONFIG_SM_DISPCC_8250=y CONFIG_SM_DISPCC_8450=m CONFIG_SM_DISPCC_8550=m +CONFIG_SM_GCC_4450=y CONFIG_SM_GCC_6115=y CONFIG_SM_GCC_8350=y CONFIG_SM_GCC_8450=y