From patchwork Thu Sep 21 15:06:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394115 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91F50328DA; Thu, 21 Sep 2023 17:22:38 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4AEF53664; Thu, 21 Sep 2023 10:16:49 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LATD9I031087; Thu, 21 Sep 2023 17:06:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=k2ysNniZTiB3pUaxQW8Vb1XOTlrzCqvDMX27IlP7ezU=; b=Yf dPOovkR+EKH2JR+hywe9DaeX7HlDuJkzAPuYPPIb64nlzt9EYhXZvadmYXjJ/lSt k6i8Ht0R72NTaov2ViMccUtPLQ5ma/N+gEiIz1MBURj+EO3DT7Wn6Z/pmbsZeEhz dSbT21AuK2GrdgkJi+4HnN3CQB3sd5U5mJE123ahZ0CVUvoe29SvHQUUywwlGZAM WpctJi/E3pqkiUTp3PYtbBu+jz4dRPURZHrt6+L3aUOZJEBalLUgfs+BShdV8fDP 51FAmDo5OHCIowDW/k7VQMYWN519TSv9IKvUKMH3yJlqvXgMs6xWbSnBRUh81JWB c8+Hokw/YYX3zlU16ecA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t51sfn3gh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:06:51 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 8668F100058; Thu, 21 Sep 2023 17:06:50 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4A461252250; Thu, 21 Sep 2023 17:06:50 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:06:49 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 1/7] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Thu, 21 Sep 2023 17:06:16 +0200 Message-ID: <20230921150622.599232-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../devicetree/bindings/net/stm32-dwmac.yaml | 140 +++++++++++++++--- 1 file changed, 118 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..75836916c38c 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,15 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: + - items: + - enum: + - st,stm32mp13-dwmac + - const: snps,dwmac-4.20a - items: - enum: - st,stm32mp1-dwmac @@ -72,27 +74,69 @@ properties: - eth-ck - ptp_ref - st,syscon: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to the syscon node which encompases the glue register - - description: offset of the control register + phy-supply: + description: PHY regulator + + st,ext-phyclk: description: - Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + set this property in RMII mode when you have PHY without crystal 50MHz and want to + select RCC clock instead of ETH_REF_CLK. or in RGMII mode when you want to select + RCC clock instead of ETH_CLK125. + type: boolean st,eth-clk-sel: + deprecated: true description: set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. type: boolean st,eth-ref-clk-sel: + deprecated: true description: set this property in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK. type: boolean +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the syscon node which encompases the glue register + - description: offset of the control register + description: + Should be phandle/offset pair. The phandle to the syscon node which + encompases the glue register, and the offset of the control register + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the syscon node which encompases the glue register + - description: offset of the control register + - description: field to set mask in register + description: + Should be phandle/offset pair. The phandle to the syscon node which + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register + required: - compatible - clocks @@ -112,24 +156,36 @@ examples: compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; reg-names = "stmmaceth"; - interrupts = ; - interrupt-names = "macirq"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <&exti 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; clock-names = "stmmaceth", - "mac-clk-tx", - "mac-clk-rx", - "ethstp", - "eth-ck"; + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; clocks = <&rcc ETHMAC>, - <&rcc ETHTX>, - <&rcc ETHRX>, - <&rcc ETHSTP>, - <&rcc ETHCK_K>; + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; st,syscon = <&syscfg 0x4>; + snps,mixed-burst; snps,pbl = <2>; + snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; phy-mode = "rgmii"; - }; + + stmmac_axi_config_0: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; - | //Example 2 (MCU example) @@ -161,3 +217,43 @@ examples: snps,pbl = <8>; phy-mode = "mii"; }; + + - | + #include + #include + #include + #include + //Example 4 + ethernet3: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + phy-mode = "rmii"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; From patchwork Thu Sep 21 15:06:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394218 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3026629438; Thu, 21 Sep 2023 17:49:48 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3794C7E7E4; Thu, 21 Sep 2023 10:35:20 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LB4EuF026736; Thu, 21 Sep 2023 17:06:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=HgdLqpCwv0ID+Ob78giBZKKYYOt0F9McKp/0y6gchIM=; b=mo hzVoDy8Tp13Fj7HEhBjgcLe6F//KVhTDHom7BOeyMqmbsnESfAYSXuWpNntmchJG 3YNfWZEKbXXljiHPNZaRjDEeBN+tbjmc4g+klvc0qk8X+x4N4b1HnTbXEu5PQWo+ nfgIoZaw+21ItOVMgJhOeun1UCzUOPPOYtbGEa1UsROrwA/7jZ3rhRR35LLvt0dJ 1HQjMW2cVKDxhn/kGNP6EZ92NnkduGkmvJ91e1ayRG+9d7lML9/Os/ZA0khbdybA uowUfvPD6FbUd/zglxZkkKtZ5FKRT1zSvWJvRTbCTpIywvaGdOVxw2XcSrhWk8R0 c6moW6cnZIoDtcF9T6Pg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t53px4sqx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:06:51 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3146710005C; Thu, 21 Sep 2023 17:06:51 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 26AB0252250; Thu, 21 Sep 2023 17:06:51 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:06:50 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 2/7] net: ethernet: stmmac: rework glue to simplify management for next stm32 Date: Thu, 21 Sep 2023 17:06:17 +0200 Message-ID: <20230921150622.599232-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Change glue to be more generic and manage easily next stm32 products. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 205 ++++++++++++------ 1 file changed, 139 insertions(+), 66 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index ab4324ed46da..762c5256398f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -23,10 +24,6 @@ #define SYSCFG_MCU_ETH_MASK BIT(23) #define SYSCFG_MP1_ETH_MASK GENMASK(23, 16) -#define SYSCFG_PMCCLRR_OFFSET 0x40 - -#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16) -#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17) /* CLOCK feed to PHY*/ #define ETH_CK_F_25M 25000000 @@ -46,9 +43,6 @@ * RMII | 1 | 0 | 0 | n/a | *------------------------------------------ */ -#define SYSCFG_PMCR_ETH_SEL_MII BIT(20) -#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21) -#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23) #define SYSCFG_PMCR_ETH_SEL_GMII 0 #define SYSCFG_MCU_ETH_SEL_MII 0 #define SYSCFG_MCU_ETH_SEL_RMII 1 @@ -62,17 +56,17 @@ *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| GMII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| RGMII | - | eth-ck | n/a | eth-ck | - *| | | st,ext-phyclk | | st,eth-clk-sel or| + *| | | | | st,eth-clk-sel or| *| | | | | st,ext-phyclk | * --------------------------------------------------------------------------- *| RMII | - | eth-ck | eth-ck | n/a | - *| | | st,ext-phyclk | st,eth-ref-clk-sel | | + *| | | | st,eth-ref-clk-sel | | *| | | | or st,ext-phyclk | | * --------------------------------------------------------------------------- * @@ -88,14 +82,27 @@ struct stm32_dwmac { int enable_eth_ck; int eth_clk_sel_reg; int eth_ref_clk_sel_reg; - int irq_pwr_wakeup; u32 mode_reg; /* MAC glue-logic mode register */ + u32 mode_mask; struct regmap *regmap; + struct regulator *regulator; u32 speed; const struct stm32_ops *ops; struct device *dev; }; +struct stm32_syscfg_pmcsetr { + u32 eth1_clk_sel; + u32 eth1_ref_clk_sel; + u32 eth1_selmii; + u32 eth1_sel_rgmii; + u32 eth1_sel_rmii; + u32 eth2_clk_sel; + u32 eth2_ref_clk_sel; + u32 eth2_sel_rgmii; + u32 eth2_sel_rmii; +}; + struct stm32_ops { int (*set_mode)(struct plat_stmmacenet_data *plat_dat); int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare); @@ -103,7 +110,8 @@ struct stm32_ops { void (*resume)(struct stm32_dwmac *dwmac); int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); - u32 syscfg_eth_mask; + u32 syscfg_clr_off; + struct stm32_syscfg_pmcsetr pmcsetr; }; static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) @@ -173,26 +181,26 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) dwmac->enable_eth_ck = false; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; - val = SYSCFG_PMCR_ETH_SEL_MII; + val = dwmac->ops->pmcsetr.eth1_selmii; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; - if (clk_rate == ETH_CK_F_25M && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_CLK_SEL; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: - val = SYSCFG_PMCR_ETH_SEL_RMII; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && + val = dwmac->ops->pmcsetr.eth1_sel_rmii | dwmac->ops->pmcsetr.eth2_sel_rmii; + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_50M) && (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; + val |= dwmac->ops->pmcsetr.eth1_ref_clk_sel; + val |= dwmac->ops->pmcsetr.eth2_ref_clk_sel; } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; @@ -200,11 +208,14 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: - val = SYSCFG_PMCR_ETH_SEL_RGMII; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && + val = dwmac->ops->pmcsetr.eth1_sel_rgmii | dwmac->ops->pmcsetr.eth2_sel_rgmii; + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_CLK_SEL; + val |= dwmac->ops->pmcsetr.eth1_clk_sel; + val |= dwmac->ops->pmcsetr.eth2_clk_sel; } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; @@ -216,12 +227,12 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) } /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, - dwmac->ops->syscfg_eth_mask); + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, + dwmac->mode_mask); /* Update PMCSETR (set register) */ return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val); + dwmac->mode_mask, val); } static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -247,7 +258,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) } return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val << 23); + SYSCFG_MCU_ETH_MASK, val << 23); } static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac) @@ -290,18 +301,33 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, return PTR_ERR(dwmac->regmap); err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); + if (err) { + dev_err(dev, "Can't get sysconfig register offset (%d)\n", err); + return err; + } + + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); if (err) - dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); + pr_debug("Warning sysconfig register mask not set\n"); - return err; + dwmac->regulator = devm_regulator_get_optional(dev, "phy"); + if (IS_ERR(dwmac->regulator)) { + if (PTR_ERR(dwmac->regulator) == -EPROBE_DEFER) { + dev_dbg(dev, "phy regulator is not available yet, deferred probing\n"); + return -EPROBE_DEFER; + } + dev_dbg(dev, "no regulator found\n"); + dwmac->regulator = NULL; + } + + return 0; } static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; - int err = 0; /* Ethernet PHY have no crystal */ dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); @@ -316,7 +342,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, /* Get ETH_CLK clocks */ dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); if (IS_ERR(dwmac->clk_eth_ck)) { - dev_info(dev, "No phy clock provided...\n"); + dev_dbg(dev, "No phy clock provided...\n"); dwmac->clk_eth_ck = NULL; } @@ -333,29 +359,45 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, if (IS_ERR(dwmac->syscfg_clk)) dwmac->syscfg_clk = NULL; - /* Get IRQ information early to have an ability to ask for deferred - * probe if needed before we went too far with resource allocation. - */ - dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev, - "stm32_pwr_wakeup"); - if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) { - err = device_init_wakeup(&pdev->dev, true); - if (err) { - dev_err(&pdev->dev, "Failed to init wake up irq\n"); - return err; - } - err = dev_pm_set_dedicated_wake_irq(&pdev->dev, - dwmac->irq_pwr_wakeup); - if (err) { - dev_err(&pdev->dev, "Failed to set wake up irq\n"); - device_init_wakeup(&pdev->dev, false); - } - device_set_wakeup_enable(&pdev->dev, false); + return 0; +} + +static int stm32_dwmac_wake_init(struct device *dev, + struct stmmac_resources *stmmac_res) +{ + int err; + + device_set_wakeup_capable(dev, true); + + err = dev_pm_set_wake_irq(dev, stmmac_res->wol_irq); + if (err) { + dev_err(dev, "Failed to set wake up irq\n"); + device_set_wakeup_capable(dev, false); + return err; + } + + return 0; +} + +static int phy_power_on(struct stm32_dwmac *bsp_priv, bool enable) +{ + int ret; + struct device *dev = bsp_priv->dev; + + if (!bsp_priv->regulator) + return 0; + + if (enable) { + ret = regulator_enable(bsp_priv->regulator); + if (ret) + dev_err(dev, "fail to enable phy-supply\n"); + } else { + ret = regulator_disable(bsp_priv->regulator); + if (ret) + dev_err(dev, "fail to disable phy-supply\n"); } - return err; + + return 0; } static int stm32_dwmac_probe(struct platform_device *pdev) @@ -393,21 +435,37 @@ static int stm32_dwmac_probe(struct platform_device *pdev) return ret; } + if (stmmac_res.wol_irq && !dwmac->clk_eth_ck) { + ret = stm32_dwmac_wake_init(&pdev->dev, &stmmac_res); + if (ret) + goto err_wake_init_disable; + } + plat_dat->bsp_priv = dwmac; ret = stm32_dwmac_init(plat_dat); if (ret) - return ret; + goto err_wake_init_disable; - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = phy_power_on(plat_dat->bsp_priv, true); if (ret) goto err_clk_disable; + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_gmac_powerdown; + return 0; +err_gmac_powerdown: + phy_power_on(plat_dat->bsp_priv, false); err_clk_disable: stm32_dwmac_clk_disable(dwmac); - +err_wake_init_disable: + if (stmmac_res.wol_irq && !dwmac->clk_eth_ck) { + dev_pm_clear_wake_irq(&pdev->dev); + device_set_wakeup_capable(&pdev->dev, false); + } return ret; } @@ -415,16 +473,13 @@ static void stm32_dwmac_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct stmmac_priv *priv = netdev_priv(ndev); - struct stm32_dwmac *dwmac = priv->plat->bsp_priv; stmmac_dvr_remove(&pdev->dev); stm32_dwmac_clk_disable(priv->plat->bsp_priv); - if (dwmac->irq_pwr_wakeup >= 0) { - dev_pm_clear_wake_irq(&pdev->dev); - device_init_wakeup(&pdev->dev, false); - } + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); } static int stm32mp1_suspend(struct stm32_dwmac *dwmac) @@ -440,12 +495,20 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac) if (dwmac->enable_eth_ck) clk_disable_unprepare(dwmac->clk_eth_ck); + /* Keep the PHY up if we use Wake-on-Lan. */ + if (!device_may_wakeup(dwmac->dev)) + phy_power_on(dwmac, false); + return ret; } static void stm32mp1_resume(struct stm32_dwmac *dwmac) { clk_disable_unprepare(dwmac->clk_ethstp); + + /* The PHY was up for Wake-on-Lan. */ + if (!device_may_wakeup(dwmac->dev)) + phy_power_on(dwmac, true); } static int stm32mcu_suspend(struct stm32_dwmac *dwmac) @@ -499,7 +562,6 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, static struct stm32_ops stm32mcu_dwmac_data = { .set_mode = stm32mcu_set_mode, .suspend = stm32mcu_suspend, - .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK }; static struct stm32_ops stm32mp1_dwmac_data = { @@ -508,7 +570,18 @@ static struct stm32_ops stm32mp1_dwmac_data = { .suspend = stm32mp1_suspend, .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, - .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK + .syscfg_clr_off = 0x44, + .pmcsetr = { + .eth1_clk_sel = BIT(16), + .eth1_ref_clk_sel = BIT(17), + .eth1_selmii = BIT(20), + .eth1_sel_rgmii = BIT(21), + .eth1_sel_rmii = BIT(23), + .eth2_clk_sel = 0, + .eth2_ref_clk_sel = 0, + .eth2_sel_rgmii = 0, + .eth2_sel_rmii = 0 + } }; static const struct of_device_id stm32_dwmac_match[] = { From patchwork Thu Sep 21 15:06:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394090 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E7321803D; Thu, 21 Sep 2023 17:10:01 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E973D1FF7; Thu, 21 Sep 2023 10:09:28 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LBWej4026620; Thu, 21 Sep 2023 17:06:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 21 Sep 2023 17:06:51 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:06:51 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 3/7] net: ethernet: stmmac: add management of stm32mp13 for stm32 Date: Thu, 21 Sep 2023 17:06:18 +0200 Message-ID: <20230921150622.599232-4-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net X-Patchwork-Delegate: kuba@kernel.org Add Ethernet support for STM32MP13. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 762c5256398f..0f843ab3822f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -584,9 +584,30 @@ static struct stm32_ops stm32mp1_dwmac_data = { } }; +static struct stm32_ops stm32mp13_dwmac_data = { + .set_mode = stm32mp1_set_mode, + .clk_prepare = stm32mp1_clk_prepare, + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, + .syscfg_clr_off = 0x08, + .pmcsetr = { + .eth1_clk_sel = BIT(16), + .eth1_ref_clk_sel = BIT(17), + .eth1_selmii = 0, + .eth1_sel_rgmii = BIT(21), + .eth1_sel_rmii = BIT(23), + .eth2_clk_sel = BIT(24), + .eth2_ref_clk_sel = BIT(25), + .eth2_sel_rgmii = BIT(29), + .eth2_sel_rmii = BIT(31) + } +}; + static const struct of_device_id stm32_dwmac_match[] = { { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, + { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, { } }; MODULE_DEVICE_TABLE(of, stm32_dwmac_match); From patchwork Thu Sep 21 15:06:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394145 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B19F445F60; Thu, 21 Sep 2023 17:24:31 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC7A51F26; Thu, 21 Sep 2023 10:23:57 -0700 (PDT) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LAxpKM001781; Thu, 21 Sep 2023 17:06:53 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=0VUKdAaSXm7Howm9XkOWAHruu18FxRlOmQhy2i7q6Fs=; b=HG 2Fm5GJ+DmQKU8R7/HIrmgiFlZWXTpFXF9h+G5SWBe7blveet5AIg+y7v2SgddVqB Md0JV+2ZAzrcQi7sI1YthVjquldc6sCXudfVDbyA77kLd0lVcWPi7PJoveka/Slb K5hQKcSX0SCb9DtlA4B4wt37Mzg81tXJ3s4HiogRDs+vfUAIafqByVdJn8Xobydo Czi0V81Pk0gmw25UTqn85K7E80+ueDKykHYJUFf0SMJcgiW8EZeHGCIT3EnG7KHp qPQqaoVg3+Cz+itL73qSQdRI6YtiYrTK+7Cz8Sm54PAz051ydGRCUH1RkZZEzFSp OYqBZVkT2Vxq9kGVyOnw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t5nx0u3g3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:06:53 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C2BBB100057; Thu, 21 Sep 2023 17:06:52 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BA93A252250; Thu, 21 Sep 2023 17:06:52 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:06:51 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 4/7] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13 Date: Thu, 21 Sep 2023 17:06:19 +0200 Message-ID: <20230921150622.599232-5-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp131.dtsi | 31 ++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 30 +++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index ac90fcbf0c09..d8339eea05d5 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1296,6 +1296,37 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index df451c3c2a26..aee855cd2f36 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -64,5 +64,35 @@ channel@18 { }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; }; }; From patchwork Thu Sep 21 15:06:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394289 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2987513C0; Thu, 21 Sep 2023 18:34:39 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1103AD62EC; Thu, 21 Sep 2023 11:26:56 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LAbQtR000605; Thu, 21 Sep 2023 17:08:03 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=3/V2xXKbKiuormTCKyq/pzyo0NKY0Oe2d+uD3Di/oxk=; b=0w 1AS85Nwu6+wZckk3AYgcNbdI7gjEr0qtI18DA9MPjNp0UgarhtRYnYo5OQx84bXC Bkbx2ww+3Gubs574r641rf88vHErp83GDZYFBIL6LJSSZhQjpF/+F4Lysgxn5Xo4 Px+ULbceOrpjurZCOA3nbKtD4+h10FLw2BBXBlO1/HrVfI8dQesjcgHchBeJvtnG 4BCn2ZpjAoZzx9u7P1ns1LmkVi7NsMRoUr4nFPuAKoqJJ9+3ICWTICvOziJshYeq oI7KD7dArU6h34jL48Mwo9x86jHpXGvXFpOAdT7S5F9c1z4Yy0T0c/ZkrvudgdoJ niFk2PVL6hDJk7S3P6+Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t51sfn3nd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:08:03 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0416C100057; Thu, 21 Sep 2023 17:08:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EFD3F25225F; Thu, 21 Sep 2023 17:08:02 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:08:02 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 5/7] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Date: Thu, 21 Sep 2023 17:06:20 +0200 Message-ID: <20230921150622.599232-6-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 27e0c3826789..b2583df813af 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,77 @@ pins { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From patchwork Thu Sep 21 15:06:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394214 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E64681799F; Thu, 21 Sep 2023 17:49:08 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E961790A71; Thu, 21 Sep 2023 10:47:09 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LATD9S031087; Thu, 21 Sep 2023 17:08:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=DaNcFv3F7lcl33eD683tXuCPbabyLWEwzze4nvIxM/8=; b=XO y4ozePFttTWxeHAcdMkAgbXLjFbOV1OH4Sf5ShbBEhn+nMJc8p5/nF2WeR8aOcV+ xbk2iGu/S7HpGoTmoInzdC+GQMGdSw58C/kkyR8i+GwQF2vnpvjHysn1lW130P6d bTJSD7eEnGxpiZaxdq3ooUm6PiZJx5vcjv+hR4Ab4v264CQOwczjJ9tSIfhkW2hj WWKiQFx2SRGWACPBH5w3pG6xSEag6tSGxu2mHyVZnQMAePHvIq5GcDJcpNYOhl90 Nm5XNT5HaPw8OovO6u2wGnoaBfltiTBz+TAbBFg++qhVwD+7aiSd3uVNDfsQqXBw 7v0P2RZA8FlimjUdo2Ew== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t51sfn3nf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:08:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C8CC0100058; Thu, 21 Sep 2023 17:08:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BC2BF257A80; Thu, 21 Sep 2023 17:08:03 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:08:03 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 6/7] ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board Date: Thu, 21 Sep 2023 17:06:21 +0200 Message-ID: <20230921150622.599232-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add dual Ethernet: -Ethernet1: RMII with crystal -Ethernet2: RMII without crystal With Ethernet1, we can performed WoL from PHY instead of GMAC point of view. (in this case IRQ for WoL is managed as wakeup pin and configured in OS secure). Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index eea740d097c7..1316cc16f8dd 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,8 @@ / { compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -93,6 +95,52 @@ channel@12 { }; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg = <0>; + wakeup-source; + }; + }; +}; + +ðernet2 { + status = "okay"; + pinctrl-0 = <ð2_rmii_pins_a>; + pinctrl-1 = <ð2_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth2>; + st,ext-phyclk; + phy-supply = <&scmi_v3v3_sw>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From patchwork Thu Sep 21 15:06:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13394116 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CA3C44494; Thu, 21 Sep 2023 17:23:03 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D4515A026; Thu, 21 Sep 2023 10:20:53 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38LB5qEa030987; Thu, 21 Sep 2023 17:08:05 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=zKgubgfi6Pb54XiIzppYUInYCBS8Pc8fetwYjtT9IwE=; b=lf I4Erdufi2YGpRtcdZ4ukaRioDOkkOFDAo+q9KbDCrPqhWHqd8+QWs9dDW2S75u4Y +DG4xtMwDF5p5ypY7BMb4SVC2enFhnH+GXeAZg1hm1iA0TSU9hMLXbN28Uuk+vuh MGbpU0KqWLKODwyMr5mKuqAaGonf+VIH2612ru9rYZbgXoi9Dc1H9eNZttsIrTu8 9LfUoy9cCuEflmoQc5fV0M84x51fdVmzlxe2/G1srrm7e6nRZugd29cQJ6ITxzel oz1EvLOKiLD+68HcK9FQKpAIYTjqIEPeqoeH/xJ23sA4TebW0bjEnddXhrpzczXU hmnh5Dttjs1pL075nITw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t51sfn3nk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Sep 2023 17:08:05 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3993A100057; Thu, 21 Sep 2023 17:08:05 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 31832257A80; Thu, 21 Sep 2023 17:08:05 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 21 Sep 2023 17:08:04 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 7/7] ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support Date: Thu, 21 Sep 2023 17:06:22 +0200 Message-ID: <20230921150622.599232-8-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Need to enable MCP23S08 I/O expanders to manage Ethernet phy reset in STM32MP135F-DK board STMMAC driver defer is not silent, need to put this config in built-in to avoid huge of Ethernet messages Signed-off-by: Christophe Roullier --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 23fc49f23d25..373f58f2d5b9 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -458,6 +458,7 @@ CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y