From patchwork Fri Sep 22 13:30:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13395790 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42042E6FE2A for ; Fri, 22 Sep 2023 13:30:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE4AF10E66C; Fri, 22 Sep 2023 13:30:57 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 861E710E66D; Fri, 22 Sep 2023 13:30:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695389445; x=1726925445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Do4qj4VhMHy0ehSIxkujcxGmFZxKQE6vyCcDB+176Zc=; b=W97mLTqdsDBkBoXZS9v0/4Jhzzz8u1xpXs7rb4u9cUAmbXXOa8XC4pYn LaiXJU8Y5lqJNWEkVujl4HnamovsX4pThNiqeb7ZUOfGxQ2jN0sta7w/Z IAWDzfbKLUxddE+PHfuJif5fagLCnUIydj+LTs/CLGVKqpLop66c9XqRu tJ6dpj3eAHvF7VcWAXUtBUR59pqeoKqMoA+MWwFq0gm+lkd0j+h3NKT7V 07Hqypr5PThbK8Kz4txKgXlqiS5wIzWKMVNGSRf28Q72FzWPAypu6Y/7J X4VYR5qx49zA2BDHlpzerN8Ro2LxktAOiAwF9Rt2nuyBvJQDWTMeKZ58m g==; X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="361078358" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="361078358" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 06:30:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="1078374387" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="1078374387" Received: from rvaittin-mobl.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.251.220.9]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 06:30:18 -0700 From: Vinod Govindapillai To: intel-xe@lists.freedesktop.org Date: Fri, 22 Sep 2023 16:30:02 +0300 Message-Id: <20230922133003.150578-2-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922133003.150578-1-vinod.govindapillai@intel.com> References: <20230922133003.150578-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v5 1/2] drm/i915/lnl: possibility to enable FBC on first three planes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In LNL onwards, FBC can be associated to the first three planes. FBC will be enabled on planes first come first served basis until the userspace can select one of these FBC capable planes explicitly. v2: - avoid fbc->state.plane check in intel_fbc_check_plane (Ville) - simplify plane binding register writes (Matt) - Update the subject to reflect that fbc can be enabled only in the first three planes (Matt) v3: - use icl_is_hdr_plane(), use wrapper macro for plane binding register access, comments update and patch split (Ville) v4: - update to the plane binding register access macro Bspec: 69560 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 7f70166f7035..aef5a4f6ad09 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -592,6 +592,9 @@ static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) if (IS_IVYBRIDGE(i915)) dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); + if (DISPLAY_VER(i915) >= 20) + dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); + if (fbc_state->fence_id >= 0) dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 4d01c7ae4485..8f946c5a2fd8 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1956,13 +1956,16 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) return pipe - PIPE_A + INTEL_FBC_A; } -static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, +static bool skl_plane_has_fbc(struct drm_i915_private *i915, enum intel_fbc_id fbc_id, enum plane_id plane_id) { - if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0) + if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0) return false; - return plane_id == PLANE_PRIMARY; + if (DISPLAY_VER(i915) >= 20) + return icl_is_hdr_plane(i915, plane_id); + else + return plane_id == PLANE_PRIMARY; } static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index aefad14ab27a..d44ac6f1c052 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1327,6 +1327,8 @@ #define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) #define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) #define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ #define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ #define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ From patchwork Fri Sep 22 13:30:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Govindapillai, Vinod" X-Patchwork-Id: 13395792 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E4E9E6FE2C for ; Fri, 22 Sep 2023 13:31:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A34C410E667; Fri, 22 Sep 2023 13:31:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F34B10E66C; Fri, 22 Sep 2023 13:30:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695389446; x=1726925446; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ExnZHFiUvvkZEaljUvD+RczBaTFBqPSQXIpBOmyUt2E=; b=SEGZnerG8oDm+Nw9lalMFTNh3k5X6UMMJHFM0R0qu7pL2Il4RKJbcNxC 9oTuvYGN/cXzQ3qQasFODiewWhq0MBbS9RLlzHnjx7aKC3XyG+50714BB jTXy5VuwFu9anL0xupXseW3OFuraCSzZ2rr8FpLDKVGm9nV8TLDK88MgM xheLYVziqgUuYL9GHZ24QdAKDgDSf8cDhe8tFMFJs+KqdQFEnj71v/f2L yw5T6Lc2TNktnyEBYADVzlMPNcYX4LN3bZKGQ+Czz2JI2Oz9oW37g+EsV kGgkpC/AI8amlACd0K7RgwAHQnI3g3no038GW+3HtxO6rnWjJvdv9NXxe g==; X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="361078362" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="361078362" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 06:30:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10841"; a="1078374389" X-IronPort-AV: E=Sophos;i="6.03,167,1694761200"; d="scan'208";a="1078374389" Received: from rvaittin-mobl.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.251.220.9]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2023 06:30:22 -0700 From: Vinod Govindapillai To: intel-xe@lists.freedesktop.org Date: Fri, 22 Sep 2023 16:30:03 +0300 Message-Id: <20230922133003.150578-3-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922133003.150578-1-vinod.govindapillai@intel.com> References: <20230922133003.150578-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH v5 2/2] drm/i915/lnl: update the supported plane formats with FBC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com, intel-gfx@lists.freedesktop.org, ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" FBC is supported with RGB32 8:8:8:8 with or without alpha Bspec: 68904, 69560 Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index aef5a4f6ad09..9b19fe018bce 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -903,6 +903,11 @@ static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) if (IS_G4X(i915)) return false; return true; + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_ABGR8888: + if (DISPLAY_VER(i915) >= 20) + return true; + fallthrough; default: return false; } @@ -1132,7 +1137,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } - if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && + if (DISPLAY_VER(i915) < 20 && + plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && fb->format->has_alpha) { plane_state->no_fbc_reason = "per-pixel alpha not supported"; return 0;