From patchwork Tue Sep 26 12:19:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13399156 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40CAEE7E62F for ; Tue, 26 Sep 2023 12:19:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7A3010E3C2; Tue, 26 Sep 2023 12:19:12 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 809F810E3B9; Tue, 26 Sep 2023 12:19:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695730750; x=1727266750; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ZM1JxfLa9X55Px8XyMwAwckX2mPOZmdLl0t/5gX7hEs=; b=WDxIOLovWQiuZhThYxsUy5lQYa4IIJx+LHQNhAb5z1mA17d44GC1ceDC Dpjy1TVTh1Jb8btTpOCQMFZa4puGXvuw/zGxD5VEB1R/uJx1+KM4twsz/ u3oz8ttE8oJ4YQrbPRMXsBk9u7Jq3+9zBDUOi7ubMStle/6f1kH4ejlt9 fjKTEFJ1WiaqUoJ2UNsMPzBx/P8T0ZgQyXxCM8BnKlPTsx6TuibrSb8wJ eHaCIQF/2OD9WmMNlSBKvoFteH9VLOLT80tNuF0gTcPJOiM4P/gMcuR4N bFDRKqA8x4YalRH10JSc18SgDYQjHr9sXVgytjC/TOobkj8P7HdAjtdn3 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="412467626" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="412467626" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="1079681330" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="1079681330" Received: from wagnert-mobl2.ger.corp.intel.com (HELO localhost) ([10.252.52.202]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:08 -0700 From: Jani Nikula To: intel-gvt-dev@lists.freedesktop.org Date: Tue, 26 Sep 2023 15:19:01 +0300 Message-Id: <20230926121904.499888-1-jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/4] drm/i915/gvt: remove unused to_gvt() and reduce includes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" gvt.h has no need to include i915_drv.h once the unused to_gvt() has been removed. Signed-off-by: Jani Nikula Reviewed-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gvt.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 53a0a42a50db..3a0624fe63bf 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -39,7 +39,7 @@ #include -#include "i915_drv.h" +#include "gt/intel_gt.h" #include "intel_gvt.h" #include "debug.h" @@ -368,11 +368,6 @@ struct intel_gvt { struct dentry *debugfs_root; }; -static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) -{ - return i915->gvt; -} - enum { /* Scheduling trigger by timer */ INTEL_GVT_REQUEST_SCHED = 0, From patchwork Tue Sep 26 12:19:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13399157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77968E7E62E for ; Tue, 26 Sep 2023 12:19:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1625910E3B9; Tue, 26 Sep 2023 12:19:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id F1CBF10E3C3; Tue, 26 Sep 2023 12:19:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695730755; x=1727266755; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6tk2fbHqdDds+SyN2CcOj7oDyp+NPP4+QGfiDm+VkEU=; b=cjLcwwio1BrjlSM3XGSlvY/ZoK/PjKf9FcsMGATtx6Huf/xFb2TGOVh4 V9Qm4TPBTATi8WCUXUIUOsWOT+gQDBjX2vKDbjgg1qVZUYEundyKG767w saA3qw7plVfnzruBdJ8zydUfyV7326DEqww0AXaZRRmMIvFhZWVz6k/Ct fXgJlhmjxfLpwJh9gB0zSkfQSeBRdQu9GHGX6GGRCs2XcN7Yyj92KTT1C vDl9sK8fMQUeCaNbN8fBVysPV3T1zS30JWGLzZvTaHAb0Ie5zh82HLnhY jh/uXsPYJjISHh70lGorRb+yryWiW1rEJj9I8FxUtcfE3CfBm2ZViSxok A==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="371884657" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="371884657" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="819012423" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="819012423" Received: from wagnert-mobl2.ger.corp.intel.com (HELO localhost) ([10.252.52.202]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:12 -0700 From: Jani Nikula To: intel-gvt-dev@lists.freedesktop.org Date: Tue, 26 Sep 2023 15:19:02 +0300 Message-Id: <20230926121904.499888-2-jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230926121904.499888-1-jani.nikula@intel.com> References: <20230926121904.499888-1-jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 2/4] drm/i915/gvt: don't include gvt.h from intel_gvt_mmio_table.h X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" intel_gvt_mmio_table.c has no need to include the massive gvt.h. Simplify. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b3c036a54529..87ecc5104fd9 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -15,8 +15,9 @@ #include "display/intel_psr_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_gt_regs.h" -#include "gvt/gvt.h" +#include "gvt/reg.h" #include "i915_drv.h" #include "i915_pvinfo.h" From patchwork Tue Sep 26 12:19:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13399158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F32BE7E62F for ; Tue, 26 Sep 2023 12:19:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC54A10E3C7; Tue, 26 Sep 2023 12:19:19 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id A962E10E3C3; Tue, 26 Sep 2023 12:19:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695730757; x=1727266757; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cc9mPRb6FxlH3GuugnfFplhL0n41m6haSldICOGULIM=; b=RVNZIvEDvEupYGQnsRpNre4QuQkRT60HN436N8h/s3MHWNPvUEqx6/oL RMoO5qbJxM1v2IltMV5IlYloGJwrIq+17lUhTbJZIk650P7BxDyFpYNtb jHUiRO11NsvtP5RZiaL96tDci1yRD4paUFP1eFWxI8c/ZubhFhRvh7PLt LakuW4QJ4VNHgJo7CzEyn+O8qLoE1ntTajWAmZ3lGQAv2jxPozbJFRvaM m4GttlswXMIkdx3mHRi/k+W41F2q5NKxvjEm5yVmIR7fr1SYrZhEr5cuV iRtLse6fOrd7BsDAZEVqK2gB5ed521D2EpcoFOMKb40qwhle86xxaZZSS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="371884680" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="371884680" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="819012447" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="819012447" Received: from wagnert-mobl2.ger.corp.intel.com (HELO localhost) ([10.252.52.202]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:16 -0700 From: Jani Nikula To: intel-gvt-dev@lists.freedesktop.org Date: Tue, 26 Sep 2023 15:19:03 +0300 Message-Id: <20230926121904.499888-3-jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230926121904.499888-1-jani.nikula@intel.com> References: <20230926121904.499888-1-jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 3/4] drm/i915/gvt: move struct engine_mmio to mmio_context.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" struct engine_mmio is not used outside of mmio_context.c. Hide it, and reduce includes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/gvt.h | 2 ++ drivers/gpu/drm/i915/gvt/mmio_context.c | 8 ++++++++ drivers/gpu/drm/i915/gvt/mmio_context.h | 10 ---------- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 3a0624fe63bf..c57aba09091f 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -60,6 +60,8 @@ #define GVT_MAX_VGPU 8 +struct engine_mmio; + /* Describe per-platform limitations. */ struct intel_gvt_device_info { u32 max_support_vgpus; diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index 490e8ae51228..273db14fd5fc 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -45,6 +45,14 @@ #define GEN9_MOCS_SIZE 64 +struct engine_mmio { + enum intel_engine_id id; + i915_reg_t reg; + u32 mask; + bool in_context; + u32 value; +}; + /* Raw offset is appened to each line for convenience. */ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = { {RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */ diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.h b/drivers/gpu/drm/i915/gvt/mmio_context.h index 9540813b88e5..a821edf574dd 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.h +++ b/drivers/gpu/drm/i915/gvt/mmio_context.h @@ -39,8 +39,6 @@ #include #include "gt/intel_engine_regs.h" -#include "gt/intel_engine_types.h" -#include "gt/intel_lrc_reg.h" struct i915_request; struct intel_context; @@ -48,14 +46,6 @@ struct intel_engine_cs; struct intel_gvt; struct intel_vgpu; -struct engine_mmio { - enum intel_engine_id id; - i915_reg_t reg; - u32 mask; - bool in_context; - u32 value; -}; - void intel_gvt_switch_mmio(struct intel_vgpu *pre, struct intel_vgpu *next, const struct intel_engine_cs *engine); From patchwork Tue Sep 26 12:19:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 13399159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFDC8E7E62F for ; Tue, 26 Sep 2023 12:19:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CF6F10E3C3; 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26 Sep 2023 05:19:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="1079681341" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="1079681341" Received: from wagnert-mobl2.ger.corp.intel.com (HELO localhost) ([10.252.52.202]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 05:19:19 -0700 From: Jani Nikula To: intel-gvt-dev@lists.freedesktop.org Date: Tue, 26 Sep 2023 15:19:04 +0300 Message-Id: <20230926121904.499888-4-jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230926121904.499888-1-jani.nikula@intel.com> References: <20230926121904.499888-1-jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 4/4] drm/i915/gvt: move structs intel_gvt_irq_info and intel_gvt_irq_map to interrupt.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Structs intel_gvt_irq_info and intel_gvt_irq_map are not used outside of interrupt.c. Hide them, and reduce includes. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/interrupt.c | 17 +++++++++++++++ drivers/gpu/drm/i915/gvt/interrupt.h | 31 ++++++---------------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c index 68eca023bbc6..de3f5903d1a7 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.c +++ b/drivers/gpu/drm/i915/gvt/interrupt.c @@ -36,6 +36,23 @@ #include "gvt.h" #include "trace.h" +struct intel_gvt_irq_info { + char *name; + i915_reg_t reg_base; + enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; + unsigned long warned; + int group; + DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); + bool has_upstream_irq; +}; + +struct intel_gvt_irq_map { + int up_irq_group; + int up_irq_bit; + int down_irq_group; + u32 down_irq_bitmask; +}; + /* common offset among interrupt control registers */ #define regbase_to_isr(base) (base) #define regbase_to_imr(base) (base + 0x4) diff --git a/drivers/gpu/drm/i915/gvt/interrupt.h b/drivers/gpu/drm/i915/gvt/interrupt.h index b62f04ab47cb..e60ad476fe60 100644 --- a/drivers/gpu/drm/i915/gvt/interrupt.h +++ b/drivers/gpu/drm/i915/gvt/interrupt.h @@ -32,10 +32,13 @@ #ifndef _GVT_INTERRUPT_H_ #define _GVT_INTERRUPT_H_ -#include -#include +#include -#include "i915_reg_defs.h" +struct intel_gvt; +struct intel_gvt_irq; +struct intel_gvt_irq_info; +struct intel_gvt_irq_map; +struct intel_vgpu; enum intel_gvt_event_type { RCS_MI_USER_INTERRUPT = 0, @@ -138,10 +141,6 @@ enum intel_gvt_event_type { INTEL_GVT_EVENT_MAX, }; -struct intel_gvt_irq; -struct intel_gvt; -struct intel_vgpu; - typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq, enum intel_gvt_event_type event, struct intel_vgpu *vgpu); @@ -175,17 +174,6 @@ enum intel_gvt_irq_type { #define INTEL_GVT_IRQ_BITWIDTH 32 -/* device specific interrupt bit definitions */ -struct intel_gvt_irq_info { - char *name; - i915_reg_t reg_base; - enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH]; - unsigned long warned; - int group; - DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH); - bool has_upstream_irq; -}; - /* per-event information */ struct intel_gvt_event_info { int bit; /* map to register bit */ @@ -194,13 +182,6 @@ struct intel_gvt_event_info { gvt_event_virt_handler_t v_handler; /* for v_event */ }; -struct intel_gvt_irq_map { - int up_irq_group; - int up_irq_bit; - int down_irq_group; - u32 down_irq_bitmask; -}; - /* structure containing device specific IRQ state */ struct intel_gvt_irq { const struct intel_gvt_irq_ops *ops;