From patchwork Wed Sep 27 15:46:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13401293 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4199E82CA5 for ; Wed, 27 Sep 2023 15:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232005AbjI0PqJ (ORCPT ); Wed, 27 Sep 2023 11:46:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231752AbjI0PqI (ORCPT ); Wed, 27 Sep 2023 11:46:08 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DC8C0272AB for ; Wed, 27 Sep 2023 08:46:06 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3231d6504e1so7605717f8f.2 for ; Wed, 27 Sep 2023 08:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695829565; x=1696434365; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=AnVyIhUQftvj++Ho5Yy6rcq1eYnc1pWWiufohODrEFE=; b=yMMij82nkhn4Th830NPLjXLNPcSSoWWVBozahIduJCUCr97mo97OVUDEnaUSIqHIn8 mB2+bKQFfdICXcxkcifGdTUhUFG0s7cTcx2viflW6pMBn2s01RlHhAGUyz8aYaQMdrXk Dwp3G9SRV+fm2cvq4NPT7yYTJaDodrhOfSBlbG95/og1E4w1Jjd48WhTGKQtgtbJ4lDF IWtElAfog+Wbm6L5MXKfCew5VKxWgJFJjm536l7oYh8Z0psCzMqJNVPCf4kcxmd/g0Q2 w55c+P+jV1i/xJOWuplzClh91O7xjX8qGtI8Fe6ugc5aFbIPicSPFQKdbU8Ja6n8+k9O T86w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695829565; x=1696434365; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=AnVyIhUQftvj++Ho5Yy6rcq1eYnc1pWWiufohODrEFE=; b=fIeDk/9+zPMBY8txlMBETfhV9p3kb3oqbovkSTBNxh1vo0ZTw3yFgInHx3WyR6J8fL JnLY8ru1X8/qvfNqIIb2jgT98BpWgBwRV9+8Z+kI4C6STUMEHlgTnDWkPkuYCnDzz5OJ KUUHMuIQarQnqRNVDVbySgz2wX9JfPq0jD48sXlFI/yycLLqODcZN/kl64OC8ZQxYe3L I66MCl67HxlzomB9u2ZBmiGP4RtcDWH1VV7KFCoN51QQxYGMi2phNoM/GN07IH4ibfQK 5YtZ+sLdCCxX+Y/2nXrDrV3E/8lmDq5XkyOyoZNhO8XQNL3zxXjM0N60FAHswiFzVscf wrVA== X-Gm-Message-State: AOJu0YwsQ6CJFQwf781XoFRVyDfa/lS079eGG3IHWnaWM56aXN6kQCnT QpnnaP+EbJld0XwevOdC+leO X-Google-Smtp-Source: AGHT+IHPVlFHZSR7dS0CVY+TjYfy0oJ3z2n7yBnN6VGdCusCelDVK4SOfVJbaXNnh5OXlhTYFnYG6A== X-Received: by 2002:a05:6000:4cd:b0:321:4df5:b85e with SMTP id h13-20020a05600004cd00b003214df5b85emr2167996wri.26.1695829565184; Wed, 27 Sep 2023 08:46:05 -0700 (PDT) Received: from thinkpad.fritz.box ([2a02:2454:9d09:3f00:b024:394e:56d7:d8b4]) by smtp.gmail.com with ESMTPSA id s28-20020adfa29c000000b003232f167df5sm6925852wra.108.2023.09.27.08.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 08:46:04 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, abel.vesa@linaro.org, Manivannan Sadhasivam Subject: [PATCH v3 1/3] PCI: qcom: Make use of PCIE_SPEED2MBS_ENC() macro for encoding link speed Date: Wed, 27 Sep 2023 17:46:01 +0200 Message-Id: <20230927154603.172049-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Instead of hardcoding the link speed in MBps, let's make use of the existing PCIE_SPEED2MBS_ENC() macro that does the encoding of the link speed for us. Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do the conversion to ICC speed. This eliminates the need for a switch case in qcom_pcie_icc_update() and also works for future Gen speeds without any code modifications. Suggested-by: Bjorn Helgaas Signed-off-by: Manivannan Sadhasivam --- Changes in v3: - Used Mbps_to_icc() macro and changed the commit message a bit Changes in v2: - Switched to QCOM_PCIE_LINK_SPEED_TO_BW() macro as per Bjorn's suggestion https://lore.kernel.org/linux-pci/20230924160713.217086-1-manivannan.sadhasivam@linaro.org/ drivers/pci/controller/dwc/pcie-qcom.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e2f29404c84e..367acb419a2b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -148,6 +148,9 @@ #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ + Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) + #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; @@ -1347,7 +1350,7 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) * Set an initial peak bandwidth corresponding to single-lane Gen 1 * for the pcie-mem path. */ - ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250)); + ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); if (ret) { dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); @@ -1360,7 +1363,7 @@ static int qcom_pcie_icc_init(struct qcom_pcie *pcie) static void qcom_pcie_icc_update(struct qcom_pcie *pcie) { struct dw_pcie *pci = pcie->pci; - u32 offset, status, bw; + u32 offset, status; int speed, width; int ret; @@ -1377,22 +1380,7 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - switch (speed) { - case 1: - bw = MBps_to_icc(250); - break; - case 2: - bw = MBps_to_icc(500); - break; - default: - WARN_ON_ONCE(1); - fallthrough; - case 3: - bw = MBps_to_icc(985); - break; - } - - ret = icc_set_bw(pcie->icc_mem, 0, width * bw); + ret = icc_set_bw(pcie->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) { dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); From patchwork Wed Sep 27 15:46:02 2023 Content-Type: text/plain; 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Also, let's Wrap it with QCOM_PCIE_LINK_SPEED_TO_BW() macro to do the conversion to ICC speed. This eliminates the need for a switch case in qcom_pcie_icc_update() and also works for future Gen speeds without any code modifications. Suggested-by: Bjorn Helgaas Signed-off-by: Manivannan Sadhasivam --- Changes in v3: - New patch drivers/pci/controller/dwc/pcie-qcom-ep.c | 31 +++++------------------ 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 8bd8107690a6..32c8d9e37876 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -23,6 +23,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" /* PARF registers */ @@ -135,10 +136,8 @@ #define CORE_RESET_TIME_US_MAX 1005 #define WAKE_DELAY_US 2000 /* 2 ms */ -#define PCIE_GEN1_BW_MBPS 250 -#define PCIE_GEN2_BW_MBPS 500 -#define PCIE_GEN3_BW_MBPS 985 -#define PCIE_GEN4_BW_MBPS 1969 +#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ + Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) #define to_pcie_ep(x) dev_get_drvdata((x)->dev) @@ -266,7 +265,7 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; - u32 offset, status, bw; + u32 offset, status; int speed, width; int ret; @@ -279,25 +278,7 @@ static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); - switch (speed) { - case 1: - bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); - break; - case 2: - bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); - break; - case 3: - bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); - break; - default: - dev_warn(pci->dev, "using default GEN4 bandwidth\n"); - fallthrough; - case 4: - bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); - break; - } - - ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); if (ret) dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", ret); @@ -335,7 +316,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) * Set an initial peak bandwidth corresponding to single-lane Gen 1 * for the pcie-mem path. */ - ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); 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Wed, 27 Sep 2023 08:46:06 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: andersson@kernel.org, konrad.dybcio@linaro.org, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, abel.vesa@linaro.org, Manivannan Sadhasivam , Vidya Sagar Subject: [PATCH v3 3/3] PCI: tegra194: Use Mbps_to_icc() macro for setting icc speed Date: Wed, 27 Sep 2023 17:46:03 +0200 Message-Id: <20230927154603.172049-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230927154603.172049-1-manivannan.sadhasivam@linaro.org> References: <20230927154603.172049-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PCIe speed returned by the PCIE_SPEED2MBS_ENC() macro is in Mbps. So instead of converting it to MBps explicitly and using the MBps_to_icc() macro, let's use the Mbps_to_icc() macro to pass the value directly. Cc: Vidya Sagar Signed-off-by: Manivannan Sadhasivam --- Changes in v3: - New patch drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 4bba31502ce1..5feac690e127 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -321,9 +321,9 @@ static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie) speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val); width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val); - val = width * (PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]) / BITS_PER_BYTE); + val = width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]); - if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0)) + if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) dev_err(pcie->dev, "can't set bw[%u]\n", val); if (speed >= ARRAY_SIZE(pcie_gen_freq))