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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Add L2 cache node for RZ/Five SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index 6ec1c6f9a403..c8d63a8f7d86 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -29,6 +29,7 @@ cpu0: cpu@0 { i-cache-line-size = <0x40>; d-cache-size = <0x8000>; d-cache-line-size = <0x40>; + next-level-cache = <&l2cache>; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; operating-points-v2 = <&cluster0_opp>; @@ -56,4 +57,15 @@ plic: interrupt-controller@12c00000 { resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; + + l2cache: cache-controller@13400000 { + compatible = "andestech,ax45mp-cache", "cache"; + reg = <0x0 0x13400000 0x0 0x100000>; + interrupts = ; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-unified; + cache-level = <2>; + }; }; From patchwork Fri Sep 29 00:07:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13403603 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F02B5E743D0 for ; Fri, 29 Sep 2023 00:07:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 28 Sep 2023 17:07:40 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:fe98:5e2c:1821:4cb6]) by smtp.gmail.com with ESMTPSA id y20-20020a7bcd94000000b004030e8ff964sm245667wmj.34.2023.09.28.17.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 17:07:39 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [PATCH 2/5] riscv: dts: renesas: r9a07g043f: Add dma-noncoherent property Date: Fri, 29 Sep 2023 01:07:01 +0100 Message-Id: <20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_170742_928058_525BCAB9 X-CRM114-Status: UNSURE ( 8.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent property to RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index c8d63a8f7d86..b0796015e36b 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -43,6 +43,7 @@ cpu0_intc: interrupt-controller { }; &soc { + dma-noncoherent; interrupt-parent = <&plic>; plic: interrupt-controller@12c00000 { From patchwork Fri Sep 29 00:07:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13403601 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B8FFE743D6 for ; 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Thu, 28 Sep 2023 17:07:41 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [PATCH 3/5] riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled Date: Fri, 29 Sep 2023 01:07:02 +0100 Message-Id: <20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_170744_295634_BC0D2A34 X-CRM114-Status: GOOD ( 11.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Now that noncoherent dma support is added for RZ/Five SoC enable the IP blocks which were disabled on RZ/Five SMARC. Now with this patch we get support for the below peripherals: * DMAC * SDHI * USB * RSPI * SSI Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzfive-smarc-som.dtsi | 23 -------- arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 ------------------- 2 files changed, 79 deletions(-) diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index c62debc7ca7e..433ab5c6a626 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -7,25 +7,8 @@ #include -/ { - aliases { - /delete-property/ ethernet0; - /delete-property/ ethernet1; - }; - - chosen { - bootargs = "ignore_loglevel"; - }; -}; - -&dmac { - status = "disabled"; -}; - #if (!SW_ET0_EN_N) ð0 { - status = "disabled"; - phy0: ethernet-phy@7 { /delete-property/ interrupt-parent; /delete-property/ interrupts; @@ -34,14 +17,8 @@ phy0: ethernet-phy@7 { #endif ð1 { - status = "disabled"; - phy1: ethernet-phy@7 { /delete-property/ interrupt-parent; /delete-property/ interrupts; }; }; - -&sdhi0 { - status = "disabled"; -}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi index c07a487c4e5a..a8573fdfd8b1 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -6,59 +6,3 @@ */ #include - -&ehci0 { - status = "disabled"; -}; - -&ehci1 { - status = "disabled"; -}; - -&hsusb { - status = "disabled"; -}; - -&ohci0 { - status = "disabled"; -}; - -&ohci1 { - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - -&sdhi1 { - status = "disabled"; -}; - -&snd_rzg2l { - status = "disabled"; -}; - -&spi1 { - status = "disabled"; -}; - -&ssi1 { - status = "disabled"; -}; - -&usb0_vbus_otg { - status = "disabled"; -}; - -&usb2_phy0 { - status = "disabled"; -}; - -&usb2_phy1 { - status = "disabled"; -}; - -&vccq_sdhi1 { - status = "disabled"; -}; From patchwork Fri Sep 29 00:07:03 2023 Content-Type: text/plain; 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Thu, 28 Sep 2023 17:07:42 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:fe98:5e2c:1821:4cb6]) by smtp.gmail.com with ESMTPSA id y20-20020a7bcd94000000b004030e8ff964sm245667wmj.34.2023.09.28.17.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 17:07:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [PATCH 4/5] riscv: dts: renesas: rzfive-smarc: Drop dma properties from SSI1 node Date: Fri, 29 Sep 2023 01:07:03 +0100 Message-Id: <20230929000704.53217-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_170744_722367_298131CC X-CRM114-Status: UNSURE ( 8.91 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar With DMA enabled audio capture/playback has some echo noise. So for now switch to PIO mode until fixed. Signed-off-by: Lad Prabhakar --- arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi index a8573fdfd8b1..85f96e24a96e 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -6,3 +6,8 @@ */ #include + +&ssi1 { + /delete-property/ dmas; + /delete-property/ dma-names; +}; From patchwork Fri Sep 29 00:07:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13403602 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DBB4E743D4 for ; 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Thu, 28 Sep 2023 17:07:43 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Rob Herring , Krzysztof Kozlowski , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Biju Das , Prabhakar , Lad Prabhakar Subject: [PATCH 5/5] riscv: configs: defconfig: Enable configs required for RZ/Five SoC Date: Fri, 29 Sep 2023 01:07:04 +0100 Message-Id: <20230929000704.53217-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20230929000704.53217-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230928_170745_352391_1BD39256 X-CRM114-Status: UNSURE ( 9.85 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Lad Prabhakar Enable the configs required by the below IP blocks which are present on RZ/Five SoC: * ADC * CANFD * DMAC * eMMC/SDHI * OSTM * RAVB (+ Micrel PHY) * RIIC * RSPI * SSI (Sound+WM8978 codec) * Thermal * USB (PHY/RESET/OTG) Along with the above some core configs are enabled too, -> CPU frequency scaling as RZ/Five does support this. -> MTD is enabled as RSPI can be connected to flash chips -> Enabled I2C chardev so that it enables userspace to read/write i2c devices (similar to arm64) -> Thermal configs as RZ/Five SoC does have thermal unit -> GPIO regulator as we might have IP blocks for which voltage levels are controlled by GPIOs -> OTG configs as RZ/Five USB can support host/function -> Gadget configs so that we can test USB function (as done in arm64 all the gadget configs are enabled) Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- arch/riscv/configs/defconfig | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..1e81c865a271 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -36,6 +36,13 @@ CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_PM=y CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPUFREQ_DT=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m CONFIG_ACPI=y @@ -94,6 +101,7 @@ CONFIG_NETLINK_DIAG=y CONFIG_CGROUP_NET_PRIO=y CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y +CONFIG_CAN=m CONFIG_PCI=y CONFIG_PCIEPORTBUS=y CONFIG_PCI_HOST_GENERIC=y @@ -101,6 +109,11 @@ CONFIG_PCIE_XILINX=y CONFIG_PCIE_FU740=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_SPI_NOR=y CONFIG_BLK_DEV_LOOP=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=m @@ -123,8 +136,11 @@ CONFIG_VIRTIO_NET=y CONFIG_MACB=y CONFIG_E1000E=y CONFIG_R8169=y +CONFIG_RAVB=y CONFIG_STMMAC_ETH=m +CONFIG_MICREL_PHY=y CONFIG_MICROSEMI_PHY=y +CONFIG_CAN_RCAR_CANFD=m CONFIG_INPUT_MOUSEDEV=y CONFIG_KEYBOARD_SUN4I_LRADC=m CONFIG_SERIAL_8250=y @@ -135,16 +151,24 @@ CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C_CHARDEV=m CONFIG_I2C_MV64XXX=m +CONFIG_I2C_RIIC=y CONFIG_SPI=y +CONFIG_SPI_RSPI=m CONFIG_SPI_SIFIVE=y CONFIG_SPI_SUN6I=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SIFIVE=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_RZG2L_THERMAL=y CONFIG_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=y +CONFIG_RENESAS_RZG2LWDT=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y CONFIG_DRM=m CONFIG_DRM_RADEON=m CONFIG_DRM_NOUVEAU=m @@ -152,39 +176,67 @@ CONFIG_DRM_SUN4I=m CONFIG_DRM_VIRTIO_GPU=m CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_RZ=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SIMPLE_CARD=m CONFIG_USB=y +CONFIG_USB_OTG=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_RENESAS_USBHS=m CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y CONFIG_USB_MUSB_HDRC=m CONFIG_USB_MUSB_SUNXI=m CONFIG_NOP_USB_XCEIV=m +CONFIG_USB_GADGET=y +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SPI=y +CONFIG_MMC_SDHI=y CONFIG_MMC_SUNXI=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SUN6I=y CONFIG_DMADEVICES=y CONFIG_DMA_SUN6I=m +CONFIG_RZ_DMAC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y CONFIG_VIRTIO_MMIO=y +CONFIG_RENESAS_OSTM=y CONFIG_SUN8I_DE2_CCU=m CONFIG_SUN50I_IOMMU=y CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_VIRTIO=y CONFIG_ARCH_R9A07G043=y +CONFIG_IIO=y +CONFIG_RZG2L_ADC=m +CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_PHY_SUN4I_USB=m +CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_LIBNVDIMM=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_EXT4_FS=y