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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id ck17-20020a170906c45100b00982a92a849asm12289551ejb.91.2023.09.29.05.51.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 05:51:24 -0700 (PDT) From: Luca Weiss Date: Fri, 29 Sep 2023 14:51:22 +0200 Subject: [PATCH v2] arm64: dts: qcom: sc7280: Add ports subnodes in usb/dp qmpphy node MIME-Version: 1.0 Message-Id: <20230929-sc7280-qmpphy-ports-v2-1-aae7e9c286b0@fairphone.com> X-B4-Tracking: v=1; b=H4sIAEnIFmUC/32NQQ6DIBBFr2Jm3WlgtKF25T0aFwShzEKhYEiN8 e6lHqDL95L//g7ZJrYZHs0OyRbOHJYKdGnAeL28LPJUGUhQK3rqMRtFd4HvOUa/YQxpzUhCu6k jSZ0SUJcxWcefs/ocK3vOa0jbeVLkz/7vFYkS1a0lI2WvWu0GpzlFHxZ7NWGG8TiOLxHJGyO6A AAA To: cros-qcom-dts-watchers@chromium.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the USB3+DP Combo QMP PHY port subnodes to facilitate the description of the connection between the hardware blocks. Put it in the SoC DTSI to avoid duplication in the device DTs. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss --- Changes in v2: - Update commit message after feedback from Konrad - Pick up tags - Link to v1: https://lore.kernel.org/r/20230929-sc7280-qmpphy-ports-v1-1-7532c11973af@fairphone.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) --- base-commit: df964ce9ef9fea10cf131bf6bad8658fde7956f6 change-id: 20230929-sc7280-qmpphy-ports-20afd4212470 Best regards, diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 66f1eb83cca7..4e34d00e246b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3399,6 +3399,32 @@ usb_1_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_2: usb@8cf8800 {