From patchwork Mon Oct 2 18:08:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Wolsieffer X-Patchwork-Id: 13406509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99434E74902 for ; Mon, 2 Oct 2023 18:10:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 02 Oct 2023 11:09:30 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id w15-20020ae9e50f000000b0077423f849c3sm7390255qkf.24.2023.10.02.11.09.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:09:29 -0700 (PDT) From: Ben Wolsieffer To: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Ben Wolsieffer Subject: [PATCH 1/2] clk: stm32: initialize syscon after clocks are registered Date: Mon, 2 Oct 2023 14:08:53 -0400 Message-ID: <20231002180854.1603452-2-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231002180854.1603452-1-ben.wolsieffer@hefring.com> References: <20231002180854.1603452-1-ben.wolsieffer@hefring.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_110931_035667_02B681E2 X-CRM114-Status: GOOD ( 21.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The stm32-power-config syscon (PWR peripheral) is used in this driver and the STM32 RTC driver to enable write access to backup domain registers. The syscon's clock has a gate controlled by this clock driver, but this clock is currently not registered in the device tree. This only happens to work currently because all relevant clock setup and RTC initialization happens before clk_disabled_unused(). After this point, all syscon register writes are ignored. If we simply add the syscon clock in the device tree, we end up with a circular dependency because the clock has not been registered at the point this driver requests the syscon. This patch avoids this circular dependency by moving the syscon lookup after the clocks are registered. This does appear to create a possible race condition where someone could attempt to perform an operation on a backup domain clock before the syscon has been initialized. This would result in the operation having no effect because backup domain writes could not be enabled. I'm not sure if this is a problem or if there is a way to avoid it. Signed-off-by: Ben Wolsieffer --- drivers/clk/clk-stm32f4.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 07c13ebe327d..a88e762d2b5e 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -1697,12 +1697,6 @@ static void __init stm32f4_rcc_init(struct device_node *np) return; } - pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); - if (IS_ERR(pdrm)) { - pdrm = NULL; - pr_warn("%s: Unable to get syscfg\n", __func__); - } - match = of_match_node(stm32f4_of_match, np); if (WARN_ON(!match)) return; @@ -1894,6 +1888,12 @@ static void __init stm32f4_rcc_init(struct device_node *np) of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL); + pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); + if (IS_ERR(pdrm)) { + pdrm = NULL; + pr_warn("%s: Unable to get syscfg\n", __func__); + } + return; fail: kfree(clks); From patchwork Mon Oct 2 18:08:54 2023 Content-Type: text/plain; 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Mon, 02 Oct 2023 11:09:31 -0700 (PDT) Received: from localhost.localdomain ([50.212.55.89]) by smtp.gmail.com with ESMTPSA id w15-20020ae9e50f000000b0077423f849c3sm7390255qkf.24.2023.10.02.11.09.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:09:30 -0700 (PDT) From: Ben Wolsieffer To: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Michael Turquette , Stephen Boyd , Ben Wolsieffer Subject: [PATCH 2/2] ARM: dts: stm32: add pwrcfg clock for stm32f4/7 Date: Mon, 2 Oct 2023 14:08:54 -0400 Message-ID: <20231002180854.1603452-3-ben.wolsieffer@hefring.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231002180854.1603452-1-ben.wolsieffer@hefring.com> References: <20231002180854.1603452-1-ben.wolsieffer@hefring.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231002_110933_488219_05D8448D X-CRM114-Status: GOOD ( 12.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the circular dependency between syscon and clock initialization has been resolved, we can add the clock that drives the pwrcfg syscon to the device tree. Signed-off-by: Ben Wolsieffer --- arch/arm/boot/dts/st/stm32f429.dtsi | 1 + arch/arm/boot/dts/st/stm32f746.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi index 8efcda9ef8ae..7c9a9133cc86 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -665,6 +665,7 @@ spi6: spi@40015400 { pwrcfg: power-config@40007000 { compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(PWR)>; }; ltdc: display-controller@40016800 { diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index d1802efd067c..cc8177466a51 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -510,6 +510,7 @@ pwm { pwrcfg: power-config@40007000 { compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(PWR)>; }; crc: crc@40023000 {