From patchwork Wed Oct 4 06:35:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 13408460 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 982B7E8FDDD for ; Wed, 4 Oct 2023 09:00:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pfpKAsd3QRuv4o83ZEyhcirVswt4Kav11x+Ehd0es1E=; b=hM7Iuq1UfcwYEX 2wgzywk/fQ6HxcCTJG5plarf/cQF1Scpa3P2Tv9yksuFk/lWwMwC595vZUK0p6mbd6QmpOB/DQZIR PKE5fgw336FW2Pp6n5iUbQ+D9pkvDzDiIOV2vf6+C014Yk/8RXJWn7zqJnWOm0VRP7PzVW9ulzvSR lPjX6jMXpvfzm6cN4XeLgvSVix7hCl3Zj09B1U4uaiqeFc7InTlYyq87ZjkDDOXqy7aAGVbPqfpyX 7xDjspXlU6yroKVi1CS2ojr4r8ALMw3q8QKSJB3i7Mun/8XiiVb1Z5LkQ17ULCK9NWjOlk0PkEP+/ AlyeFQtItLXXwfFqm9aw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qnxkB-00GxPO-0y; Wed, 04 Oct 2023 09:00:35 +0000 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qnvVo-00GR86-1x for linux-arm-kernel@lists.infradead.org; Wed, 04 Oct 2023 06:37:40 +0000 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-9ae7383b7ecso127380366b.0 for ; Tue, 03 Oct 2023 23:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401453; x=1697006253; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OYKY9mFmL0eJ6Vii+DUBC2q4iHATJVweYT3mzBHdRNo=; b=W7xbfjmtVgNZvtRQm9/+GjPjznKyT5EGwUS145ksMMRJ10Ym/nGzKsB6jk1qt8GjKc MddfrjzmLueS0ZfSIMr6CC+xVj9CsQnz3ydvDL3SpnaJWpv9fpLPh5OzIsmwyfDPyAUk blywMmn/xB85fVFuw59ecBgQbfDTxJKy6EoALcp9MUAKaK4KaPrH839Al8P5ofouAEt3 Izob4Ts7r26j7bffR4mVEpJDxNXkKbkXSSWOuZAK1n6KN9eyZgGpOtBEW5UFsSFeRVdw 2tjyB+sGp4EOGlB/I1F8Xv+BZxuXL0sCahpq+JNnFk6mGOxwdQMlFhQu3EyF7gjojV2m qz4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401453; x=1697006253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OYKY9mFmL0eJ6Vii+DUBC2q4iHATJVweYT3mzBHdRNo=; b=sRdbbRSExAc/bb2Fmhmrs3z9NiRCLITL8DWmUvK32Xpbsx2HofpaKCn9pW4u6Vocyt ZUkuJUcF3UU4dI/OhncY/fM2OXNSaEWy6XTk3DvwxtDDX7L7JJ786IC/oWxBn/qiw+Ef 8fcuSSpQJinxdzFXlPvZoB6VELOAi2AUiFIXkrYFHmgmA+RT8lAFRWy7FE58AZYCHj1R 85bowum7gEFUMn5EEpzDfLCpexafUXo/NB7ngBQ06gLfBxhiUgzTYD7g97oVfPBux/RU PlASf1+a8zXv4mTsdsHeHQv9u2UtIOI5ByTvnYzipGjlt04GFbVdY0Amcy6G4nnAe/F7 goAQ== X-Gm-Message-State: AOJu0YzWQqixmWon41x0fB3+pkJuDm5ULn7IIBCjDfk2Llmku6xaQ27H rW0vXgMLw77k3Vg/L3LVzmeqfg== X-Google-Smtp-Source: AGHT+IGpHgyVPc6kOSyP5QaEmukyp94bUYaLYHUd5j+0jlgaXbkILR3X0vFPfO0AgXq0gwSWrNxMYA== X-Received: by 2002:a17:906:5e:b0:9a9:f0e6:904e with SMTP id 30-20020a170906005e00b009a9f0e6904emr1201861ejg.16.1696401452905; Tue, 03 Oct 2023 23:37:32 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:32 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/4] dt-bindings: clock: si5351: convert to yaml Date: Wed, 4 Oct 2023 08:35:27 +0200 Message-ID: <20231004063712.3348978-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231003_233736_643557_718B7220 X-CRM114-Status: GOOD ( 29.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Alvin Šipraga The following additional properties are described: - clock-names - clock-frequency of the clkout child nodes In order to suppress warnings from the DT schema validator, the clkout child nodes are prescribed names clkout@[0-7] rather than clkout[0-7]. The latter form is still admissible but the example has been changed to use the former. The example is refined as follows: - correct the usage of property pll-master -> silabs,pll-master - give an example of how the silabs,pll-reset property can be used I made myself maintainer of the file as I cannot presume that anybody else wants the responsibility. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.txt | 126 --------- .../bindings/clock/silabs,si5351.yaml | 253 ++++++++++++++++++ 2 files changed, 253 insertions(+), 126 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index bfda6af76bee..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml new file mode 100644 index 000000000000..400c8cec2a3a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5351A/B/C programmable I2C clock generators + +description: | + The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to + 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 + output clocks are accessible. The internal structure of the clock generators + can be found in [1]. + + [1] Si5351A/B/C Data Sheet + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf + +maintainers: + - Alvin Šipraga + +properties: + compatible: + enum: + - silabs,si5351a # Si5351A, 20-QFN package + - silabs,si5351a-msop # Si5351A, 10-MSOP package + - silabs,si5351b # Si5351B, 20-QFN package + - silabs,si5351c # Si5351C, 20-QFN package + + reg: + enum: + - 0x60 + - 0x61 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + + silabs,pll-source: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of cell pairs containing a PLL index and its source. Allows to + overwrite clock source of the internal PLLs. + minItems: 1 + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). + enum: [ 0, 1 ] + +patternProperties: + "^clkout@[0-7]$": + type: object + + properties: + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Clock output number. + + clock-frequency: true + + silabs,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Source clock of the this output's divider stage. + + 0 - use multisynth N for this output, where N is the output number + 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4 + (otherwise) for this output + 2 - use XTAL for this output + 3 - use CLKIN for this output (Si5351C only) + + silabs,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8 ] + description: Output drive strength in mA. + + silabs,multisynth-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: | + Source PLL A (0) or B (1) for the corresponding multisynth divider. + + silabs,pll-master: + type: boolean + description: | + The frequency of the source PLL is allowed to be changed by the + multisynth when setting the rate of this clock output. + + silabs,pll-reset: + type: boolean + description: Reset the source PLL when enabling this clock output. + + silabs,disable-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + Clock output disable state. The state can be one of: + + 0 - clock output is driven LOW when disabled + 1 - clock output is driven HIGH when disabled + 2 - clock output is FLOATING (HIGH-Z) when disabled + 3 - clock output is never disabled + + allOf: + - if: + properties: + compatible: + contains: + const: silabs,si5351a-msop + then: + properties: + reg: + minimum: 0 + maximum: 2 + else: + properties: + reg: + minimum: 0 + maximum: 7 + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + silabs,clock-source: + enum: [ 0, 1, 2, 3 ] + else: + properties: + silabs,clock-source: + enum: [ 0, 1, 2 ] + required: + - reg + + additionalProperties: false + +allOf: + - $ref: /schemas/clock/clock.yaml + - if: + properties: + compatible: + contains: + enum: + - silabs,si5351a + - silabs,si5351a-msop + - silabs,si5351b + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: xtal + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: xtal + - const: clkin + +required: + - reg + - "#address-cells" + - "#size-cells" + - "#clock-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* Connect XTAL input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* Use XTAL input as source of PLL0 and PLL1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* + * Overwrite CLK0 configuration with: + * - 8 mA output drive strength + * - PLL0 as clock source of multisynth 0 + * - Multisynth 0 as clock source of output divider + * - Multisynth 0 can change PLL0 + * - Set initial clock frequency of 74.25MHz + */ + clkout@0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * Overwrite CLK1 configuration with: + * - 4 mA output drive strength + * - PLL1 as clock source of multisynth 1 + * - Multisynth 1 as clock source of output divider + * - Multisynth 1 can change PLL1 + * - Reset PLL1 when enabling this clock output + */ + clkout@1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + silabs,pll-reset; + }; + + /* + * Overwrite CLK2 configuration with: + * - XTAL as clock source of output divider + */ + clkout@2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; + }; From patchwork Wed Oct 4 06:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 13408294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9174CE8FDD1 for ; Wed, 4 Oct 2023 07:45:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ATrBXuslbRbq7Of8cdPsNHI071PKNXTkGekF3dmH5lw=; b=4ad8fImO+x8+FV 2Rkhm/3qCXWLMzcnONQmEN00Yi5VMqRghA1m58zqzhpw9JVDnDe5GKIV38mz8KZEoijBPhP9ElaNe vXmCNHdZ+cI33s48gqAn5FbV24dO3XWnKWxrPx2nx7lfoC4d+b3sjt62a/DpvdJH/STixlfSnOcrV WijdmeBd89/z7SpJIdhKhOtuPWLnVV7nZGQe3hvB9bFGFQJ8Xw2xzXerEMYH3Wy160/x/sBd84jh2 az14005/oJYoQ5EDrkScdxuwskbfjWi/KCLJ4GzRSXjrJX5r0k5bk1C0EzQNFwojv87SPwxu3Pzx5 AkeCTZCA5UwdDYFXnwbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qnwZZ-00GfCs-0Z; Wed, 04 Oct 2023 07:45:33 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qnvVv-00GRCO-2j for linux-arm-kernel@bombadil.infradead.org; Wed, 04 Oct 2023 06:37:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; b=A5Q2PQFhVQWOkYhM8kSmsme/BF hWrrJtTUrGM/Se6JpBNsL1DyMP4/fVhzq6GNZDvKdsaOKEJCG5fF1H5/2KTR0YeNUJ/9gI1/7sROB CvPh97PFdqsVcUUjGxXasxSVnUMaoaSSHk9rpgg2FiAgdzzvDBSJqNivCDShnypnOdSY2J8ksW9QJ 7TL8KO0TWmj9+5Sb5nQIcW2wK71UE3EO4ij0cRfiT36qgq2MpJPJpw9SL51HwBTU4TJ13l7de7xI7 uKRGgWw/V/RnyArZ1d1DFA7Vfgj12HYcIdGKOKF0Fy3PDnyHgGOHsKd0NxuhgoUQR6+ytF0/af8v0 /Xf8eI2A==; Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by desiato.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qnvVp-00AYAy-2K for linux-arm-kernel@lists.infradead.org; Wed, 04 Oct 2023 06:37:42 +0000 Received: by mail-ej1-x632.google.com with SMTP id a640c23a62f3a-99c1c66876aso316737666b.2 for ; Tue, 03 Oct 2023 23:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401455; x=1697006255; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; b=ljnXblch4LlLgcz0q2Y4TphI2mTPXK9CFyhIkaNoTaxeBWdpqGTotCl8qS+nLsveH6 pd2CfeH8v47IAHQM1ecn3m1d8C9c3VYVA8LQbxV60NnLk4tM3qHmLLE6aljuYCOkabUJ dDC0DkHnDaZwzdUdGyJ41Y2wIKoHKR4Ut5boU2UXmv/YJlev049YTxmLzdfORJ6LVjLm KaSTaNBKSeOf3UvksXDu1TAy3PvdCJH/kqs3QK8+F0JhG6NZH0FJ8U62vn5FJIEKIL8U bUPIagabqej1hUrLK8T2FNOgrqYY+4lZJvyfTGBrbnuJNeBtLH+MscOJhZhR82znQnxV C8AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401455; x=1697006255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; b=EmzU+587TrvYkRcPm3Bll7NXNcjNaSRlPkCcGiz/LhkZpqWYXst8ni1Lrhl/gPLtx0 GuhTgRCEdx1rU8su0pJhwn8XndYW8zlQ6GPKh/UtTEXKZMzWZ4YpFVkxh4osnrlyuWsW Tls8ZPOieT6ZLjTZIcrkNkNpzKi5UpTeQC16KI+k8gZTeTWAOgB+Aea41/haDiSGAWmD K5CR+w/zLQMcdeVvmkyZndwwVnSCt6fewL/UO5kM6KZ4vlf+4HhqyjiMsWJwhkO2uu/b tvCwR9u2ianP/nhBMhVuUi/FDjx78SJJQPJgkHjf7XhcvHCzAf+Wt01VfHyqfHINopyS r0kQ== X-Gm-Message-State: AOJu0YyxETjuuLNaP6p9tsT2JDu9kXir8irlK6Jl02sNCaeuCBat1UjG suvqbxbJX1KdN+aRSreyRG2bVQ== X-Google-Smtp-Source: AGHT+IGLapIb4nj4ZcigiKiclJwBDD7Fs6WqXJRbY2zCs9wk0EgcSlXwJuT4bHJBOsXGkpLAkKWNew== X-Received: by 2002:a17:907:d047:b0:9ae:6744:4591 with SMTP id vb7-20020a170907d04700b009ae67444591mr1105255ejc.43.1696401455571; Tue, 03 Oct 2023 23:37:35 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:35 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/4] ARM: dts: dove-cubox: fix si5351 node names Date: Wed, 4 Oct 2023 08:35:28 +0200 Message-ID: <20231004063712.3348978-3-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231004_073739_520315_C76E2F86 X-CRM114-Status: GOOD ( 14.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Alvin Šipraga Correct the device tree to conform with the bindings. The node name and index should be separated with an @. Suggested-by: Rob Herring Signed-off-by: Alvin Šipraga --- arch/arm/boot/dts/marvell/dove-cubox.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/marvell/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts index bfde99486a87..bcaaf8320c45 100644 --- a/arch/arm/boot/dts/marvell/dove-cubox.dts +++ b/arch/arm/boot/dts/marvell/dove-cubox.dts @@ -101,7 +101,7 @@ si5351: clock-generator@60 { /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; - clkout0 { + clkout@0 { reg = <0>; silabs,drive-strength = <8>; silabs,multisynth-source = <0>; @@ -109,7 +109,7 @@ clkout0 { silabs,pll-master; }; - clkout2 { + clkout@2 { reg = <2>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; From patchwork Wed Oct 4 06:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 13408459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0876E8FDDB for ; Wed, 4 Oct 2023 09:00:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Wats60MdbUYsmZZALtfUNOj9lOdlwxkFTiDJC9oYMDI=; b=oNJFpJHpMclOLG e5TVH50GfDGSG/+ddb1yfyMd6/euctDoD4cmpOxxZoKmlqlx6Btm63DraVbff2AH8qU/nLIzBYmlW 72il7qPcQ76v5oBitNH6cjDwVUueBaQgC4NryBB4xwUrwxW0sx4VwAJKjry9o5hkSPRnSBAeUCwM+ X4zKqv9CH82m+q1vlGHEOPaq5+9nx8xTr4eUKlnmF/0Zlfzm7Rn1w42lM13SJaJYs8CPYF/iwcAK3 vCU9NgsCbqfHi/GixnkP3efRMdlgCSJEG6ZE4ngc+9A5kt1x4TAgq3JV2kEyZxgEe2rpnbYAtuFos sOsvIc4Bq1f55Biw/Qzg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qnxkB-00GxPf-2Z; Wed, 04 Oct 2023 09:00:35 +0000 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qnvVt-00GR9o-27 for linux-arm-kernel@lists.infradead.org; Wed, 04 Oct 2023 06:37:43 +0000 Received: by mail-ej1-x631.google.com with SMTP id a640c23a62f3a-9a58dbd5daeso310501566b.2 for ; Tue, 03 Oct 2023 23:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401458; x=1697006258; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+QGSDNn6mvgk3D6FylGr3G9S7gB7eM4JL0YqBrEuXRo=; b=amTGs0NhxUu64dHma8S6SPkvL/gCYl8bKd0tvDykby98zXo40xUOkmNPpH+DytVmZB YIttrpxMDCNyx9SVkB3gHzQmy2UpoJ50mj52S3bn4i/W4/5SbRdy/0pLqsTknuYweIJz TV5nn4I9WNPgbnQzKJ93zmeKU5FM33Lclg01neICGoambiayarH7OEGRQtP/ZTl85bmL ln8MvCO8anHzVdDbP+Zgm6cJs/rTwTc+MYdsK4DlV+VgGrRzO/dhcMDR7xNUmgWJJcJW 1sCG8T/ldkz7KbZHVM+D27NzLkC0ziF+wgFjmmKXubHKjmx1+hv/iFYBtOwq9Gyy9K+3 1YRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401458; x=1697006258; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+QGSDNn6mvgk3D6FylGr3G9S7gB7eM4JL0YqBrEuXRo=; b=ioAoYHcMJSoQrM3ErUARbYk2qwTKaTpUYXzJyUgPEqoCyvyX8BqBLktvOzYEAx05AT JQRdHubtWZI30PtsBi/huYFf06skyChenAcKJ7eDFDTqxxD2dhhbA/jHiuOEKwCtz1+7 XUF2UmGyPR3bWnX9OEya/4RU8I159ccYvhK4hHrVjDpGZYp8aJvDMcxcJZMgqBDmUv/6 1sNfryuAmyl2I+r7/IUPK3b3Zqufcofv7x2FbTdSo7wiJcuGruLDWs0wAHNpi/zZtGWc vlEtXf3diaLakZgsOgiO+al68DqZnlkfPpw6b32Su8lR6d+klcLPFvBqRMwuf9KmnCSx alTA== X-Gm-Message-State: AOJu0YzNMcyuLr+nJr6a4WC6S851aKd/z9bB0RiUS3zZ33jHKRVJ/ORu vpXH/QKg1xCcv4C/F9IaoKkemQ== X-Google-Smtp-Source: AGHT+IFndInI3ROJr7Xma3uL1HuF3MxWN7W2vtrRlnwhIYSMbBbuFCG3VE4WjMo60/MNXEXTe2yByQ== X-Received: by 2002:a17:906:7492:b0:9b2:d018:20b2 with SMTP id e18-20020a170906749200b009b2d01820b2mr1372868ejl.39.1696401458083; Tue, 03 Oct 2023 23:37:38 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:37 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/4] dt-bindings: clock: si5351: add PLL reset mode property Date: Wed, 4 Oct 2023 08:35:29 +0200 Message-ID: <20231004063712.3348978-4-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231003_233741_693971_05073D46 X-CRM114-Status: GOOD ( 15.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Alvin Šipraga For applications where the PLL must be adjusted without glitches in the clock output(s), a new silabs,pll-reset-mode property is added. It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml index 400c8cec2a3a..f1be09b5c48c 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -53,6 +53,27 @@ properties: - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). enum: [ 0, 1 ] + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + description: | + A list of cell pairs containing a PLL index and its reset mode. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: | + Reset mode for the PLL. Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is + specified in one of the clock output child nodes that also sources + the PLL. This mode may be preferable if output clocks are expected + to be adjusted without glitches. + enum: [ 0, 1 ] + patternProperties: "^clkout@[0-7]$": type: object @@ -207,6 +228,9 @@ examples: /* Use XTAL input as source of PLL0 and PLL1 */ silabs,pll-source = <0 0>, <1 0>; + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode = <1 1>; + /* * Overwrite CLK0 configuration with: * - 8 mA output drive strength From patchwork Wed Oct 4 06:35:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 13408273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25D15E8FDD0 for ; Wed, 4 Oct 2023 06:38:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XB0mGBJS4iTE1NAHur9XAUI/pydczn+JpotNnVn9Ngk=; b=nsFGbXEMuL/Woq 8eJBXqV61iQb4icFOR8Bf3NTagNRVVqmf8SY0Wg9yyO+d6wupDAdRIVUxTDo1T3pbZ3X3fNi98jA6 wnnqub7esF8uFfwZIy8GvF3FUseR72huu0w1NXprCQf/g722b9dS0E30sH4WFLbtu+Ds/COw+rI6g M7MLpncMOKGy4E8lW0mq+QWven4r8nL8KpFsPa2d1QON0Qg9SId006ZbM75UB4MaS4zjflEQ0yMgy dW250jtZHq6Q1ziGE6+jocWKF5Qhmk6ZhuEtAsEaC0b4VRMpGggI65FQOm6oLp73FbnHZc0pI6dEL szUiETcWhw531Vbq+8pQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qnvW0-00GRFu-2n; Wed, 04 Oct 2023 06:37:48 +0000 Received: from mail-ej1-f51.google.com ([209.85.218.51]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qnvVw-00GRBb-0B for linux-arm-kernel@lists.infradead.org; Wed, 04 Oct 2023 06:37:45 +0000 Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-9a6190af24aso315244066b.0 for ; Tue, 03 Oct 2023 23:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401461; x=1697006261; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+rE6XvlSeUckpfUomIWf/ozKzyY+JN+wOSM6QZFHuwo=; b=HUofCYEKXzV8EWtLjgDhpvnfGE3KHbKKwx+AeKIKdpLQEJgEmbdzbaru/68eS359t9 8F290TBU3WCEbWR2Ymuvynx2M34KTT5PHgObXytahStbQUducZyoz8b08d2fFB84cQR4 H0wNeSN+xbzB0p/+inzSOmgQorT7p0kdTNaCJi8Nkn7hMY80yd5OHzJZNEsaDZtAae6K CJbPTyMMPFmobswoyfQF/A7kGpGbsfJT14Z/qTd6Cq7lOYQDmVqMxSeojH1ogHsnb9lL WWX+VRb1dJh/Megv3IojREAnYLVV6ViiFfAcn9DadQ7IjcOD78vsemmJzNjtHRhbs/98 pnZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401461; x=1697006261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+rE6XvlSeUckpfUomIWf/ozKzyY+JN+wOSM6QZFHuwo=; b=bCrpQ1G8HoJq/i5TsRESklsiRrFcTPN2ppyvMZ97ZNhSU7xZaCjfn1c+pplqwobwiN R0k0rDD+Iq1h+soOBFLbucPHvjsSqaHtsi0WUFmkhpFHMwt+FAKTHMWgykQFwx9asOS9 WX3UcURePcMJVwu54/FRxUFk7NQzda3o2HVNXjuQvcqtEuxGjVT2gtCc9dQuniVRwJGQ nr9EDlbJ6+QHua0dHpoZTSKKfa++I8nq4YhPr0ycLLSIF37WLg7NoxY/PbPVFuaxA4eQ QlLq6mJm09KsXkj47J8P7JG0U3BmOZ9Lfs0MAVx/nBeDgrfrAcJIUY6PRyg3AjMde9hw Q0Kg== X-Gm-Message-State: AOJu0YyVp8yCcpEFMkL9CvLFx7T9ZlKnPvUedn0W0sKTQZufQioHFIYW Stp8ydVjKyLkwTw1u/+VEmaj1Q== X-Google-Smtp-Source: AGHT+IHU2z1M0rnNTwOLTwxqBhdkD2ERONtPqMIyQCjhRDJLVt1Cq8Z//jENvytoAOWzoM5XtKEZQA== X-Received: by 2002:a17:906:5341:b0:9b8:7709:6360 with SMTP id j1-20020a170906534100b009b877096360mr1121607ejo.40.1696401460849; Tue, 03 Oct 2023 23:37:40 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:40 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] clk: si5351: allow PLLs to be adjusted without reset Date: Wed, 4 Oct 2023 08:35:30 +0200 Message-ID: <20231004063712.3348978-5-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231003_233744_096697_A4ADD2E1 X-CRM114-Status: GOOD ( 25.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Alvin Šipraga Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga Acked-by: --- drivers/clk/clk-si5351.c | 47 ++++++++++++++++++++++++++-- include/linux/platform_data/si5351.h | 2 ++ 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 00fb9b09e030..95d7afb8cfc6 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index c71a2dd66143..5f412a615532 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -105,10 +105,12 @@ struct si5351_clkout_config { * @clk_xtal: xtal input clock * @clk_clkin: clkin input clock * @pll_src: array of pll source clock setting + * @pll_reset: array indicating if plls should be reset after setting the rate * @clkout: array of clkout configuration */ struct si5351_platform_data { enum si5351_pll_src pll_src[2]; + bool pll_reset[2]; struct si5351_clkout_config clkout[8]; };