From patchwork Wed Oct 4 16:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD38DE7C4DA for ; Wed, 4 Oct 2023 16:10:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233125AbjJDQKy (ORCPT ); Wed, 4 Oct 2023 12:10:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233853AbjJDQKx (ORCPT ); Wed, 4 Oct 2023 12:10:53 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28DA9B; Wed, 4 Oct 2023 09:10:49 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 7777260003; Wed, 4 Oct 2023 16:10:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435847; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zphNeuBKwavuluA4nnf6uDnS6Nyy4EaH0fzXUOIOYYM=; b=KjEvbUqbKE+hHhimKQB2sEaTSSYifdMqsGRX4SqNqrUjX519Vc6KBUKo19UhOljwZBgDb2 WxnVeMUtcmIGODBEKzBQlEsj13mE/0YtMStD1yOnsnNOZxotHBQPcK2HN/4T2F+Mfxg1Qs ZuessHwlQ8gvAPtXqHocasvgOop1Mo5RaJqIEQc+TmWOGfQGbiyHWDD5O/bHbmxlzceM7Q vsrY+aCIh6ITSRUeLsYFy+BnVsLxU3DiFyl+a4T0NJ02aSrz7IvgE6saVuF0R4o0DTY4Lo 0HRtVkGXQ1jMMMyri5AfB3mPBmKS9Eo1TuPhPpVMCZ3womA04etm3tpbrlsMUw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64 bit code Date: Wed, 4 Oct 2023 18:10:28 +0200 Message-Id: <20231004161038.2818327-2-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The code clearing BSS already use macro or use correct instruction depending id the CPU is 32 bits or 64 bits. However, a few instructions remained 32 bits only. By using the accurate MACRO, it is now possible to deal with memory address beyond 32 bits. As a side effect, when using 64bits processor, it also divides the loop number needed to clear the BSS by 2. Signed-off-by: Gregory CLEMENT Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Florian Fainelli --- arch/mips/boot/compressed/head.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S index 5795d0af1e1b..d237a834b85e 100644 --- a/arch/mips/boot/compressed/head.S +++ b/arch/mips/boot/compressed/head.S @@ -25,8 +25,8 @@ /* Clear BSS */ PTR_LA a0, _edata PTR_LA a2, _end -1: sw zero, 0(a0) - addiu a0, a0, 4 +1: PTR_S zero, 0(a0) + PTR_ADDIU a0, a0, PTRSIZE bne a2, a0, 1b PTR_LA a0, (.heap) /* heap address */ From patchwork Wed Oct 4 16:10:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E5E8E7C4DD for ; Wed, 4 Oct 2023 16:10:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243258AbjJDQK6 (ORCPT ); Wed, 4 Oct 2023 12:10:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243065AbjJDQK4 (ORCPT ); Wed, 4 Oct 2023 12:10:56 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C980DA7; Wed, 4 Oct 2023 09:10:50 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 2EA5C60007; Wed, 4 Oct 2023 16:10:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AdS05Ve7lxnDwdF1Yquti+PQQLRtSRrj8ca5Ty3LXvY=; b=cqOuAnAGGgrCcIVKDvmLu1lxyQCMpRYqkwrc3k7DLT7hZbNC2ZL3YGZaGMZ/iVL9WSU5pC //IznqjmCXq/VBVvor0Z/D0Tqu0M9tHYKJ9rcFNZ42VlWstgbPOzg7NFkHrVgDS2JpuNIM z9Mju2OoJIVlUGKbcT7q61MYT6w38/vhHlWEiK+a70nfz830F20F+5tRzMHmoUXMXmxKvs 1ZWbcAuBIZPMIAIOUSM29IA80rhhc3NBRBmTexhi94Oj8AODnCOneT3XULZRJsY5veMoak XCy3oCBnjFRuq0xbyzDJIGs1hEIK/zr7H/SXViJhZ5MqBAG+lfQyqrRKUeuXTg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 02/11] MIPS: use virtual addresses from xkphys for MIPS64 Date: Wed, 4 Oct 2023 18:10:29 +0200 Message-Id: <20231004161038.2818327-3-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Vladimir Kondratiev Now 64-bit MIPS uses 32-bit compatible segments KSEG0 and KSEG1 to trivially map first 1/2 GByte of physical memory. This memory used to run kernel. This mean, one should have memory installed in this area in order for Linux to work. Kconfig CONFIG_USE_XKPHYS introduced; it adds support for kernel to use virtual addresses from the XKPHYS segment for both cached and uncached access. XKPHYS allows to access 2^48 bytes of memory, thus allowing kernel to work with any memory configuration. MIPS CPU sets KX bit in the CP0 status register at reset if RESET_BASE_MODE (BIT 1) set in the GCR_CL_RESET_BASE. Reset vector should fit into 32-bit. If reset vector put outside of KSEG1, BIT(1) should be set in this value. IRQ handler for CPU updated to generate 64-bit address for jump Signed-off-by: Vladimir Kondratiev Signed-off-by: Gregory CLEMENT --- arch/mips/Kconfig | 15 +++++++++++++ arch/mips/Makefile | 4 ++++ arch/mips/generic/Platform | 5 +++++ arch/mips/include/asm/addrspace.h | 12 ++++++++-- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/page.h | 10 +++++++++ arch/mips/include/asm/vga.h | 4 ++++ arch/mips/kernel/cps-vec.S | 8 +++++++ arch/mips/kernel/genex.S | 14 ++++++++++++ arch/mips/kernel/smp-cps.c | 37 +++++++++++++++++++++++-------- arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--- arch/mips/lib/uncached.c | 10 +++++++++ arch/mips/mm/init.c | 4 ++-- 13 files changed, 140 insertions(+), 16 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc8421859006..92832bbcca5d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2026,6 +2026,21 @@ config 64BIT endchoice +config USE_XKPHYS + bool "use virtual address from XKPHYS" + depends on 64BIT + default n + help + By default, MIPS uses 32-bit compatible segments KSEG0 and KSEG1 + to trivially map first 1/2 GByte of physical memory. This mean, + one should have memory installed in this area in order for Linux to + work. With this option selected, kernel uses virtual addresses from + the XKPHYS segment for both cached and uncached access. XKPHYS allows + to access 2^48 bytes of memory, thus allowing to work with any memory + configuration. + + Say N if not sure + config MIPS_VA_BITS_48 bool "48 bits virtual memory" depends on 64BIT diff --git a/arch/mips/Makefile b/arch/mips/Makefile index f49807e1f19b..544ee8427cab 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -303,6 +303,10 @@ ifdef CONFIG_64BIT endif endif + ifdef CONFIG_USE_XKPHYS + KBUILD_SYM32 = n + endif + ifeq ($(KBUILD_SYM32), y) cflags-$(KBUILD_SYM32) += -msym32 -DKBUILD_64BIT_SYM32 else diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index 0c03623f3897..2be9947814ad 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -12,7 +12,12 @@ cflags-$(CONFIG_MACH_INGENIC_SOC) += -I$(srctree)/arch/mips/include/asm/mach-ingenic cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic +ifndef (CONFIG_USE_XKPHYS) load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000 +else +load-$(CONFIG_MIPS_GENERIC) += 0xa800000080100000 +endif + all-$(CONFIG_MIPS_GENERIC) += vmlinux.gz.itb its-y := vmlinux.its.S diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065..8dc500d8e66d 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -65,10 +65,15 @@ #define XKSSEG _CONST64_(0x4000000000000000) #define XKPHYS _CONST64_(0x8000000000000000) #define XKSEG _CONST64_(0xc000000000000000) +#if !defined(CONFIG_USE_XKPHYS) #define CKSEG0 _CONST64_(0xffffffff80000000) #define CKSEG1 _CONST64_(0xffffffffa0000000) #define CKSSEG _CONST64_(0xffffffffc0000000) #define CKSEG3 _CONST64_(0xffffffffe0000000) +#else +#define CKSEG0 XKPHYS_CM_CACHED +#define CKSEG1 XKPHYS_CM_UNCACHED +#endif /* !defined(CONFIG_USE_XKPHYS) */ #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) @@ -126,8 +131,11 @@ #define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) #define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) #define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a)) - +#define XKPHYS_CM(cm) (XKPHYS | (_ACAST64_(cm) << 59)) +#define PHYS_TO_XKPHYS(cm, a) (XKPHYS_CM(cm) | (a)) +#define XKPHYS_CM_CACHED (XKPHYS_CM(K_CALG_COH_SHAREABLE)) +#define XKPHYS_CM_UNCACHED (XKPHYS_CM(K_CALG_UNCACHED)) +#define IS_XKPHYS(a) (((a) >> 62) == 2) /* * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting * the region, 3 bits for the CCA mode. This leaves 59 bits of which the diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..15d8d69de455 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 5978a8dfb917..53b8306da571 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -176,7 +176,11 @@ static inline unsigned long ___pa(unsigned long x) * the compatibility segements ckseg0 or ckseg1, or it may * be in xkphys. */ +#if defined(CONFIG_USE_XKPHYS) + return XPHYSADDR(x); +#else return x < CKSEG0 ? XPHYSADDR(x) : CPHYSADDR(x); +#endif } if (!IS_ENABLED(CONFIG_EVA)) { @@ -196,7 +200,11 @@ static inline unsigned long ___pa(unsigned long x) return x - PAGE_OFFSET + PHYS_OFFSET; } #define __pa(x) ___pa((unsigned long)(x)) +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS) +#define __va(x) ((void *)PHYS_TO_XKSEG_CACHED(x)) +#else #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) +#endif #include /* @@ -239,6 +247,8 @@ static inline unsigned long kaslr_offset(void) return __kaslr_offset; } +#define UNCAC_ADDR(addr) (UNCAC_BASE + __pa(addr)) + #include #include diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h index 0136e0366698..e338e57d0784 100644 --- a/arch/mips/include/asm/vga.h +++ b/arch/mips/include/asm/vga.h @@ -16,7 +16,11 @@ * access the videoram directly without any black magic. */ +#if defined(CONFIG_USE_XKPHYS) +#define VGA_MAP_MEM(x, s) UNCAC_ADDR(0x10000000L + (unsigned long)(x)) +#else #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x)) +#endif #define vga_readb(x) (*(x)) #define vga_writeb(x, y) (*(y) = (x)) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580..541f31a43a7f 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -554,7 +554,11 @@ LEAF(mips_cps_cache_init) mul t1, t1, t0 mul t1, t1, t2 +#if defined(CONFIG_USE_XKPHYS) + PTR_LI a0, XKPHYS_CM_CACHED +#else li a0, CKSEG0 +#endif PTR_ADD a1, a0, t1 1: cache Index_Store_Tag_I, 0(a0) PTR_ADD a0, a0, t0 @@ -581,7 +585,11 @@ icache_done: mul t1, t1, t0 mul t1, t1, t2 +#if defined(CONFIG_USE_XKPHYS) + PTR_LI a0, XKPHYS_CM_CACHED +#else li a0, CKSEG0 +#endif PTR_ADDU a1, a0, t1 PTR_SUBU a1, a1, t0 1: cache Index_Store_Tag_D, 0(a0) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..a002058e1838 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,25 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler +#if defined(CONFIG_USE_XKPHYS) +FEXPORT(except_vec_vi_63_48) + lui v0, 0 /* Patched - bits 63:48 */ +FEXPORT(except_vec_vi_47_32) + ori v0, 0 /* Patched - bits 47:32 */ + dsll v0, v0, 0x10 +FEXPORT(except_vec_vi_31_16) + ori v0, 0 /* Patched - bits 31:16 */ + dsll v0, v0, 0x10 + jr v1 +FEXPORT(except_vec_vi_15_0) + ori v0, 0 /* Patched - bits 15:0 */ +#else /* defined(CONFIG_USE_XKPHYS) */ FEXPORT(except_vec_vi_lui) lui v0, 0 /* Patched */ jr v1 FEXPORT(except_vec_vi_ori) ori v0, 0 /* Patched */ +#endif /* defined(CONFIG_USE_XKPHYS) */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db..47e76722a306 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -34,10 +34,33 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +/** + * plat_core_entry - query reset vector for NMI/reset + * + * Returns low 32 bits of the reset vector + * + * This is used to fill 2 registers: + * - BEV Base (GCR_BEV_BASE) Offset: 0x0680 + * - VP Local Reset Exception Base (GCR_CL_RESET_BASE,GCR_CO_RESET_BASE) + * Offset: 0x0020 (0x2020 relative to GCR_BASE_ADDR) + * + * In both registers, BIT(1) should be set in case it uses address in XKPHYS + * (as opposed to KSEG1). This bit defined as CM_GCR_Cx_RESET_BASE_MODE, + * using it unconditionally because for GCR_BEV_BASE its value is the same + */ +static u32 plat_core_entry(void) +{ +#if defined(CONFIG_USE_XKPHYS) + return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff) + | CM_GCR_Cx_RESET_BASE_MODE; +#else + return CKSEG1ADDR((unsigned long)mips_cps_core_entry); +#endif +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +117,8 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(plat_core_entry()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -213,7 +234,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(plat_core_entry()); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +311,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +334,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(plat_core_entry()); mips_cm_unlock_other(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..875594843626 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,11 +2091,20 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_end[]; extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; + const int handler_len = except_vec_vi_end - vec_start; +#if defined(CONFIG_USE_XKPHYS) + extern const u8 except_vec_vi_63_48[], except_vec_vi_47_32[]; + extern const u8 except_vec_vi_31_16[], except_vec_vi_15_0[]; + const int offset_63_48 = except_vec_vi_63_48 - vec_start; + const int offset_47_32 = except_vec_vi_47_32 - vec_start; + const int offset_31_16 = except_vec_vi_31_16 - vec_start; + const int offset_15_0 = except_vec_vi_15_0 - vec_start; +#else /* defined(CONFIG_USE_XKPHYS) */ + extern const u8 except_vec_vi_lui[], except_vec_vi_ori[]; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) const int lui_offset = except_vec_vi_lui - vec_start + 2; const int ori_offset = except_vec_vi_ori - vec_start + 2; @@ -2103,7 +2112,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) const int lui_offset = except_vec_vi_lui - vec_start; const int ori_offset = except_vec_vi_ori - vec_start; #endif - const int handler_len = except_vec_vi_end - vec_start; +#endif /* defined(CONFIG_USE_XKPHYS) */ if (handler_len > VECTORSPACING) { /* @@ -2119,10 +2128,21 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif +#if defined(CONFIG_USE_XKPHYS) + h = (u16 *)(b + offset_63_48); + *h = (handler >> 48) & 0xffff; + h = (u16 *)(b + offset_47_32); + *h = (handler >> 32) & 0xffff; + h = (u16 *)(b + offset_31_16); + *h = (handler >> 16) & 0xffff; + h = (u16 *)(b + offset_15_0); + *h = (handler >> 0) & 0xffff; +#else /* defined(CONFIG_USE_XKPHYS) */ h = (u16 *)(b + lui_offset); *h = (handler >> 16) & 0xffff; h = (u16 *)(b + ori_offset); *h = (handler & 0xffff); +#endif /* defined(CONFIG_USE_XKPHYS) */ local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } @@ -2332,7 +2352,11 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { +#if IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_USE_XKPHYS) + unsigned long uncached_ebase = UNCAC_ADDR(ebase); +#else unsigned long uncached_ebase = CKSEG1ADDR(ebase); +#endif if (!addr) panic(panic_null_cerr); @@ -2384,9 +2408,11 @@ void __init trap_init(void) * EVA is special though as it allows segments to be rearranged * and to become uncached during cache error handling. */ +#if !defined(CONFIG_USE_XKPHYS) if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) ebase = CKSEG0ADDR(ebase_pa); else +#endif ebase = (unsigned long)phys_to_virt(ebase_pa); } diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c index f80a67c092b6..8a78348a2dd7 100644 --- a/arch/mips/lib/uncached.c +++ b/arch/mips/lib/uncached.c @@ -44,6 +44,10 @@ unsigned long run_uncached(void *func) __asm__("move %0, $sp" : "=r" (sp)); +#if defined(CONFIG_USE_XKPHYS) + if (IS_XKPHYS(sp)) + usp = UNCAC_ADDR(sp); +#else /* defined(CONFIG_USE_XKPHYS) */ if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) usp = CKSEG1ADDR(sp); #ifdef CONFIG_64BIT @@ -52,10 +56,15 @@ unsigned long run_uncached(void *func) usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)sp)); #endif +#endif /* defined(CONFIG_USE_XKPHYS) */ else { BUG(); usp = sp; } +#if defined(CONFIG_USE_XKPHYS) + if (IS_XKPHYS(lfunc)) + ufunc = UNCAC_ADDR(lfunc); +#else /* defined(CONFIG_USE_XKPHYS) */ if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2) ufunc = CKSEG1ADDR(lfunc); #ifdef CONFIG_64BIT @@ -64,6 +73,7 @@ unsigned long run_uncached(void *func) ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)lfunc)); #endif +#endif /* defined(CONFIG_USE_XKPHYS) */ else { BUG(); ufunc = lfunc; diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 5dcb525a8995..eb57283ec4e0 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -427,7 +427,7 @@ void __init paging_init(void) free_area_init(max_zone_pfns); } -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS) static struct kcore_list kcore_kseg0; #endif @@ -470,7 +470,7 @@ void __init mem_init(void) setup_zero_pages(); /* Setup zeroed pages. */ mem_init_free_highmem(); -#ifdef CONFIG_64BIT +#if defined(CONFIG_64BIT) && !defined(CONFIG_USE_XKPHYS) if ((unsigned long) &_text > (unsigned long) CKSEG0) /* The -4 is a hack so that user tools don't have to handle the overflow. */ From patchwork Wed Oct 4 16:10:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6C4EE7C4DE for ; Wed, 4 Oct 2023 16:10:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243253AbjJDQK5 (ORCPT ); Wed, 4 Oct 2023 12:10:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243244AbjJDQK4 (ORCPT ); Wed, 4 Oct 2023 12:10:56 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7A47C0; Wed, 4 Oct 2023 09:10:52 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id D2623E0006; Wed, 4 Oct 2023 16:10:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VOjmWr0mfjgBp7nTWHYGPwk6e22EOwSF4b0ZHDI/Irc=; b=mK6smk9vHL4Vz1l1in2vpkrJfRKPFK5FWJ/iGAp0VFPia3gMZAa1jSIoybLSXms4wEB9+5 EuY4Q042RL7K5FRQZieMtyubzN4Fvnyr8/udm4tmIqYNj91o0GAEaa9MN/80cprFJd0iYF tAT2DermcTvyHEMy2rrieelCWPFbTM/2D6JBQtyGWdjWdEg+AbBo8u6whRPOfBY9gI1LU4 EH5/7oXEYrasvjmvAxcI+ePVL6Hhe3PLrPI8cotMRE85SvO1BInV+MG/6j8olGOfNSMv5j ukHuI4V3mIF/9845SJCizcDJC74Z2HatyWu561L7nvPkKRTrQRMD21BgbOKPNw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 03/11] MIPS: support RAM beyond 32-bit Date: Wed, 4 Oct 2023 18:10:30 +0200 Message-Id: <20231004161038.2818327-4-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org From: Vladimir Kondratiev Support platforms where RAM is mapped beyond 32-bit. The kernel parameter ddr32_alias allows to setup the alias to point outside the first 4 GB of memory. Signed-off-by: Vladimir Kondratiev Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/smp-cps.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 47e76722a306..fcfb19487612 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -34,6 +34,16 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static int ddr32_alias; + +static int __init ddr32_alias_setup(char *str) +{ + get_option(&str, &ddr32_alias); + + return 0; +} +early_param("ddr32_alias", ddr32_alias_setup); + /** * plat_core_entry - query reset vector for NMI/reset * @@ -52,7 +62,7 @@ static u32 plat_core_entry(void) { #if defined(CONFIG_USE_XKPHYS) return (UNCAC_ADDR(mips_cps_core_entry) & 0xffffffff) - | CM_GCR_Cx_RESET_BASE_MODE; + | ddr32_alias | CM_GCR_Cx_RESET_BASE_MODE; #else return CKSEG1ADDR((unsigned long)mips_cps_core_entry); #endif From patchwork Wed Oct 4 16:10:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94275E7C4DF for ; Wed, 4 Oct 2023 16:10:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243266AbjJDQLA (ORCPT ); Wed, 4 Oct 2023 12:11:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243247AbjJDQK5 (ORCPT ); Wed, 4 Oct 2023 12:10:57 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02A14A6; Wed, 4 Oct 2023 09:10:53 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 78E3CE0009; Wed, 4 Oct 2023 16:10:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jnyUTLwehVTtlgEUKBboKjzUzWzf0QX897nmrudhojE=; b=XQn9Zepg+l7OWf8lbe+kp6cCBOb7ZTPXRsJrUDCtXSOIscOIotgCfPqHblOzi98DohPz2i n8dqH0Tu3GnLEwJtiC8+a/dpQcJBysao6weyK1w98Bj1SDkVTJ96kIcQ6sbURdQIZo8bFM 9WB01KKpHJ7U/qzbYjM49TZaGzqcc8+q6UARwUcmKvPbvuLS3Cxbwl2Chx/y2IysUdoYoU fl26Uiscvh1d06p/Xgj+R/iubguDnX6YH4OBQ7ZMHuGD6Xqj0myPf8uoF2ywdJmBevCVPT 3IDLGHAv42JJrBzo18atNNZ0aOl+RDiHaevcsAzXtmKjY6sa82JxThi2lbEKuw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 04/11] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd. Date: Wed, 4 Oct 2023 18:10:31 +0200 Message-Id: <20231004161038.2818327-5-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Mobileye Vision Technologies Ltd. is a company developing autonomous driving technologies and advanced driver-assistance systems (ADAS) including cameras, computer chips and software. Signed-off-by: Gregory CLEMENT Reviewed-by: Philippe Mathieu-Daudé Acked-by: Rob Herring --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 573578db9509..510c6c03f6d5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -877,6 +877,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. "^modtronix,.*": description: Modtronix Engineering "^moortec,.*": From patchwork Wed Oct 4 16:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D152E7C4DE for ; Wed, 4 Oct 2023 16:11:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243252AbjJDQLC (ORCPT ); Wed, 4 Oct 2023 12:11:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243261AbjJDQK6 (ORCPT ); Wed, 4 Oct 2023 12:10:58 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63239DC; Wed, 4 Oct 2023 09:10:55 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id E79DF60009; Wed, 4 Oct 2023 16:10:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435854; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2M+32849Tx+dqNVRkLeeEYLB/CoHX0gof98iAjJ75Jc=; b=oz+oIwM+20+krXSAk6TkymvOyLYexgraxaJceDR6rYOEMnyXRRutCNE/9DFoMsloF22niG a+Ww7+oPAFBCZsPXAMh1WCoe10L5pmpy9hV2v33mUU/IcPKg7/biRquqrF7EAaSBGQ6Xe+ 7LLbt0K21xIVAxxbMo5Rjvtm3EXszwVK5lBB1U//wXpIRS0HuuTE9zAuOe4Zh3s0vj5I26 1xdyIwNwrAS7DqpvDvj8l2lI7zW30jTO2uMWjP28r7KxPANPRmKy6ofSuXbqZM+f4Roe3S Q2Vb12uXpPlEzGlS/u/2amjS2L8KPHdouXJOxF9uRohNMGhwSOC7njyWiSxATg== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 05/11] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Date: Wed, 4 Oct 2023 18:10:32 +0200 Message-Id: <20231004161038.2818327-6-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Signed-off-by: Gregory CLEMENT Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Sergio Paracuellos Acked-by: Arnd Bergmann Acked-by: Serge Semin --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922..87fd2842ba68 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -39,6 +39,7 @@ properties: - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,i6500 reg: maxItems: 1 From patchwork Wed Oct 4 16:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B9EEE7C4DE for ; Wed, 4 Oct 2023 16:11:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243274AbjJDQLJ (ORCPT ); Wed, 4 Oct 2023 12:11:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243272AbjJDQLC (ORCPT ); Wed, 4 Oct 2023 12:11:02 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D79C3A7; Wed, 4 Oct 2023 09:10:56 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 4F197E0004; Wed, 4 Oct 2023 16:10:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fNUAlceB4v3YuX6aNvHrvuj3iMFZRS3mSoGXc1wzpQw=; b=Z2GGNY7o8N2rLe6Y49DVkTqqNhtXuJ9ybKtkgTuNRRUli3Wg+X3ywhRoOWTdfBycHAAtNi NekvbHMLOd2GJRNIEXgCdmS2u6j0Rsy12RbtvQbHFdguZwkSggXET/nRMpkFjuSlSvYAud a9bKM0GJblQyLLzeCeP0AobG9PJNh8UEG5BjlyAQmRIBsqv/VKUSXtGO+hEcp6ySVqw8It L6FM/nqMSsQSCVVrb3XK4RMZ3H5QSqXMd+1uu3O2XWm1GgQTU93e/gtdSg/cAQ+Qgh8fQb 5KbC4dB0rQh2MLNl2Hxe3BDLb9y0zZlH0/ZgGKFn+EmLN6u86EnRQZNHFPE83Q== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 06/11] dt-bindings: mips: Add bindings for Mobileye SoCs Date: Wed, 4 Oct 2023 18:10:33 +0200 Message-Id: <20231004161038.2818327-7-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add the yaml bindings for Mobileye SoCs. Currently only EyeQ5 is supported Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/mips/mobileye.yaml | 36 +++++++++ include/dt-bindings/soc/mobileye,eyeq5.h | 77 +++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml create mode 100644 include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml new file mode 100644 index 000000000000..f47767bc2c8f --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev + - Gregory CLEMENT + - Théo Lebrun + +description: | + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + + - description: Boards with Mobileye EyeQ6 SoC + items: + - const: mobileye,eyeq6 + +additionalProperties: true + +... diff --git a/include/dt-bindings/soc/mobileye,eyeq5.h b/include/dt-bindings/soc/mobileye,eyeq5.h new file mode 100644 index 000000000000..7d8cb97b45bf --- /dev/null +++ b/include/dt-bindings/soc/mobileye,eyeq5.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ +#ifndef _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H +#define _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H + +/* EQ5 interrupts */ +#define NUM_INT_I2C_A 1 +#define NUM_INT_I2C_B 2 +#define NUM_INT_I2C_C 3 +#define NUM_INT_I2C_D 4 +#define NUM_INT_I2C_E 5 + +#define NUM_INT_UART 6 /* same for all UARTs - A, B, C */ +#define NUM_INT_PCIE0_INT0 7 +#define NUM_INT_PCIE0_INT1 8 + +#define NUM_INT_CAN 9 /* same for all CANs A, B, C */ + +#define NUM_INT_EMMC 10 +/* empty 11 */ +#define NUM_INT_SPIA_B 12 +#define NUM_INT_SPIC_D 13 + +#define NUM_INT_GPIO 14 + +#define NUM_INT_TIMER_0 15 +#define NUM_INT_TIMER_1 16 +#define NUM_INT_TIMER_2 17 +#define NUM_INT_TIMER_3 18 +#define NUM_INT_TIMER_4_ETIMER0_1 19 +#define NUM_INT_OQSPI 20 +#define NUM_INT_DDR_CTRL 21 +#define NUM_INT_NOC 22 + +#define NUM_INT_GEM0 23 +#define NUM_INT_GEM1 24 + +#define NUM_INT_VDI_0_VC0 25 +#define NUM_INT_VDI_0_VC1 26 +#define NUM_INT_VDI_0_VC2 27 +#define NUM_INT_VDI_0_VC3 28 +#define NUM_INT_VDI_0_ERR 29 +#define NUM_INT_VDI_1_VC0 30 +#define NUM_INT_VDI_1_VC1 31 +#define NUM_INT_VDI_1_VC2 32 +#define NUM_INT_VDI_1_VC3 33 +#define NUM_INT_VDI_1_ERR 34 + +#define NUM_INT_MPC0 35 +#define NUM_INT_MPC1 36 +#define NUM_INT_MPC2 37 +#define NUM_INT_MPC3 38 +#define NUM_INT_MPC4 39 +#define NUM_INT_VMP0 40 +#define NUM_INT_VMP1 41 +#define NUM_INT_VMP2 42 +#define NUM_INT_VMP3 43 +#define NUM_INT_PMA0 44 +#define NUM_INT_PMA1 45 +#define NUM_INT_PMAC0 46 +#define NUM_INT_PMAC1 47 + +#define NUM_INT_PCIE1_INT0 48 +#define NUM_INT_PCIE1_INT1 49 + +#define NUM_INT_HSM_C3 50 + +#define NUM_INT_MJPEG 51 + +#define NUM_INT_FCMU_OLB 52 +#define NUM_INT_FCMU_NMI 53 +#define NUM_INT_WDDOG_TIMER 54 +#define NUM_INT_WDDOG_TIMER_1 55 + +#endif /* _DT_BINDINGS_SOC_MOBILEYE_EYEQ5_H */ From patchwork Wed Oct 4 16:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8A30E7C4DA for ; Wed, 4 Oct 2023 16:11:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243297AbjJDQLQ (ORCPT ); Wed, 4 Oct 2023 12:11:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243265AbjJDQLD (ORCPT ); Wed, 4 Oct 2023 12:11:03 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B27FEA; Wed, 4 Oct 2023 09:10:58 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id C5C46E000B; Wed, 4 Oct 2023 16:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435857; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NbiHukxXHtfMlJb+CEN6liIu+XF9nH8/hmBYmzodN1k=; b=TBGgKq8PXQ8vlq4nuLeUcJcz+BtZfXNd/ki69O9VOavoe9dWDcAr2i7tqcF0qZm0TCAtpO I93ekBeHUg5qLqha6C4xmsX/YQZMsf7Kitea/5P1yFCSXQY8Nd6hZPXlrSRV/Co5eY4PZl QxXdchNXkrkw0UhgBYO4QCq++09ahwOcDCdmOdYGhQmz+67EtFK+Qa5pVhYu4WAvSSxfbg Ff+Zp+aQzF0nVC9ry7XxoHZbgCE+O/pX1hffOOM8VSR3/7afqwlZ+vPaJ4Gz2LdGzzgspv q99wYlTmYjb8yOMdpuMAuUsIilALVrayy46aVxPxKzK88UyKltmWVPK8e16D7Q== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 07/11] dt-bindings: mfd: syscon: Document EyeQ5 OLB Date: Wed, 4 Oct 2023 18:10:34 +0200 Message-Id: <20231004161038.2818327-8-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document Mobileye EyeQ5 compatibles for OLB registers that are misceallanous SoC related registers. Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 8103154bbb52..70bc6e8d15ba 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -53,6 +53,7 @@ properties: - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8365-syscfg + - mobileye,eyeq5-olb - microchip,lan966x-cpu-syscon - microchip,sparx5-cpu-syscon - mstar,msc313-pmsleep From patchwork Wed Oct 4 16:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA7AE7C4DD for ; Wed, 4 Oct 2023 16:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233624AbjJDQLe (ORCPT ); Wed, 4 Oct 2023 12:11:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243293AbjJDQLP (ORCPT ); Wed, 4 Oct 2023 12:11:15 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3396CDC; Wed, 4 Oct 2023 09:11:01 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id A1119FF80F; Wed, 4 Oct 2023 16:10:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435859; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vqzy15VCSvW/RtLwBCM0xG7t72x6WJ6p8eSZ6Hb8QJ4=; b=YOK4/SsQpDAOUkZabmrqnKr7714pWZE5khgyIPF0MF9VwIqMpqabcQA/yyQu51H3+JdtOZ v+AKX9KZUZ7SCG1yVZfdKC8zeKYxZROFFCosnX9J8CjOBI1zw7BLfJPPGFIE0iCbBVONAz r2vr/X8VhkASzYAH54+Wa4rviUY5ebeBV3Cj32dQs/2kVuKl+FeSOkH5EcTHwDQVzS36p5 lwvD0sHkUwn8i9jrioOYgHWVyKh4jtxvrAZYXkH4FRLYxcJcnWR5Bi/3PlFyXVtkGOXx5x GbWvLLieKumvHn4Ikl8PAUMlinZcyihJsopm935WxnJab+pZD2OZQYgzWgKt2w== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 08/11] MIPS: mobileye: Add EyeQ5 dtsi Date: Wed, 4 Oct 2023 18:10:35 +0200 Message-Id: <20231004161038.2818327-9-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add a device tree include file for the Mobileye EyeQ5 SoC. Based on the work of Slava Samsonov Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/Makefile | 1 + arch/mips/boot/dts/mobileye/Makefile | 4 + .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 315 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 138 ++++++++ 4 files changed, 458 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/Makefile create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 928f38a79dff..edb8e8dee758 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti +subdir-$(CONFIG_SOC_EYEQ5) += mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile new file mode 100644 index 000000000000..99c4124fd4c0 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2023 Mobileye Vision Technologies Ltd. + +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 000000000000..a0066465ac8b --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll_cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll_vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll_per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll_ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll_ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ_cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "occ_cpu"; + }; + si_css0_ref_clk: si_css0_ref_clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "si_css0_ref_clk"; + }; + cpc_clk: cpc_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "cpc_clk"; + }; + core0_clk: core0_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "core0_clk"; + }; + core1_clk: core1_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "core1_clk"; + }; + core2_clk: core2_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "core2_clk"; + }; + core3_clk: core3_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "core3_clk"; + }; + cm_clk: cm_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "cm_clk"; + }; + mem_clk: mem_clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mem_clk"; + }; + occ_isram: occ_isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_isram"; + }; + isram_clk: isram_clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "isram_clk"; + }; + occ_dbu: occ_dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "occ_dbu"; + }; + si_dbu_tp_pclk: si_dbu_tp_pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "si_dbu_tp_pclk"; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ_vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_vdi"; + }; + vdi_clk: vdi_clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "vdi_clk"; + }; + occ_can_ser: occ_can_ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + clock-output-names = "occ_can_ser"; + }; + can_ser_clk: can_ser_clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "can_ser_clk"; + }; + i2c_ser_clk: i2c_ser_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "i2c_ser_clk"; + }; +/* PLL_PER derivatives */ + occ_periph: occ_periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + clock-output-names = "occ_periph"; + }; + periph_clk: periph_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "periph_clk"; + }; + can_clk: can_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "can_clk"; + }; + spi_clk: spi_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "spi_clk"; + }; + uart_clk: uart_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "uart_clk"; + }; + i2c_clk: i2c_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio_clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc_sys_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf_ctrl_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ_mjpeg_core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm_clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg_core_clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu_a_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ_pci_sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi new file mode 100644 index 000000000000..0504c2fb3ad5 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +#include +#include + +/memreserve/ 0x40000000 0xc0000000; /* DDR32 */ +/memreserve/ 0x08000000 0x08000000; /* DDR_LOW */ + +#include "eyeq5-fixed-clocks.dtsi" + +/* almost all GIC IRQs has the same characteristics. provide short form */ +#define GIC_IRQ(x) GIC_SHARED (x) IRQ_TYPE_LEVEL_HIGH + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "mti,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + +/* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0_msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1_msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini_coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the_mhm_reserved_0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; + + timer { + compatible = "mti,gic-timer"; + interrupts = ; + clocks = <&core0_clk>; + }; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + olb: olb@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0 0xe00000 0x0 0x400>; + reg-io-width = <4>; + }; + + }; +}; From patchwork Wed Oct 4 16:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FC46E7C4DA for ; Wed, 4 Oct 2023 16:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243263AbjJDQLf (ORCPT ); Wed, 4 Oct 2023 12:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243289AbjJDQLJ (ORCPT ); Wed, 4 Oct 2023 12:11:09 -0400 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::228]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CC89109; Wed, 4 Oct 2023 09:11:02 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id C756B1BF207; Wed, 4 Oct 2023 16:10:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435861; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xelqXHCBbR0Afr1R7OtV1jiWI/pXI1JW1EUAz/IsmrY=; b=JpC0P08glaozT8Oq04At1NJCGr8LOReO617bSKDlLrnXivT/T/RQTxBL6EYRZiztaCuGNa eNsVNnyPw1RF/qraF/lQBkW26RBiqyqwndM0jwekhdCtAAqa4LoBn+MO+LIM5La6Jlj/Kg fmRpuXzL3c51620ez6yqLKZgdH8f36e1dAYmbQS65RDSGvzlItDEUN2B8TkDaqDdk9dAK1 SKDiejEZqDmxPrZuc0GOuVBzuMBBbJGHWxkuidxYNlxmqW3QFFnDY++VDe1Sm5Dx+DCYg2 OtMgjyaJcgyPCXmGiKXDkwPqmuDA1TNx6CdjlmpOdHtPqUhXzcKstiFPJ9d1+w== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 09/11] MIPS: mobileye: Add EPM5 device tree Date: Wed, 4 Oct 2023 18:10:36 +0200 Message-Id: <20231004161038.2818327-10-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add a device tree for the Mobileye EPM5 evaluation board. Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/Makefile | 2 ++ arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 24 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile index 99c4124fd4c0..539b2e1f4e07 100644 --- a/arch/mips/boot/dts/mobileye/Makefile +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # Copyright 2023 Mobileye Vision Technologies Ltd. +dtb-$(CONFIG_SOC_EYEQ5) += eyeq5-epm5.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts new file mode 100644 index 000000000000..ca03115a2858 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + bootargs = "cca=5 earlycon console=ttyAMA2 ddr32_alias=0x40000000"; + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x8 0x00000000 0x0 0x80000000>; + }; +}; + From patchwork Wed Oct 4 16:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8811EE7C4DE for ; Wed, 4 Oct 2023 16:11:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243275AbjJDQLf (ORCPT ); Wed, 4 Oct 2023 12:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243296AbjJDQLQ (ORCPT ); Wed, 4 Oct 2023 12:11:16 -0400 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1DC3115; Wed, 4 Oct 2023 09:11:04 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 8412F24000B; Wed, 4 Oct 2023 16:11:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435862; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BfYPq8UOKe/l5Lbfkqe1Q4Iz87qfHg7hyjqojqK5RzM=; b=oSHOOiIkpss4WGqXL/mS8ZHay5uvS0Vw7ZwtCcEMtjcAinBGWKBOgn27T6lQYgUNFbhJOx a4LBDf+2UExAaxubeYWGSFHm7dfWtZf+YJDqYK8v1860ijU4tf1PDP12aIOei7FaoU8QBv NrM8G07hXHinaY/3+7JpIXqUxa/5pJsyGCNlVfuZNgf5KOlcdBqlbmdXM6g3lWKLsImrWu 2uEc1ggXQRCY3nlEKQSxSi8q7Yup+vdclAjVohZ6Rvq6L3uxsi1bAJhp3MIL4J5cYpDgjU ulhraxgbIQPaI4YTBsaXcoaBB9foXEFdFMjvaS6K3nV1AdirLSNFQi1q1HSPWw== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 10/11] MIPS: generic: Add support for Mobileye EyeQ5 Date: Wed, 4 Oct 2023 18:10:37 +0200 Message-Id: <20231004161038.2818327-11-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Introduce support for the MIPS based Mobileye EyeQ5 SoCs. Signed-off-by: Gregory CLEMENT Signed-off-by: Arnd Bergmann Tested-by: Gregory CLEMENT --- arch/mips/configs/generic/board-eyeq5.config | 42 ++++++++++++++++++++ arch/mips/generic/Kconfig | 14 +++++++ arch/mips/generic/Platform | 2 + arch/mips/generic/board-epm5.its.S | 24 +++++++++++ 4 files changed, 82 insertions(+) create mode 100644 arch/mips/configs/generic/board-eyeq5.config create mode 100644 arch/mips/generic/board-epm5.its.S diff --git a/arch/mips/configs/generic/board-eyeq5.config b/arch/mips/configs/generic/board-eyeq5.config new file mode 100644 index 000000000000..946428318e15 --- /dev/null +++ b/arch/mips/configs/generic/board-eyeq5.config @@ -0,0 +1,42 @@ +CONFIG_HIGH_RES_TIMERS=y +CONFIG_TASKSTATS=y +CONFIG_FIT_IMAGE_FDT_EPM5=y +CONFIG_BOARD_EYEQ5=y +CONFIG_USE_XKPHYS=y +CONFIG_ZBOOT_LOAD_ADDRESS=0xA800000080480000 +CONFIG_CPU_HAS_MSA=y +CONFIG_NET_KEY=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_ENDPOINT=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_ROM=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_BLOCK2MTD=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_IPVLAN=y +CONFIG_MACB=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_CAN_M_CAN=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_FANOTIFY=y +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_PAGE_SIZE_16KB=y \ No newline at end of file diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig index 7dc5b3821cc6..9eb876a819c0 100644 --- a/arch/mips/generic/Kconfig +++ b/arch/mips/generic/Kconfig @@ -48,6 +48,12 @@ config SOC_VCOREIII config MSCC_OCELOT bool +config SOC_EYEQ5 + select WEAK_ORDERING + select WEAK_REORDERING_BEYOND_LLSC + select ARM_AMBA + bool + comment "FIT/UHI Boards" config FIT_IMAGE_FDT_BOSTON @@ -124,4 +130,12 @@ config VIRT_BOARD_RANCHU Android emulator. Android emulator is based on Qemu, and contains the support for the same set of virtual devices. +config FIT_IMAGE_FDT_EPM5 + bool "Include FDT for Mobileye EyeQ5 development platforms" + select SOC_EYEQ5 + default n + help + Enable this to include the FDT for the EyeQ5 development platforms + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. endif diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform index 2be9947814ad..447c42e1f676 100644 --- a/arch/mips/generic/Platform +++ b/arch/mips/generic/Platform @@ -29,3 +29,5 @@ its-$(CONFIG_FIT_IMAGE_FDT_JAGUAR2) += board-jaguar2.its.S its-$(CONFIG_FIT_IMAGE_FDT_SERVAL) += board-serval.its.S its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S its-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += board-marduk.its.S +its-$(CONFIG_FIT_IMAGE_FDT_EPM5) += board-epm5.its.S + diff --git a/arch/mips/generic/board-epm5.its.S b/arch/mips/generic/board-epm5.its.S new file mode 100644 index 000000000000..08e8c4f183d6 --- /dev/null +++ b/arch/mips/generic/board-epm5.its.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt-mobileye-epm5 { + description = "Mobileeye MP5 Device Tree"; + data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Mobileye EPM5 Linux kernel"; + kernel = "kernel"; + fdt = "fdt-mobileye-epm5"; + }; + }; +}; From patchwork Wed Oct 4 16:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 13408977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB42CE7C4DA for ; Wed, 4 Oct 2023 16:12:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243249AbjJDQMY (ORCPT ); Wed, 4 Oct 2023 12:12:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243307AbjJDQLX (ORCPT ); Wed, 4 Oct 2023 12:11:23 -0400 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1637D8; Wed, 4 Oct 2023 09:11:05 -0700 (PDT) Received: by mail.gandi.net (Postfix) with ESMTPSA id 0EBC760003; Wed, 4 Oct 2023 16:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1696435864; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wm36JSbVAUDkIx4csCo50tikiTYXJs3lG/TF9U0LJXc=; b=iFXBm38Jh0IUmcvxAckQnqBQLw/pn4Dw6yFwqjXM7p0VVng+QOlZjzNSmhjlhVEzgNDAdE Y734+xn/XEC9xqU/1VDZB9+Fiec2TwfKY0AmkZzlgh8IWKqg8SwxnADWkDRWvYFCqhRa4A zO+rs+X5aP6y8d7MhqIMAbBT/7MFf+BYnAzEs9nkXD4+DITcwKHH0bp8bZqfWHUzUt7NIW +uI7tV4VhtJnQKrW9qLwiVx6J/SZ+FMxtJRKfEes+7VYJubYj5ACtevlfD9p2u64F/BRRm tlzYpwqajKLGd58v/aX2VqwSFqh3LcPSFlABq+yON6qTNIHYFJ4FixkYZux+UQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH 11/11] MAINTAINERS: Add entry for Mobileye MIPS SoCs Date: Wed, 4 Oct 2023 18:10:38 +0200 Message-Id: <20231004161038.2818327-12-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231004161038.2818327-1-gregory.clement@bootlin.com> References: <20231004161038.2818327-1-gregory.clement@bootlin.com> MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Add Vlad, Théo and myself as co-maintainers for the Mobileye MIPS SoCs. Signed-off-by: Vladimir Kondratiev Signed-off-by: Gregory CLEMENT Signed-off-by: Théo Lebrun --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..6aedeab5f07c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14423,6 +14423,18 @@ W: http://palosaari.fi/linux/ Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/mn88473* +MOBILEYE MIPS SOCS +M: Vladimir Kondratiev +M: Gregory CLEMENT +M: Théo Lebrun +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: arch/mips/boot/dts/mobileye/ +F: arch/mips/configs/generic/board-eyeq5.config +F: arch/mips/generic/board-epm5.its.S +F: include/dt-bindings/soc/mobileye,eyeq5.h + MODULE SUPPORT M: Luis Chamberlain L: linux-modules@vger.kernel.org