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[75.72.166.104]) by smtp.gmail.com with ESMTPSA id d12-20020a92680c000000b00350b7a9f0c1sm71032ilc.62.2023.10.04.16.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 16:51:56 -0700 (PDT) From: Adam Ford To: linux-arm-kernel@lists.infradead.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , Geert Uytterhoeven , Magnus Damm , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH V3] arm64: dts: imx8mp-beacon: Configure 100MHz PCIe Ref Clk Date: Wed, 4 Oct 2023 18:51:47 -0500 Message-Id: <20231004235148.45562-1-aford173@gmail.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org There is a I2C controlled 100MHz Reference clock used by the PCIe controller. Configure this clock's DIF1 output to be used by the PCIe. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam --- V3: Update node names, clock-xtal25 and clock-generator per Shawn Guo V2: Remove the pcie0_refclk clock that the new one replaces. diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index ee64c6ffb551..0bea0798d2db 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -23,6 +23,12 @@ chosen { stdout-path = &uart2; }; + clk_xtal25: clock-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -118,12 +124,6 @@ led-3 { }; }; - pcie0_refclk: clock-pcie { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_audio: regulator-wm8962 { compatible = "regulator-fixed"; regulator-name = "3v3_aud"; @@ -273,6 +273,13 @@ pca6416_3: gpio@20 { interrupt-controller; #interrupt-cells = <2>; }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0241"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c3 { @@ -408,8 +415,9 @@ &pcie { }; &pcie_phy { + fsl,clkreq-unsupported; fsl,refclk-pad-mode = ; - clocks = <&pcie0_refclk>; + clocks = <&pcieclk 1>; clock-names = "ref"; status = "okay"; };