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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE3B.mail.protection.outlook.com (10.167.242.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Thu, 5 Oct 2023 10:28:12 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 5 Oct 2023 05:28:11 -0500 Received: from xhdpiyushm40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 5 Oct 2023 05:27:54 -0500 From: Piyush Mehta To: , , , , , , CC: , , , Piyush Mehta Subject: [PATCH] usb: dwc3: core: disable 3.0 clock when operating in 2.0 device mode Date: Thu, 5 Oct 2023 15:57:25 +0530 Message-ID: <20231005102725.8458-1-piyush.mehta@amd.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3B:EE_|SA1PR12MB7245:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a802b2a-5a69-496e-8717-08dbc58dc74e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 10:28:12.6992 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a802b2a-5a69-496e-8717-08dbc58dc74e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7245 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net The GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK bit enable the feature of internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock. This feature is applicable when core is operating in 2.0 device mode. When this bit is set in host mode and core is in 2.0 device mode (maximum speed = high-speed) then usb super speed devices not detected on host. To address the above issue added usb device mode conditional check. Fixes: 62b20e6e0dde ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode") Signed-off-by: Piyush Mehta --- DWC3 Register Map Link: https://docs.xilinx.com/r/en-US/ug1087-zynq-ultrascale-registers/GUCTL1-USB3_XHCI-Register Register Name GUCTL1 Bit: 26 Bit Name: DEV_FORCE_20_CLK_FOR_30_CLK --- drivers/usb/dwc3/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9c6bf054f15d..0cf1fe60628b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1202,6 +1202,7 @@ static int dwc3_core_init(struct dwc3 *dwc) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS; if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && + (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) && (dwc->maximum_speed == USB_SPEED_HIGH || dwc->maximum_speed == USB_SPEED_FULL)) reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;