From patchwork Tue Feb 12 16:24:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Ooi X-Patchwork-Id: 10808249 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 622CC13BF for ; Tue, 12 Feb 2019 16:25:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F5D72BF70 for ; Tue, 12 Feb 2019 16:25:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 438422BF78; Tue, 12 Feb 2019 16:25:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A60E52BF70 for ; Tue, 12 Feb 2019 16:25:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=vxbU5XAX5BaUomgRjfj/fCnAKyak02wuemnKkNamtOU=; b=YK/ mWaRw89/5sJ22AuJ6exFT0+TkQ15xt5TRAi9tI+zacXvA9I6n3xrQ/buSEu4bh69ICZYtfEXZ1oZU Q0rNKVHMSn8Gx7fQOtcDBOdl2W6aLBbREovsPgYkLGWEGQQ//OpuSLyQUwApe/6mmmmvej2hnChgG KK+hwZx6WLkOFPFDJoDtcVUsd0Rz9tboiO+n7LHo6pxWDiZlESNHElTcTBxa6Y4DqFjZCMmn+iqW/ 9jABv3vRbfnOU0xEFAGBoc1DWV1YiFEWMKMPRYOMd2tsFsdWwCaqXD7k2O/mNWGyeFnA6FDPjZ3RY PIC/JFV8b6jR1xXoOG4AXJsQx3UYbMQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gtarz-0006Z2-NZ; Tue, 12 Feb 2019 16:25:15 +0000 Received: from mga12.intel.com ([192.55.52.136]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gtarw-0006QT-E0 for linux-arm-kernel@lists.infradead.org; Tue, 12 Feb 2019 16:25:14 +0000 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Feb 2019 08:25:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,362,1544515200"; d="scan'208";a="318387067" Received: from joyceboo-mobl4.gar.corp.intel.com (HELO ubuntu.localdomain) ([10.255.147.184]) by fmsmga006.fm.intel.com with ESMTP; 12 Feb 2019 08:25:05 -0800 From: "Ooi, Joyce" To: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Maxime Coquelin Subject: [PATCH] net: stmmac: Add SMC support for EMAC System Manager register Date: Tue, 12 Feb 2019 08:24:52 -0800 Message-Id: <1549988692-4124-1-git-send-email-joyce.ooi@intel.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190212_082512_488822_2A6C6D8A X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, See Chin Liang , linux-kernel@vger.kernel.org, Joyce Ooi , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP As there is restriction to access to EMAC System Manager registers in the kernel for Intel Stratix10, the use of SMC calls are required and added in dwmac-socfpga driver. Signed-off-by: Ooi, Joyce --- .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 101 ++++++++++++++++++++ 1 files changed, 101 insertions(+), 0 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 5b3b06a..55cce97 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -15,6 +15,10 @@ * Adopted from dwmac-sti.c */ +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 +#include +#include +#endif #include #include #include @@ -52,6 +56,9 @@ struct socfpga_dwmac { int interface; u32 reg_offset; u32 reg_shift; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + u32 sysmgr_reg; +#endif struct device *dev; struct regmap *sys_mgr_base_addr; struct reset_control *stmmac_rst; @@ -61,6 +68,63 @@ struct socfpga_dwmac { struct tse_pcs pcs; }; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 +/**************** Stratix 10 EMAC Memory Controller Functions ************/ + +/* s10_protected_reg_write + * Write to a protected SMC register. + * @context: Not used + * @reg: Address of register + * @value: Value to write + * Return: INTEL_SIP_SMC_STATUS_OK (0) on success + * INTEL_SIP_SMC_REG_ERROR on error + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported + */ +static int s10_protected_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct arm_smccc_res result; + + arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0, + 0, 0, 0, &result); + + return (int)result.a0; +} + +/* s10_protected_reg_read + * Read the status of a protected SMC register + * @context: Not used + * @reg: Address of register + * @value: Value read. + * Return: INTEL_SIP_SMC_STATUS_OK (0) on success + * INTEL_SIP_SMC_REG_ERROR on error + * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported + */ +static int s10_protected_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct arm_smccc_res result; + + arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0, + 0, 0, 0, &result); + + *val = (unsigned int)result.a1; + + return (int)result.a0; +} + +static const struct regmap_config s10_emac_regmap_cfg = { + .name = "s10_emac", + .reg_bits = 32, + .val_bits = 32, + .max_register = 0xffffffff, + .reg_read = s10_protected_reg_read, + .reg_write = s10_protected_reg_write, + .use_single_read = true, + .use_single_write = true, +}; +#endif + static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed) { struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv; @@ -105,20 +169,43 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device * struct device_node *np = dev->of_node; struct regmap *sys_mgr_base_addr; u32 reg_offset, reg_shift; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + u32 sysmgr_reg = 0; +#endif int ret, index; struct device_node *np_splitter = NULL; struct device_node *np_sgmii_adapter = NULL; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + struct device_node *np_sysmgr = NULL; +#endif struct resource res_splitter; struct resource res_tse_pcs; struct resource res_sgmii_adapter; dwmac->interface = of_get_phy_mode(np); +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + sys_mgr_base_addr = devm_regmap_init(dev, NULL, (void *)dwmac, + &s10_emac_regmap_cfg); + if (IS_ERR(sys_mgr_base_addr)) + return PTR_ERR(sys_mgr_base_addr); + + np_sysmgr = of_parse_phandle(np, "altr,sysmgr-syscon", 0); + if (np_sysmgr) { + ret = of_property_read_u32_index(np_sysmgr, "reg", 0, + &sysmgr_reg); + if (ret) { + dev_info(dev, "Could not read sysmgr register address\n"); + return -EINVAL; + } + } +#else sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); if (IS_ERR(sys_mgr_base_addr)) { dev_info(dev, "No sysmgr-syscon node found\n"); return PTR_ERR(sys_mgr_base_addr); } +#endif ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); if (ret) { @@ -222,6 +309,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device * dwmac->reg_offset = reg_offset; dwmac->reg_shift = reg_shift; dwmac->sys_mgr_base_addr = sys_mgr_base_addr; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + dwmac->sysmgr_reg = sysmgr_reg; +#endif dwmac->dev = dev; of_node_put(np_sgmii_adapter); @@ -238,6 +328,9 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) int phymode = dwmac->interface; u32 reg_offset = dwmac->reg_offset; u32 reg_shift = dwmac->reg_shift; +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + u32 sysmgr_reg = dwmac->sysmgr_reg; +#endif u32 ctrl, val, module; switch (phymode) { @@ -266,7 +359,11 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) reset_control_assert(dwmac->stmmac_ocp_rst); reset_control_assert(dwmac->stmmac_rst); +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + regmap_read(sys_mgr_base_addr, sysmgr_reg + reg_offset, &ctrl); +#else regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); +#endif ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); ctrl |= val << reg_shift; @@ -284,7 +381,11 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); } +#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10 + regmap_write(sys_mgr_base_addr, sysmgr_reg + reg_offset, ctrl); +#else regmap_write(sys_mgr_base_addr, reg_offset, ctrl); +#endif /* Deassert reset for the phy configuration to be sampled by * the enet controller, and operation to start in requested mode