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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 16:41:56.7081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1062870-38cb-40be-5cbd-08dbc5c1fd0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8159 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige --- changes in v5: - None changes in v4: - None changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else From patchwork Thu Oct 5 16:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13410449 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89C07E71D4F for ; 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Thu, 5 Oct 2023 11:41:56 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , Thippeswamy Havalige Subject: [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Date: Thu, 5 Oct 2023 22:10:49 +0530 Message-ID: <20231005164051.984254-3-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|CO6PR12MB5460:EE_ X-MS-Office365-Filtering-Correlation-Id: ac938533-ca64-4dc3-dd55-08dbc5c2002c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bH/85l1i0zhKstRucMqGfEwPR/sctaJjnatUGWgUiWGzvsHgWZ+GqdOid3hU4ld9X0CNTxYiIRkKpVaWqL+pLLjAVNuApIkYf4xOIHLEpZMW7CP/fWL6qrtlJRDLlMQUKdSyjBMDt1hux5GzBElN+tcWjGD1OlrLVwnfnrNPqXuGUGCTVHjuDWpVtXMOWJYmQoZ46YCdJ1KOhFz/kIchpeJTc1BmlfCoZbBKgnhl8mM8v4Exsn4ERZgSA/lNZ4uol1DmjOD7QVjqPKcDQU8cBI85rPTf+LXKdbY+Y3IFrgOO6/adxXmzifRXLtEXCQzjwnDL0Hs1pHfJgYJbVgurWeiNSMQCubnv2+Gi7XdsJJf5J3fN+tyWIfUFG1TN1qeZXfuc4/K4Bm09Ay7t5fz/4lcsR92NS59DESYRLfiYY8uq30zLun/zIDBwQyXuLx5FBwhz3yo25ZBZiT6JRMWuj9BPaB1hVVh+95naX3px4Wus8r6YzkILD3oD9hv9SoC8xaYmPx4Bqu/WooQqarnidbMie3m4ushEzeOEjUgsSvhhvNUNr+3D/pAoDc7RDgO+p5rQ1I+b2UsssB26pT6kjcRd/G4h1lLBFqIC70MNcajXQ4cxAf8mo5xZLkqDkZMDRZs/oGt2LIQ0dfCfTx4eOldehRigUdvXnhLP+wQHRh4LoGJEf9eEzo3jI9YY0Mas7GRpaViWZrgZbEWY5M5Q/YiH3CTriq4lyLoEYIvIsbp+kyAi+Qylo69aBjodsYTkR7uepqZK0/mGtspV2rlhkL0FiAYHjqP5SFdLy1qhaFQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(230922051799003)(451199024)(64100799003)(1800799009)(82310400011)(186009)(46966006)(36840700001)(40470700004)(40460700003)(40480700001)(6666004)(478600001)(47076005)(36860700001)(356005)(86362001)(336012)(82740400003)(81166007)(70586007)(26005)(7416002)(2616005)(8936002)(426003)(5660300002)(1076003)(83380400001)(41300700001)(54906003)(8676002)(36756003)(44832011)(316002)(110136005)(70206006)(2906002)(4326008)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 16:42:01.9230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac938533-ca64-4dc3-dd55-08dbc5c2002c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5460 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update ECAM size in example to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige Acked-by: Rob Herring --- changes in v5: None changes in v4: None changes in v3: Remove period at end of subject line changes in v2: None. changes in v1: None. --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; From patchwork Thu Oct 5 16:40:50 2023 Content-Type: text/plain; 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Thu, 5 Oct 2023 09:42:03 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 5 Oct 2023 11:41:59 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , Thippeswamy Havalige Subject: [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro Date: Thu, 5 Oct 2023 22:10:50 +0530 Message-ID: <20231005164051.984254-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D4:EE_|SA0PR12MB4384:EE_ X-MS-Office365-Filtering-Correlation-Id: 6d55d85f-2eee-49f1-420f-08dbc5c20166 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d0yNuT0WGXFRawv6JgctPLFoRFyYM4DCebTwYnFbsb10ejEn9AV3fCk3QE0HmNITnoN5tVxFECu6y09c0EdgJlhvj9OG1kcsmApxvijrREKFByqlNzTvqPLsCZIROFlE4O51XALG66B6s6yHfO3ZAItcObmuNkcYXDh9SfEKbw+y2IyYFF/6PggVMwqgdhkaJj6ZM+wetYRSRzGO9wyZUlZPZx8ZMpW/Ga1c8l33JJ4aY9+VO4U3wRL2IUUvWS+GsU0zy2++ro7YS6Ig4NZ/9zysZ5BWEDj8udsDfEDvJG80BnE+4k+xEd5s1V6EMO6yVqyiXO+fCaPfC91dLDzxADQFXAJXMfaKpFBZ4d6gzQ0J3CW2AsfKzHTgvAvCJ+p7z8kNsDJtAuuiLFmcx/hY8AJgqJ0nAr8BtrIZOd5AEsbYjZaBbod6srKaMISgsqh0n01co7mOh7ZVHt9oZWLdesrvkdk09x3UCzF6hlyvqQLXpFUq+ktP23TBagD14lBCgzLsj+Z6qhTD0hKm1UbLnt3fZD6unLPYUPAb6mq4VodqDDgr6nslDsQHvBW2jvkPKIrkAVszit5torqLz0J9fprxKsyIdZDWgF6w9ZN4QTNcdu0K+A84C5zXOve+q9GlKzJ3Bl6kNc70Ak9cUt+FZDZFoQw8tQ2aPQtK0t39Ng7aVLzb4fZs0yi9EQri3je7CfCXuNL0H9JS+dDWaOCGaXz93Nwjzw90whCNHHlu7vSn/yOvi8hCnOtO4ukF6Xer5uVo0LSZh+9HRiwIs8AMjf6x5cLMPAkmD33KwhSbozg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(39860400002)(396003)(136003)(230922051799003)(82310400011)(451199024)(1800799009)(64100799003)(186009)(46966006)(40470700004)(36840700001)(7416002)(44832011)(5660300002)(8936002)(2906002)(8676002)(4326008)(41300700001)(70206006)(70586007)(2616005)(316002)(40460700003)(54906003)(110136005)(36860700001)(40480700001)(26005)(336012)(426003)(6666004)(36756003)(1076003)(86362001)(356005)(81166007)(82740400003)(83380400001)(47076005)(478600001)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 16:42:04.0082 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6d55d85f-2eee-49f1-420f-08dbc5c20166 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4384 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code Signed-off-by: Thippeswamy Havalige --- changes in v5: Remove period at end of subject line. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Thu Oct 5 16:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 13410452 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51DD5E71D4F for ; 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Thu, 5 Oct 2023 11:42:03 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , Thippeswamy Havalige Subject: [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 5 Oct 2023 22:10:51 +0530 Message-ID: <20231005164051.984254-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|IA1PR12MB7566:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9or5TypMO1/wkJGnRZopMkM4ubMavyraMdKunyT4VCs0jMZa1+r19CUhq77IkTBg4xcFKLT8bCLOnPSLbCj6IJPMcdnR7XylOLAfx2f/pPHOVm7RFNJxBVLfG5CGJi/5t5kYYU1NiHDOisXAbQ/X2ioqfcx832u5SgV6ELJi0lmCU0iiKdqi1BAfv8waXyTZnL0FpcuW1thKu2noxQzxHLURern9qTzuPl7dS4N+q/JVKVYw6xf5m2fgTWrbKPPEHp99XT1DP5yR73kmSaM2n6qbvyns6D4+Gh2VjBAlGarmPkU0SLCn5pGTEkPCGLbbFW9Xma43SmSIz1JprPfX9OTSPrjj8EXV+teYjD4H3ub6nczLMk/4p2PoTkUkHi48XWj2D8G4GDY7FHJdxtxA3U6rj5wYluVogjLFpRFWQTFicTj+1wIxo7ODBPrxS79cf/shi1+Qh/CHwPsMzkRtuUFQcigJhC7PPBBodkdpBueTDgXnMXFviMnqac9N5+xVitEfwoTMuN03y1fJC9FyoEzlqEqqG6gWIIHpRIvpBQUfQ1FJCCRtzw1pF3y1OX9LrENZL6JZ5pcKE7S7Q8puX8P47jk75wbt3+JI3SMfsexc0aX209ik6ApNOOB7ca/afWwhiMBejGchocGDOICMIxdBiLAje/ooHTHaijpkaHP/aBS7VYGlMo25vIQa1KV3EPJkGWNY5GlXN0SgcFGeSPoFV5dVAzOhv3knz6YnEOQTta86EdbfbvUBFqNsgmCXdNeB644MloLnBppfe6rqHfb+XY3dTuLIJuNIEmwXJL0= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(39860400002)(346002)(396003)(230922051799003)(1800799009)(186009)(451199024)(82310400011)(64100799003)(40470700004)(46966006)(36840700001)(40480700001)(40460700003)(2906002)(316002)(26005)(54906003)(426003)(83380400001)(44832011)(7416002)(1076003)(478600001)(336012)(2616005)(5660300002)(4326008)(70206006)(8676002)(6666004)(110136005)(47076005)(70586007)(8936002)(356005)(36860700001)(86362001)(4744005)(81166007)(41300700001)(36756003)(82740400003)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2023 16:42:07.9429 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7566 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)