From patchwork Fri Oct 6 15:07:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tretter X-Patchwork-Id: 13411669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59037E81E08 for ; Fri, 6 Oct 2023 15:07:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB4C610E51A; Fri, 6 Oct 2023 15:07:27 +0000 (UTC) Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6AD4110E519 for ; Fri, 6 Oct 2023 15:07:25 +0000 (UTC) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-2n; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:03 +0200 Subject: [PATCH v2 1/5] drm/bridge: samsung-dsim: add more mipi-dsi device debug information MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-1-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marco Felsch , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Frieder Schrempf , kernel@pengutronix.de, Adam Ford , Michael Tretter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Marco Felsch Since the MIPI configuration can be changed on demand it is very useful to print more MIPI settings during the MIPI device attach step. Signed-off-by: Marco Felsch Reviewed-by: Adam Ford #imx8mm-beacon Tested-by: Adam Ford #imx8mm-beacon Reviewed-by: Inki Dae Acked-by: Inki Dae Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch Signed-off-by: Michael Tretter --- Changes in v2: None --- drivers/gpu/drm/bridge/samsung-dsim.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index cf777bdb25d2..3e8ee9d73a72 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1712,7 +1712,10 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host, return ret; } - DRM_DEV_INFO(dev, "Attached %s device\n", device->name); + DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n", + device->name, device->lanes, + mipi_dsi_pixel_format_to_bpp(device->format), + device->mode_flags); drm_bridge_add(&dsi->bridge); From patchwork Fri Oct 6 15:07:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tretter X-Patchwork-Id: 13411666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEF59E81E06 for ; Fri, 6 Oct 2023 15:07:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 377DF10E518; Fri, 6 Oct 2023 15:07:23 +0000 (UTC) Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by gabe.freedesktop.org (Postfix) with ESMTPS id 876C810E516 for ; Fri, 6 Oct 2023 15:07:21 +0000 (UTC) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-5B; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:04 +0200 Subject: [PATCH v2 2/5] drm/bridge: samsung-dsim: reread ref clock before configuring PLL MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-2-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marco Felsch , Frieder Schrempf , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@pengutronix.de, Michael Tretter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The PLL reference clock may change at runtime when its parent clock changes. For example, this may happen on the i.MX8M Nano if the reference clock is a child of the Video PLL. If the pixel clock changes, this may propagate to the Video PLL and as a side effect change the reference clock. Thus, reading the clock rate during probe is not sufficient to correctly configure the PLL for the expected hs clock. Read the actual rate of the reference clock before calculating the PLL configuration parameters. Note that the "samsung,pll-clock-frequency" is always preferred and PLL reference clock is only read from the clock tree if that device tree property is not set. Reviewed-by: Inki Dae Acked-by: Inki Dae Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch Signed-off-by: Michael Tretter --- Changes in v2: - Clarify commit message --- drivers/gpu/drm/bridge/samsung-dsim.c | 16 +++++++++------- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 3e8ee9d73a72..392c023c5925 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -612,7 +612,12 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, u16 m; u32 reg; - fin = dsi->pll_clk_rate; + if (dsi->pll_clk) + fin = clk_get_rate(dsi->pll_clk); + else + fin = dsi->pll_clk_rate; + dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); + fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); if (!fout) { dev_err(dsi->dev, @@ -1822,18 +1827,15 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) u32 lane_polarities[5] = { 0 }; struct device_node *endpoint; int i, nr_lanes, ret; - struct clk *pll_clk; ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate, 1); /* If it doesn't exist, read it from the clock instead of failing */ if (ret < 0) { dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); - pll_clk = devm_clk_get(dev, "sclk_mipi"); - if (!IS_ERR(pll_clk)) - dsi->pll_clk_rate = clk_get_rate(pll_clk); - else - return PTR_ERR(pll_clk); + dsi->pll_clk = devm_clk_get(dev, "sclk_mipi"); + if (IS_ERR(dsi->pll_clk)) + return PTR_ERR(dsi->pll_clk); } /* If it doesn't exist, use pixel clock instead of failing */ diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 05100e91ecb9..31ff88f152fb 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -87,6 +87,7 @@ struct samsung_dsim { void __iomem *reg_base; struct phy *phy; struct clk **clks; + struct clk *pll_clk; struct regulator_bulk_data supplies[2]; int irq; struct gpio_desc *te_gpio; From patchwork Fri Oct 6 15:07:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tretter X-Patchwork-Id: 13411667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA8FBE81E07 for ; Fri, 6 Oct 2023 15:07:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8065010E50F; Fri, 6 Oct 2023 15:07:23 +0000 (UTC) Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9ACA510E516 for ; Fri, 6 Oct 2023 15:07:20 +0000 (UTC) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-7N; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:05 +0200 Subject: [PATCH v2 3/5] drm/bridge: samsung-dsim: update PLL reference clock MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marco Felsch , Frieder Schrempf , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@pengutronix.de, Michael Tretter Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The PLL requires a clock frequency in a certain platform-dependent range after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to the upper limit before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Reviewed-by: Marco Felsch Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Signed-off-by: Michael Tretter --- Changes in v2: - Specify limits for the PLL input clock in samsung_dsim_driver_data --- drivers/gpu/drm/bridge/samsung-dsim.c | 27 +++++++++++++++++++++++++-- include/drm/bridge/samsung-dsim.h | 2 ++ 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 392c023c5925..16c8326d921b 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -410,6 +410,8 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .pll_fin_min = 6, + .pll_fin_max = 12, .m_min = 41, .m_max = 125, .min_freq = 500, @@ -426,6 +428,8 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .pll_fin_min = 6, + .pll_fin_max = 12, .m_min = 41, .m_max = 125, .min_freq = 500, @@ -440,6 +444,8 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { .num_bits_resol = 11, .pll_p_offset = 13, .reg_values = reg_values, + .pll_fin_min = 6, + .pll_fin_max = 12, .m_min = 41, .m_max = 125, .min_freq = 500, @@ -455,6 +461,8 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { .num_bits_resol = 12, .pll_p_offset = 13, .reg_values = exynos5433_reg_values, + .pll_fin_min = 6, + .pll_fin_max = 12, .m_min = 41, .m_max = 125, .min_freq = 500, @@ -470,6 +478,8 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .num_bits_resol = 12, .pll_p_offset = 13, .reg_values = exynos5422_reg_values, + .pll_fin_min = 6, + .pll_fin_max = 12, .m_min = 41, .m_max = 125, .min_freq = 500, @@ -489,6 +499,8 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { */ .pll_p_offset = 14, .reg_values = imx8mm_dsim_reg_values, + .pll_fin_min = 2, + .pll_fin_max = 30, .m_min = 64, .m_max = 1023, .min_freq = 1050, @@ -612,10 +624,21 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, u16 m; u32 reg; - if (dsi->pll_clk) + if (dsi->pll_clk) { + /* + * Ensure that the reference clock is generated with a power of + * two divider from its parent, but close to the PLLs upper + * limit. + */ + fin = clk_get_rate(clk_get_parent(dsi->pll_clk)); + while (fin > driver_data->pll_fin_max * MHZ) + fin /= 2; + clk_set_rate(dsi->pll_clk, fin); + fin = clk_get_rate(dsi->pll_clk); - else + } else { fin = dsi->pll_clk_rate; + } dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 31ff88f152fb..3370f66ea80a 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -60,6 +60,8 @@ struct samsung_dsim_driver_data { unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + unsigned int pll_fin_min; + unsigned int pll_fin_max; u16 m_min; u16 m_max; }; From patchwork Fri Oct 6 15:07:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tretter X-Patchwork-Id: 13411665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85D22E81E07 for ; Fri, 6 Oct 2023 15:07:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C36E410E516; Fri, 6 Oct 2023 15:07:21 +0000 (UTC) Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9B58810E518 for ; Fri, 6 Oct 2023 15:07:20 +0000 (UTC) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-Ac; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:06 +0200 Subject: [PATCH v2 4/5] drm/bridge: samsung-dsim: adjust porches by rounding up MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-4-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marco Felsch , linux-kernel@vger.kernel.org, Frieder Schrempf , Michael Tretter , dri-devel@lists.freedesktop.org, kernel@pengutronix.de, Adam Ford Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Rounding the porches up instead of down fixes the samsung-dsim at some more resolutions and refresh rates: The following resolutions are working with rounded-up porches, but don't work when the porches are rounded down: 1920x1080-59.94 1920x1080-30.00 1920x1080-29.97 1920x1080-25.00 1680x1050-59.88 1280x1024-75.02 1200x960-59.99 1280x720-50.00 1024x768-75.03 1024x768-60.00 640x480-60.00 640x480-59.94 Reviewed-by: Adam Ford #imx8mm-beacon Tested-by: Adam Ford #imx8mm-beacon Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch Signed-off-by: Michael Tretter --- Changes in v2: - Rephrase commit message --- drivers/gpu/drm/bridge/samsung-dsim.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 16c8326d921b..714e1e833606 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -987,9 +987,9 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { int byte_clk_khz = dsi->hs_clock / 1000 / 8; - int hfp = (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock; - int hbp = (m->htotal - m->hsync_end) * byte_clk_khz / m->clock; - int hsa = (m->hsync_end - m->hsync_start) * byte_clk_khz / m->clock; + int hfp = DIV_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk_khz, m->clock); + int hbp = DIV_ROUND_UP((m->htotal - m->hsync_end) * byte_clk_khz, m->clock); + int hsa = DIV_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk_khz, m->clock); /* remove packet overhead when possible */ hfp = max(hfp - 6, 0); From patchwork Fri Oct 6 15:07:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Tretter X-Patchwork-Id: 13411668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D407E81E06 for ; Fri, 6 Oct 2023 15:07:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62ACB10E51B; Fri, 6 Oct 2023 15:07:27 +0000 (UTC) Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB8B810E518 for ; Fri, 6 Oct 2023 15:07:21 +0000 (UTC) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-D3; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:07 +0200 Subject: [PATCH v2 5/5] drm/bridge: samsung-dsim: calculate porches in Hz MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-5-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marco Felsch , linux-kernel@vger.kernel.org, Frieder Schrempf , Michael Tretter , dri-devel@lists.freedesktop.org, kernel@pengutronix.de, Adam Ford Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Calculating the byte_clk in kHz is imprecise for a hs_clock of 55687500 Hz, which may be used with a pixel clock of 74.25 MHz with mode 1920x1080-30. Fix the calculation by using HZ instead of kHZ. This requires to change the type to u64 to prevent overflows of the integer type. Reviewed-by: Adam Ford #imx8mm-beacon Tested-by: Adam Ford #imx8mm-beacon Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch Signed-off-by: Michael Tretter --- Changes in v2: None --- drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 714e1e833606..63a0d8dbe37c 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -986,10 +986,12 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { - int byte_clk_khz = dsi->hs_clock / 1000 / 8; - int hfp = DIV_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk_khz, m->clock); - int hbp = DIV_ROUND_UP((m->htotal - m->hsync_end) * byte_clk_khz, m->clock); - int hsa = DIV_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk_khz, m->clock); + u64 byte_clk = dsi->hs_clock / 8; + u64 pix_clk = m->clock * 1000; + + int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); + int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); + int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); /* remove packet overhead when possible */ hfp = max(hfp - 6, 0);