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Fri, 06 Oct 2023 17:41:19 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id x16-20020a170902ec9000b001c582de968dsm4534540plg.72.2023.10.06.17.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 17:41:19 -0700 (PDT) From: Charlie Jenkins Date: Fri, 06 Oct 2023 17:41:06 -0700 Subject: [PATCH v2 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Message-Id: <20231006-module_relocations-v2-1-47566453fedc@rivosinc.com> References: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> In-Reply-To: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 24CE9180008 X-Rspam-User: X-Rspamd-Server: rspam11 X-Stat-Signature: qepeugyf44e7h8714ypcrx7t7oxw8rgm X-HE-Tag: 1696639280-250185 X-HE-Meta: U2FsdGVkX1/fvmQTpkBaUzwJmzA8TwnsqF/XOgvqyvPb91RlXb8WGWWYq7h/KAvejBqVpAUoxIUFFVLYP5wbNceXmSVJVxqo22lRc3XEf5FYfXDmXUkgK7RLdQ0tzeqe2NsEQkNOuiDNweEVTA5zFWCka3aveYQSHL5PLOc4fsKnkPtl//BMw+DPjyCa6YEE5bsm2k9k94P5nfL3xyMH6CIS0v20VD+qDfIY0b7ywr3dcL+f0FfEO9OUSv2LHJ1/rpVGeNXC7of97tiQ1W7I9gFR69Y0k2j/4/7c4mXF473Nm1EMBKsUZcA42afVXk0j7Sp9Rkl4I2CJqlu/975sfjCCiGdkjSg37nYWz7ZVGrEeNAM5YvQRwYWfrABf+2Oi/gImSlxcr5UBcVAsH4jJPQeTTa+4ZCi8dzmoFcSPeu4131iLwy1DfZJmwqJApz45Spd/yHJNg6A2KEGOwxQMTXh6PcO8qhvUrinZWPuECfx+dBzGjCuCrovkb4Pcx2Vcws6jsiVK/Tp8BQBo2Mczr4ZaJ/bEfX9qgvFrUheWJmy97h5nZI8soSt6I4r6v16D56XQx5kysmcDA8LqeA389MGlb+xxCCr4fQqsfJMU6PDK/O/gaHfZjihJYc1Xsximu7jGXIQ2gdyiJSOVrm+Gyhj1aaZ9QJGt/Z1+i/7eLBG0FcicO5fjKRcmg1mzpQ6FNGXNDjYAIdeu7mBH9IMWIfQbpXpY0qtQpJdjgkESCokV2ix9F3RJbWrbFD31WYQ+PY1IkSOE8WEn6bchxms4cJxCaLccTGNtZbY0aA60pMe0uu3/J6TRpj0atCKcbElLUItPMWjwXxQokaQ7koYlOeEez62taQL552lhvOdv1Jz9vDNG5gt+UYxRZha43e6DxgIW4DfSRY837g4F87n8U74c8UBFuTG1qry3Mx0XAtDh+I1f/C9Ei7vBu8RHI3RcJzY68ehtsRd0RMdBVOH IKd6Zh6z 7AXiWFy72lYZddbFc8jA/Mt3YZdJ+KfOADaMwDEg35OR8sz4Ln5ix42olZdr9TCq8QWz+vziSoT/2fn1aizSulYUBGkTUEoePR//yztbPuYNFVWlyqwLWEQpPdlmhwno5chQ1JEr81m4ryI7jjbpQO1vXRlDfFsqzhLBuv9vBLoUTX6bFjiDHxzaZyR+XISycjhTU1zSRbOw7cfx9kD9aJnQX44bnACEqOp1vn1e3yvvkil2LSkXgKBjQkJE/SHwAf+v0/Zsdmgb0RG4quykkBFaHa3+H+0O7vbNhN3KQikkTsoCGaK2YSxX/YmjsISZMs91lfhBjg+f3B6yQ6ErQ40yAYHBOUnCZ6AnQoGJQQcnxhy3Fi7xy4QlNHtjloaWcpm4CXdGZrBWQnb6gMC5OYMO+upJzQS8zBygneTCnqkGQaZaZb1CICYhDNtOrBDP12dSmCLRd0Tv+Y8A= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000361, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 6 +- arch/riscv/kernel/module.c | 247 ++++++++++++++++++++++++++++++++++---- 2 files changed, 227 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..a9307a1c9ceb 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 +#define R_RISCV_RVC_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +94,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..61d5cdbe609d 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -253,6 +254,30 @@ static int apply_r_riscv_call_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_rvc_lui_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + // Get high 6 bits of 18 bit absolute address + s32 imm = ((s32)v + 0x800) >> 12; + + if (v != sign_extend32(v, 6)) { + pr_err("%s: target %016llx can not be addressed by the 6-bit offset from PC = %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + + if (imm == 0) { + // imm = 0 is invalid for c.lui, convert to c.li + *location = (*location & 0x0F83) | 0x4000; + } else { + u16 imm17 = ((((s32)v + 0x800) & 0x20000) >> (17 - 12)); + u16 imm16_12 = ((((s32)v + 0x800) & 0x1f000) >> (12 - 2)); + *location = (*location & 0xef83) | imm17 | imm16_12; + } + + return 0; +} + static int apply_r_riscv_relax_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -268,6 +293,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location += (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +320,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +347,150 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) = { - [R_RISCV_32] = apply_r_riscv_32_rela, - [R_RISCV_64] = apply_r_riscv_64_rela, - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, - [R_RISCV_JAL] = apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] = apply_r_riscv_call_rela, - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location = (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + if (v >= 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC = %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *location = v; + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) = { + [R_RISCV_32] = apply_r_riscv_32_rela, + [R_RISCV_64] = apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, + [R_RISCV_COPY] = dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, + [R_RISCV_JAL] = apply_r_riscv_jal_rela, + [R_RISCV_CALL] = apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, + [R_RISCV_TLS_GD_HI20] = tls_not_supported, + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] = tls_not_supported, + [R_RISCV_TPREL_LO12_I] = tls_not_supported, + [R_RISCV_TPREL_LO12_S] = tls_not_supported, + [R_RISCV_TPREL_ADD] = tls_not_supported, + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, + [R_RISCV_RVC_LUI] = apply_r_riscv_rvc_lui_rela, + /* 47-50 reserved for future standard use */ + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, + [R_RISCV_SET6] = apply_r_riscv_set6_rela, + [R_RISCV_SET8] = apply_r_riscv_set8_rela, + [R_RISCV_SET16] = apply_r_riscv_set16_rela, + [R_RISCV_SET32] = apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] = apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] = apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -425,6 +581,47 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, me->name); return -EINVAL; } + } else if (type == R_RISCV_SUB_ULEB128) { + unsigned long set_loc; + u32 set_type; + unsigned long set_sym_val; + + bool has_corresponding_relocation = false; + + /* R_RISCV_SET_ULEB128 must appear before the SUB */ + for (unsigned int j = i; j >= 0; j--) { + set_loc = sechdrs[sechdrs[relsec].sh_info] + .sh_addr + + rel[j].r_offset; + set_type = ELF_RISCV_R_TYPE(rel[j].r_info); + + /* + * Find the SET relocation that is targeting the + * same position as the SUB + */ + if (set_type == R_RISCV_SET_ULEB128 && + set_loc == (unsigned long)location) { + Elf_Sym *corresponding_sym = + (Elf_Sym *)sechdrs[symindex] + .sh_addr + + ELF_RISCV_R_SYM(rel[j].r_info); + + set_sym_val = + corresponding_sym->st_value + + rel[j].r_addend; + has_corresponding_relocation = true; + break; + } + } + + if (has_corresponding_relocation) { + /* Calculate set and subtraction */ + v = set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with a R_RISCV_SET_ULEB128 that comes before it. PC = %p\n", + me->name, location); + return -EINVAL; + } } res = handler(me, location, v); From patchwork Sat Oct 7 00:41:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13412111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACCF8E9413E for ; Sat, 7 Oct 2023 00:41:26 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 532348001E; Fri, 6 Oct 2023 20:41:24 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 4E33380008; Fri, 6 Oct 2023 20:41:24 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 35BE98001E; Fri, 6 Oct 2023 20:41:24 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id 2509C80008 for ; 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Fri, 06 Oct 2023 17:41:20 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id x16-20020a170902ec9000b001c582de968dsm4534540plg.72.2023.10.06.17.41.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 17:41:20 -0700 (PDT) From: Charlie Jenkins Date: Fri, 06 Oct 2023 17:41:07 -0700 Subject: [PATCH v2 2/2] riscv: Add tests for riscv module loading MIME-Version: 1.0 Message-Id: <20231006-module_relocations-v2-2-47566453fedc@rivosinc.com> References: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> In-Reply-To: <20231006-module_relocations-v2-0-47566453fedc@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 026221C0005 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: zcoo34wccfdjtzq16hc4zgefpsnynm1h X-HE-Tag: 1696639281-1322 X-HE-Meta: U2FsdGVkX197jtPzF/jsRBnLWY0he5oEiQhjCvcHwMt7RDqR1tkqM7lgi7njUQXtap6zWXSEyxPUMd3lvYhD8QsnsBosbPRtO3cu4hx4KNq9gbb6mmygU8dQPvqHSAiZ1llGdRGEf+oqIt7rRM6eTNnwXb5eo0QM4P6/VduXqYWQU7EIZr3dOPH21ywhVyi1QC0ygknmCepAl3tDxsW5mbyLxgbQYvCEAR44ro/QWMozi4xLVDf9gdzjsvLEryj4i+FecXFjIAYM0zTYQEZgtje4jLnfwPR5xmZQTw2N8waoYn84XfmS6VEaWW29Uotqv5EgsHfJ8yU8UI5sbB/5v/8ZZ0SvQ277HDGftzd9p8QDu/CRrdEZGgUEvsKLYa5HjeCTiK2MVz8fozZfo+OFbeAaStK8RlkyXVZ52ufmYAKH52I/O8vLBJhZJMY7O93STg40Nj+VayLtRUU5y8TE6jvvDpKW0Y0HUuL4b2hmxeTGQTjhVXlixP/AcSbHLp9eVso2SFjDr6VE+F+y3rfslWk3jSjCy1yWSILMUDOKjaQ3+/JIVLGkmPXelSN9jn8sPzq0tUjvtpxLeB0IztF7OT1ZY4vJ3QJjCK6vIAyTEJ3a0nosSY5+4Mm0yHu4CLOuxcG92w3dbyUG51LtZKD2g5cA2PNpvE2deidtzi+lAupKEU7Bd3Pqy2tHKlY/M8eTkLJ+0VJzBo3puPAEhvyN8HtAoFVIDcJUNnEHHiLT6b3inGYAeGn5cZNob4MNBzxnYrwD9VYr7vrfLPZq41tGVdnfSvQFTjK+J/MfOitCRNXxZoyE7qG8smY1fb8wpsVcg9vbvw6e1msHBRT4zJCPILG/o82Kb4ZsxLDSRGNgW7cgc/uIlHGNZWnsWEewwHO7r70pHUnia4DMACMMOu4WXYB6bK6gK0Gi/aeW2kHvehTAqbEkxJO12J61NQGPIB7daul5MhRg9JwIfQ75bRY fERQmJyb B4q9yciHWzm/VMKPK1Gv7RzijF7QgZss5URX1s3hq0cSq9wenCujy7ACsn2wfg8xQqy1l8tc3pyGBHX16p52+pyGuWr83hVNWwcZq+1oRTl/AOLSQk+Rekq3FoM4JYgu1fWpHXILtcDYbqcAnz91tMU+tDIImtU5cdC/QRlpVEO+Pn1GPVBYWm+EpwT8zw5jwf71dDyLvcG8ls5oSQytkW+r2ELosnpZTaZLaQiY9HIGM550nwmSPEF0rD5Sy+K6jisHqqs6NaoeC6LzMWN3meJDpvbMX72v4ZYBl5yhjQHQ8tHbnWJ6PuOfx+njwVNahZvsKgTPT0P22knC2VUkVjm9VFBKXdH6h9GAa1frBmTdwE2k/ExS8hOTLeGI+z9xvU/7oBy7h9kNiNThv+OEjLgLA70R26C0m/TKfagpo4AVjy+WIUzbLOpI6qASTp8IPTnwCkRDjeAe553N7dzzNVQpo6PpMl8d2uOPMyuBdHSZkYd5DzVZplyvOWOR8/4qtFIc9LjKoU3CuSAA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000106, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128 which is a bit different because SUB and SET are required to happen together. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 32 ++++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 +++++ .../tests/module_test/test_module_linking_main.c | 73 ++++++++++++++++++++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 ++++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 ++++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 +++++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 20 ++++++ 16 files changed, 347 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ +obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug new file mode 100644 index 000000000000..05ca55fb4645 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug log + in TAP format (http://testanything.org/). Only useful for kernel devs + running the KUnit test harness, and not intended for inclusion into a + production build. + + For more information on KUnit and unit tests in general please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Makefile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kernel/tests/module_test/Makefile new file mode 100644 index 000000000000..cacd50cd1127 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m += test_module_linking.o + +test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o + +test_set := test_set6.o test_set8.o test_set16.o test_set32.o + +test_uleb := test_uleb128.o + +test_module_linking-objs += $(test_sub) + +test_module_linking-objs += $(test_set) + +test_module_linking-objs += $(test_uleb) + +test_module_linking-objs += test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..c142c2657d0c --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); +extern int test_uleb(void); + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test) +{ + int val32 = test_set32(); + int val16 = test_set16(); + int val8 = test_set8(); + int val6 = test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 = test_sub64(); + int val32 = test_sub32(); + int val16 = test_sub16(); + int val8 = test_sub8(); + int val6 = test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_uleb(struct kunit *test) +{ + int valuleb = test_uleb(); + + CHECK_EQ(valuleb, 0); +} + +static struct kunit_case __refdata riscv_module_linking_test_cases[] = { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), + KUNIT_CASE(run_test_uleb), + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite = { + .name = "riscv_checksum", + .test_cases = riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/kernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/kernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/kernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/kernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..db9f301092d0 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb +test_uleb: + ld a0, second + addi a0, a0, -127 + ret +.data +first: + .rept 127 + .byte 0 + .endr +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0