From patchwork Sun Oct 8 06:23:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B62ACE95A67 for ; Sun, 8 Oct 2023 06:27:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCr-00084f-IZ; Sun, 08 Oct 2023 02:24:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCo-000834-2B for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:58 -0400 Received: from mout.kundenserver.de ([212.227.17.24]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCl-0007je-UU for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:57 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MN4qp-1r8HdN0PG1-00IzKn; Sun, 08 Oct 2023 08:23:52 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Laurent Vivier Subject: [PULL 01/20] q800-glue.c: convert to Resettable interface Date: Sun, 8 Oct 2023 08:23:30 +0200 Message-ID: <20231008062349.2733552-2-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:+lJL08/qeSbH7s6Z0vBod0TfLv6gmbLFH0LCl82OaUr1Rh6fGUg mDNYeB1By4DGTTSivNccVomp0iRuqB3uXXtfdcLfnL1w/zRW+iC66dTTZ1ZoM3DVZk9ouF3 P4pKTwmGvsdBme32POg5B5nZzScKMYM9QEDqnTGW3NAPPrkxDrPh9fL/QaLAzH8YfmaKU9a 7PEjxG78WmN1FbeGTn8yw== UI-OutboundReport: notjunk:1;M01:P0:58aXnF3sjWo=;vBxjtR8iXKjdBezr43Qd/rm6njB t/Xf0l3HovAvjmE4zkoQH64Z5Bpvach1tsleAx15FhpDcUjKXv91p3Biq2gbW1U4tUIGXQmkb v2UFR/WukJgG+sam13VuDMrSDa0Ck+WMg6SlkiDerxmTagUMWKIDchi4T+gCwnRUejEnNLplK IoEsUyxzBt3QwaJJ+25au0pYAgfL0/69W7RewkqNkcSnrgA/UxgpKIAzspn0XgMJ5W+S+/0Dj kweQ1YSGxQ4sHOUJuKehn+PCixwM09vC9eyuv772lpsM/nZXbFecStHjO6eiTKm4PQMMSRQkU lL014K8rZ+HwvcIUAcuMwSUe9MkUHoBlPkx587g//sU3ACSB4JhRMg41HDe5N0Ar8MONP773P Qdvrt36BHKFodkN5KybrVU4SXEtiEW4pRdghHEt1bRgYMT0IJxruzDvBIayyPY6G4h6hJVtAI 0sEoGxGObPYr1TagboeAfQMXrpvEY3h6233slc9RFd0N6SO9rVMnvDrflk37hWkmvQsNYsA/A 2fmSIlGeFGVykVtD0YK52uz5ASt3qUquqfW8U/JMAftAmTQMBgc7wpIAcwXfHlnCJuA8qYcDe vXhEWfcWN/WwWqfb2Uwa9t064Zfm20zcj3fGFh0hXLc4SbOq5VrzHp8UBmCxq9/Db1KMiYwyN uyvoLY7u5cvA+7M8a9zxI1jqLiykGq5no0GvPdC8QEWcJosBx6IIZH5dCV8gxSWLvJ8NQXmqZ 2JerpcBjF8F+7mJ85xFVBOGlhwr2BHMtxJDxL8kFXClSIJaiapEnyvoiIxbQ5Q2ctUA5ces8a /UGh5fmlqVrpoXnqtRRGD5i04ObbC8lbUewudznti6KawY5A+fa9hQ/OiOfjP6K1gMyxcw/lM JgKo1QBcXr29+aA== Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland Convert the GLUE device to 3-phase reset. The legacy method doesn't do anything that's invalid in the hold phase, so the conversion is simple and not a behaviour change. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/m68k/q800-glue.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c index 34c4f0e9876d..710a5c331ec9 100644 --- a/hw/m68k/q800-glue.c +++ b/hw/m68k/q800-glue.c @@ -166,9 +166,9 @@ static void glue_nmi_release(void *opaque) GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0); } -static void glue_reset(DeviceState *dev) +static void glue_reset_hold(Object *obj) { - GLUEState *s = GLUE(dev); + GLUEState *s = GLUE(obj); s->ipr = 0; s->auxmode = 0; @@ -223,11 +223,12 @@ static void glue_init(Object *obj) static void glue_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); NMIClass *nc = NMI_CLASS(klass); dc->vmsd = &vmstate_glue; - dc->reset = glue_reset; device_class_set_props(dc, glue_properties); + rc->phases.hold = glue_reset_hold; nc->nmi_monitor_handler = glue_nmi; } From patchwork Sun Oct 8 06:23:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412581 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE853E95A67 for ; Sun, 8 Oct 2023 06:26:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCp-00083p-Cn; Sun, 08 Oct 2023 02:23:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCn-00082o-7Z for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:57 -0400 Received: from mout.kundenserver.de ([212.227.17.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCl-0007jv-1y for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:56 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1M4aEC-1qpvR82X6U-001jQs; Sun, 08 Oct 2023 08:23:52 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 02/20] q800: add djMEMC memory controller Date: Sun, 8 Oct 2023 08:23:31 +0200 Message-ID: <20231008062349.2733552-3-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:V9XnxqbUOTs9WRHhz9b5KSERGBklgU8iuIw0a6DD3gs7/VCw46w g+ewzIANybcPqnaPQFCMkmOStaTHreLMIv0aQDBPYxAoLdIER7WvMU6xYoJ6KruTZV/IoEf D+daK01+obO3+c8BEA24XSPlMvjtVHS5y3xAd8JmiGphJhOtHVqOfq0xNXUQLj1ClkYxEQQ rfwSbfI/zg/EjX9y05f8g== UI-OutboundReport: notjunk:1;M01:P0:aXKmiEmrYuM=;KHsaXgb9lOJBxo7eKWdtcn5SARd 1meW/cFWZn47Dp63Qhp0rnX1fufmABgktKWxLEFRJyTumYeU4WjzMpxNtxGuB/RM9U52JayEf dJBnKnrJJ6imJC+AzmFM/WHaaN1uVEXozIsITgRUVmKoMorJP3MLijtNiLwZxPhFcPp2MnIps f/Yf9LEDkPVteKH2lbxMQcMY+oG1tNwQDJ2QlHp0tihFDkvM+7cBkI1MkPJGrscqA7gb7Bugu prtTCOId0bsXyOf5Wwrbb5ZhnnwWFfh/sjIgNQgNfDn28834/FimWk6OOfMlhzeXtYfHF19+j gPm9R+JFcPzz6S009EMUr815iKRxmCSG5bHTGBdkBXR2NGrGhYQRHM7WwjLBl6+aqcLGMRap5 B4XWuN5wRRofzQ+auqa+vqYIpp7jow0idj+04wbrBgiIVptAdy+M0kttcDyYkjnREA1sTYiOl 7B28JcEkNUQILGsMYJ7wvyQQPChBwDubX0xj2KNP0DFxe9jYVHIPAzYTaOJkeIC7rA+aJN/dq tfGtv+3eSys6Rr3uQZKah2FzV28Tu40thREiOv883BpUGAR8YBcc5x+L4pQSy82kLBxaXiU3b TDL97pNnubohMQP1/bQLW5shxt+T7ISSLU6gGHtGJpWhJxMc3cyUsy1s2erK3EK6CM1BuAicK JIoEdIBlcDp1ktLN/L0SWE/8fSkVMLn/rPVNEd84RP5DR7qF5bluyKlFJadSmtnQVMne6uMDt ZFEvCed58gBbc/wm8q9ajypieJ+pDK1WiMZXakCS+0Z/cwnukI71rWLmwhrgEsm+RJVY913n1 /BRtgcd3zXabgbZ5imlZVsAQdY4cHYiOaAVmG9dR/Pcbgj/MYHcq0f2L537Jd9mngcTFT8TAC AZnDzxhJfCNXxTw== Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The djMEMC controller is used to store information related to the physical memory configuration. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231004083806.757242-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- MAINTAINERS | 2 + include/hw/m68k/q800.h | 2 + include/hw/misc/djmemc.h | 30 +++++++++ hw/m68k/q800.c | 10 +++ hw/misc/djmemc.c | 135 +++++++++++++++++++++++++++++++++++++++ hw/m68k/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/trace-events | 4 ++ 9 files changed, 188 insertions(+) create mode 100644 include/hw/misc/djmemc.h create mode 100644 hw/misc/djmemc.c diff --git a/MAINTAINERS b/MAINTAINERS index ea91f9e80481..dead0d4a47e3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1229,6 +1229,7 @@ F: hw/misc/mac_via.c F: hw/nubus/* F: hw/display/macfb.c F: hw/block/swim.c +F: hw/misc/djmemc.c F: hw/m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo-mac.h @@ -1238,6 +1239,7 @@ F: include/hw/display/macfb.h F: include/hw/block/swim.h F: include/hw/m68k/q800.h F: include/hw/m68k/q800-glue.h +F: include/hw/misc/djmemc.h virt M: Laurent Vivier diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index b3d77f1cba6e..f6ae4c1c4fd5 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -36,6 +36,7 @@ #include "hw/block/swim.h" #include "hw/nubus/mac-nubus-bridge.h" #include "hw/display/macfb.h" +#include "hw/misc/djmemc.h" /* * The main Q800 machine @@ -56,6 +57,7 @@ struct Q800MachineState { Swim swim; MacNubusBridge mac_nubus_bridge; MacfbNubusState macfb; + DJMEMCState djmemc; MemoryRegion macio; MemoryRegion macio_alias; }; diff --git a/include/hw/misc/djmemc.h b/include/hw/misc/djmemc.h new file mode 100644 index 000000000000..82d4e4a2fee2 --- /dev/null +++ b/include/hw/misc/djmemc.h @@ -0,0 +1,30 @@ +/* + * djMEMC, macintosh memory and interrupt controller + * (Quadra 610/650/800 & Centris 610/650) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_DJMEMC_H +#define HW_MISC_DJMEMC_H + +#include "hw/sysbus.h" + +#define DJMEMC_SIZE 0x2000 +#define DJMEMC_NUM_REGS (0x38 / sizeof(uint32_t)) + +#define DJMEMC_MAXBANKS 10 + +struct DJMEMCState { + SysBusDevice parent_obj; + + MemoryRegion mem_regs; + + /* Memory controller */ + uint32_t regs[DJMEMC_NUM_REGS]; +}; + +#define TYPE_DJMEMC "djMEMC" +OBJECT_DECLARE_SIMPLE_TYPE(DJMEMCState, DJMEMC); + +#endif diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index b770b71d5475..f9ecc1fbb094 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -40,6 +40,7 @@ #include "hw/m68k/q800.h" #include "hw/m68k/q800-glue.h" #include "hw/misc/mac_via.h" +#include "hw/misc/djmemc.h" #include "hw/input/adb.h" #include "hw/nubus/mac-nubus-bridge.h" #include "hw/display/macfb.h" @@ -66,6 +67,7 @@ #define SONIC_PROM_BASE (IO_BASE + 0x08000) #define SONIC_BASE (IO_BASE + 0x0a000) #define SCC_BASE (IO_BASE + 0x0c020) +#define DJMEMC_BASE (IO_BASE + 0x0e000) #define ESP_BASE (IO_BASE + 0x10000) #define ESP_PDMA (IO_BASE + 0x10100) #define ASC_BASE (IO_BASE + 0x14000) @@ -257,6 +259,14 @@ static void q800_machine_init(MachineState *machine) &error_abort); sysbus_realize(SYS_BUS_DEVICE(&m->glue), &error_fatal); + /* djMEMC memory controller */ + object_initialize_child(OBJECT(machine), "djmemc", &m->djmemc, + TYPE_DJMEMC); + sysbus = SYS_BUS_DEVICE(&m->djmemc); + sysbus_realize_and_unref(sysbus, &error_fatal); + memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); + /* VIA 1 */ object_initialize_child(OBJECT(machine), "via1", &m->via1, TYPE_MOS6522_Q800_VIA1); diff --git a/hw/misc/djmemc.c b/hw/misc/djmemc.c new file mode 100644 index 000000000000..fd02640838b8 --- /dev/null +++ b/hw/misc/djmemc.c @@ -0,0 +1,135 @@ +/* + * djMEMC, macintosh memory and interrupt controller + * (Quadra 610/650/800 & Centris 610/650) + * + * https://mac68k.info/wiki/display/mac68k/djMEMC+Information + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/misc/djmemc.h" +#include "hw/qdev-properties.h" +#include "trace.h" + + +#define DJMEMC_INTERLEAVECONF 0x0 +#define DJMEMC_BANK0CONF 0x4 +#define DJMEMC_BANK1CONF 0x8 +#define DJMEMC_BANK2CONF 0xc +#define DJMEMC_BANK3CONF 0x10 +#define DJMEMC_BANK4CONF 0x14 +#define DJMEMC_BANK5CONF 0x18 +#define DJMEMC_BANK6CONF 0x1c +#define DJMEMC_BANK7CONF 0x20 +#define DJMEMC_BANK8CONF 0x24 +#define DJMEMC_BANK9CONF 0x28 +#define DJMEMC_MEMTOP 0x2c +#define DJMEMC_CONFIG 0x30 +#define DJMEMC_REFRESH 0x34 + + +static uint64_t djmemc_read(void *opaque, hwaddr addr, unsigned size) +{ + DJMEMCState *s = opaque; + uint64_t val = 0; + + switch (addr) { + case DJMEMC_INTERLEAVECONF: + case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF: + case DJMEMC_MEMTOP: + case DJMEMC_CONFIG: + case DJMEMC_REFRESH: + val = s->regs[addr >> 2]; + break; + default: + qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented read addr=0x%"PRIx64 + " val=0x%"PRIx64 " size=%d\n", + addr, val, size); + } + + trace_djmemc_read(addr, val, size); + return val; +} + +static void djmemc_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + DJMEMCState *s = opaque; + + trace_djmemc_write(addr, val, size); + + switch (addr) { + case DJMEMC_INTERLEAVECONF: + case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF: + case DJMEMC_MEMTOP: + case DJMEMC_CONFIG: + case DJMEMC_REFRESH: + s->regs[addr >> 2] = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented write addr=0x%"PRIx64 + " val=0x%"PRIx64 " size=%d\n", + addr, val, size); + } +} + +static const MemoryRegionOps djmemc_mmio_ops = { + .read = djmemc_read, + .write = djmemc_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void djmemc_init(Object *obj) +{ + DJMEMCState *s = DJMEMC(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mem_regs, obj, &djmemc_mmio_ops, s, "djMEMC", + DJMEMC_SIZE); + sysbus_init_mmio(sbd, &s->mem_regs); +} + +static void djmemc_reset_hold(Object *obj) +{ + DJMEMCState *s = DJMEMC(obj); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static const VMStateDescription vmstate_djmemc = { + .name = "djMEMC", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, DJMEMCState, DJMEMC_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void djmemc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->vmsd = &vmstate_djmemc; + rc->phases.hold = djmemc_reset_hold; +} + +static const TypeInfo djmemc_info_types[] = { + { + .name = TYPE_DJMEMC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(DJMEMCState), + .instance_init = djmemc_init, + .class_init = djmemc_class_init, + }, +}; + +DEFINE_TYPES(djmemc_info_types) diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index f839f8a03064..330cfdfa2d6f 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -23,6 +23,7 @@ config Q800 select ESP select DP8393X select OR_IRQ + select DJMEMC config M68K_VIRT bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 6996d265e4c5..cb7857e3ed9e 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -186,4 +186,7 @@ config AXP2XX_PMU bool depends on I2C +config DJMEMC + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 88ecab839237..ee5ee376487c 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -20,6 +20,7 @@ system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) # Mac devices system_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) +system_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c')) # virt devices system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index bc87cd367070..c71a47d28880 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -301,3 +301,7 @@ virt_ctrl_instance_init(void *dev) "ctrl: %p" lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" + +# djmemc.c +djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" +djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" From patchwork Sun Oct 8 06:23:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D84FE95A82 for ; Sun, 8 Oct 2023 06:26:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCs-00085j-6P; Sun, 08 Oct 2023 02:24:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCo-000833-1C for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:58 -0400 Received: from mout.kundenserver.de ([212.227.17.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCl-0007k6-K6 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:57 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N1gac-1rZfDl0wvo-011yFc; Sun, 08 Oct 2023 08:23:53 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 03/20] q800: add machine id register Date: Sun, 8 Oct 2023 08:23:32 +0200 Message-ID: <20231008062349.2733552-4-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:DE9WfMoSSpA1M6CzN4zlKPubll018lr+XkwM7z4ADtZO575TWgz jXjcU2uPYdwU/2doWF6hM8JA8ofEp5deY9hVOSbjh6d0VYnQrnUrxeWuHZnnGarQWjD1Yeb YojGl/Ic8+NyZnczEMB6bF/gMFRRd/Isa8GiiXs1f7kziFH3zdtua5k0Cn+xjNsSqzL7OxC iAiHMTAyq+JcFOYzbIcJQ== UI-OutboundReport: notjunk:1;M01:P0:C0pjHAxsZlw=;lPnXTV0XIQP5Myl3mntmLOHJjXC y0HC0LCYvzrCl3lYXg5BbF2Z8DZbmYWzuS39Dj0owGyaqNu2mRMFyYiGm5vog/r0rpvWsT2pv DihwvgpgU4mKa8YU3GZdMBmdECSfSqI1zUCj60Vz5jQbDSTFwlH/y6Srl5w+yLnUZjTrO6oxf u1V28d4CDSdJ5R5H3XBS4ilYFU3NevqQpFrgcxICt8dj2TSsv1R20PpKE3kQ/k6vybhOYGnrr MlsJq40eld4E+ssaupvwSqNj1bgJH3XudJ6EEMWMoj4IG5P+bSiT75I4Q31Ahkdv991i8sS69 prsXuRG7DpRoqwRiWsqHO4sw7vXfs42HMzz5qArpXtT6gGw7G/odqcY62nAOsnrykiflZ50VU SI3IdbwASlfT29GweJipEm4+FVJV+sD7nIpevTN86e3KFmaeLm9gCGLAcrK6RMv6JKKKEuytR FrFB21CtLgHnQXGfRBjfac80Q1E9H2BKrHlIaatEZZxNBuVf7eVRETfXFnVX/Sm08lpCTR4yN XbWTxdol7Gi1gZYpRZmklCPTxHWl2T7bsZEqZQfy72ZPrr2szGdmimpb1yFECahi5qLM7wCt4 9poYz0Ks0GvdfCdBhmsB7DxRIGLmmv44n1Y+FX0JqR3PguIgomqzGM+DeGEYajdTBG4e/7wVL 0P4rIe0aKKmhgQfKm8kifPKjOTPcir34P63kEDRjCm6ua5o1S5Cv/1XL6y5GAP3dU02UzPWug GBi4raxVJ+WRSep2JMjtQnsvVodPZTH7wqbhibgWRAC5MIaKZhnVcfL66va7labWekgawwnkC oXnlmfsWc4a19n0y2gWn3ofPyYRq+f6hZs1XYje+LKvT1N0DLKI0txIUoFhnugmN+w/rLPDbi GQA/u1Enh/gejQA== Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland MacOS reads this address to identify the hardware. This is a basic implementation returning the ID of Quadra 800. Details: http://mess.redump.net/mess/driver_info/mac_technical_notes "There are 3 ID schemes [...] The third and most scalable is a machine ID register at 0x5ffffffc. The top word must be 0xa55a to be valid. Then bits 15-11 are 0 for consumer Macs, 1 for portables, 2 for high-end 68k, and 3 for high-end PowerPC. Bit 10 is 1 if additional ID bits appear elsewhere (e.g. in VIA1). The rest of the bits are a per-model identifier. Model Lower 16 bits of ID ... Quadra/Centris 610/650/800 0x2BAD" Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231004083806.757242-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800.h | 1 + hw/m68k/q800.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index f6ae4c1c4fd5..dd7d7a6f2c48 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -60,6 +60,7 @@ struct Q800MachineState { DJMEMCState djmemc; MemoryRegion macio; MemoryRegion macio_alias; + MemoryRegion machine_id; }; #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800") diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index f9ecc1fbb094..ac8509ba6f7e 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -91,6 +91,9 @@ #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \ BIT(0xe)) +/* Quadra 800 machine ID */ +#define Q800_MACHINE_ID 0xa55a2bad + static void main_cpu_reset(void *opaque) { @@ -192,6 +195,27 @@ static const MemoryRegionOps macio_alias_ops = { }, }; +static uint64_t machine_id_read(void *opaque, hwaddr addr, unsigned size) +{ + return Q800_MACHINE_ID; +} + +static void machine_id_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + return; +} + +static const MemoryRegionOps machine_id_ops = { + .read = machine_id_read, + .write = machine_id_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + static void q800_machine_init(MachineState *machine) { Q800MachineState *m = Q800_MACHINE(machine); @@ -253,6 +277,11 @@ static void q800_machine_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE, &m->macio_alias); + memory_region_init_io(&m->machine_id, NULL, &machine_id_ops, NULL, + "Machine ID", 4); + memory_region_add_subregion(get_system_memory(), 0x5ffffffc, + &m->machine_id); + /* IRQ Glue */ object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE); object_property_set_link(OBJECT(&m->glue), "cpu", OBJECT(&m->cpu), From patchwork Sun Oct 8 06:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56A0FE95A82 for ; Sun, 8 Oct 2023 06:26:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCp-00083w-W5; Sun, 08 Oct 2023 02:24:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCn-000831-Tk for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:57 -0400 Received: from mout.kundenserver.de ([217.72.192.74]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCm-0007kC-9D for qemu-devel@nongnu.org; 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envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231004083806.757242-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/misc/mac_via.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index f84cc68849ab..e87a1b82d8c5 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -114,6 +114,9 @@ #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */ #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */ #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */ +#define VIA1A_CPUID_MASK (VIA1A_CPUID0 | VIA1A_CPUID1 | \ + VIA1A_CPUID2 | VIA1A_CPUID3) +#define VIA1A_CPUID_Q800 (VIA1A_CPUID0 | VIA1A_CPUID2) /* * Info on VIA1B is from Macintosh Family Hardware & MkLinux. @@ -872,9 +875,18 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) { MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); MOS6522State *ms = MOS6522(s); + uint64_t ret; addr = (addr >> 9) & 0xf; - return mos6522_read(ms, addr, size); + ret = mos6522_read(ms, addr, size); + switch (addr) { + case VIA_REG_A: + case VIA_REG_ANH: + /* Quadra 800 Id */ + ret = (ret & ~VIA1A_CPUID_MASK) | VIA1A_CPUID_Q800; + break; + } + return ret; } static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, From patchwork Sun Oct 8 06:23:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64520E95A67 for ; Sun, 8 Oct 2023 06:25:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCr-00084r-LZ; Sun, 08 Oct 2023 02:24:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCo-00083T-Vf for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:58 -0400 Received: from mout.kundenserver.de ([212.227.17.24]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCm-0007kZ-S4 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:58 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MWjUc-1r4kJW1RP6-00X3Hk; Sun, 08 Oct 2023 08:23:54 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier , BALATON Zoltan Subject: [PULL 05/20] q800: add IOSB subsystem Date: Sun, 8 Oct 2023 08:23:34 +0200 Message-ID: <20231008062349.2733552-6-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:Oh8B680Is3+ckhv8cgWktkFX3/resZQ85BieIhtZfYPdKIp3pdI UVOqyrY6cHqQZFNwetDajayEMRatsGw5+bGxx54cRfBdsnDQizCPIefrYQ2uEoThgUxaxxf KbTy+DFAhE1dIKcR3ilF5fUYgwTow3uzYI944yc6KcJz/vCmmDnMqqaCtKAY7yfmcx++Zs/ KG5aeVwLNssKGSlXOSs6A== UI-OutboundReport: notjunk:1;M01:P0:JV4/NGc54Gk=;PIOSsmtL8rIDnESLUW2ywbknccR yA8uGvUk+EV+EGHnd1fCrRQmHcg8Gf2WUvlz5/PB7Q5Wv3OdMOSXGM2fphWrqvOFSJKa7RWxW Xh+wOPx07bbmIwIXNI9daWldGaJXQUB7ge+RNVCcuAHh8NsaP/jR53/foBGP7UI7mkLqzlFWN 2t+8OzhbmZWldGezGDKwkE0r3hk5ijlmJ7UW4FaNoztkaTgmnLtzncb3sOqnUpBkO1eIu24Ha /R9+Sk0bFNY5jOvd55Fw1RDXudDarJPpZPPTNahen2DdNq44PGV2EoBRqbDe5cAZKh/wYbrzP yjFgIYrQymj3GpFgNLjx9Z0ayu+zBz3vEd4WhycMf/z/sVz5HKB6s9RR2DCubZukHlfDLxRyL absZygSe1q85QJXx2+WTuCyjmI8hJ7F6QgiNb0rSPLkZitgxdzpCsoaxXEr+n5vwPfTSgmnEk aOrPTfg4hh9WZaYrQyQvcr9ZyDyt9a3KjygktG9u443G8bf3Xr3nCw7qUYbawsQCJI4sfPiOz T8/oQApOUo6zTumwCBecLXsLLidiTCUe4sxXGwduNleNQC6G6fs1b/vxyal64QDU0/yuH4pz1 FHxzK/F+bAOIpME00kU03yIBq0BQjskbFvzQu9wrXPsUTiKGhk/D4Uy7bbQpFz8mehE5D7fS+ ky77Df9GbyNsOOQKyMHSkr1hox+gu/Jz6diUyfe7hmdLE0RykJD9n7ufaj9aghFE45QSq83KT MxtWDxybfadtXfWgTK9iI9rjVXHW6yKRLkQpn4qBdKOS6Frex9CLSwclTxXnHp/Zz/g2m20PV GfOXucc4y1rPCRi7V7NrHzSsUpC/KYvpnBvOk3HXMDRZcMZ6iQytiwwUszlYrBDZWCcsr2cDM a71SAr6tY0KGroA== Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland It is needed because it defines the BIOSConfig area. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland Reviewed-by: BALATON Zoltan Message-ID: <20231004083806.757242-6-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- MAINTAINERS | 2 + include/hw/m68k/q800.h | 2 + include/hw/misc/iosb.h | 25 ++++++++ hw/m68k/q800.c | 9 +++ hw/misc/iosb.c | 133 +++++++++++++++++++++++++++++++++++++++++ hw/m68k/Kconfig | 1 + hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/trace-events | 4 ++ 9 files changed, 180 insertions(+) create mode 100644 include/hw/misc/iosb.h create mode 100644 hw/misc/iosb.c diff --git a/MAINTAINERS b/MAINTAINERS index dead0d4a47e3..38fc8e0a22b8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1230,6 +1230,7 @@ F: hw/nubus/* F: hw/display/macfb.c F: hw/block/swim.c F: hw/misc/djmemc.c +F: hw/misc/iosb.c F: hw/m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo-mac.h @@ -1240,6 +1241,7 @@ F: include/hw/block/swim.h F: include/hw/m68k/q800.h F: include/hw/m68k/q800-glue.h F: include/hw/misc/djmemc.h +F: include/hw/misc/iosb.h virt M: Laurent Vivier diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index dd7d7a6f2c48..98097165d954 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -37,6 +37,7 @@ #include "hw/nubus/mac-nubus-bridge.h" #include "hw/display/macfb.h" #include "hw/misc/djmemc.h" +#include "hw/misc/iosb.h" /* * The main Q800 machine @@ -58,6 +59,7 @@ struct Q800MachineState { MacNubusBridge mac_nubus_bridge; MacfbNubusState macfb; DJMEMCState djmemc; + IOSBState iosb; MemoryRegion macio; MemoryRegion macio_alias; MemoryRegion machine_id; diff --git a/include/hw/misc/iosb.h b/include/hw/misc/iosb.h new file mode 100644 index 000000000000..377f8ca7e2fa --- /dev/null +++ b/include/hw/misc/iosb.h @@ -0,0 +1,25 @@ +/* + * QEMU IOSB emulation + * + * Copyright (c) 2019 Laurent Vivier + * Copyright (c) 2022 Mark Cave-Ayland + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MEM_IOSB_H +#define HW_MEM_IOSB_H + +#define IOSB_REGS 7 + +struct IOSBState { + SysBusDevice parent_obj; + + MemoryRegion mem_regs; + uint32_t regs[IOSB_REGS]; +}; + +#define TYPE_IOSB "IOSB" +OBJECT_DECLARE_SIMPLE_TYPE(IOSBState, IOSB); + +#endif diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index ac8509ba6f7e..081b95e9cf66 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -41,6 +41,7 @@ #include "hw/m68k/q800-glue.h" #include "hw/misc/mac_via.h" #include "hw/misc/djmemc.h" +#include "hw/misc/iosb.h" #include "hw/input/adb.h" #include "hw/nubus/mac-nubus-bridge.h" #include "hw/display/macfb.h" @@ -71,6 +72,7 @@ #define ESP_BASE (IO_BASE + 0x10000) #define ESP_PDMA (IO_BASE + 0x10100) #define ASC_BASE (IO_BASE + 0x14000) +#define IOSB_BASE (IO_BASE + 0x18000) #define SWIM_BASE (IO_BASE + 0x1E000) #define SONIC_PROM_SIZE 0x1000 @@ -296,6 +298,13 @@ static void q800_machine_init(MachineState *machine) memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE, sysbus_mmio_get_region(sysbus, 0)); + /* IOSB subsystem */ + object_initialize_child(OBJECT(machine), "iosb", &m->iosb, TYPE_IOSB); + sysbus = SYS_BUS_DEVICE(&m->iosb); + sysbus_realize_and_unref(sysbus, &error_fatal); + memory_region_add_subregion(&m->macio, IOSB_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); + /* VIA 1 */ object_initialize_child(OBJECT(machine), "via1", &m->via1, TYPE_MOS6522_Q800_VIA1); diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c new file mode 100644 index 000000000000..e7e9dcca476c --- /dev/null +++ b/hw/misc/iosb.c @@ -0,0 +1,133 @@ +/* + * QEMU IOSB emulation + * + * Copyright (c) 2019 Laurent Vivier + * Copyright (c) 2022 Mark Cave-Ayland + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/sysbus.h" +#include "hw/misc/iosb.h" +#include "trace.h" + +#define IOSB_SIZE 0x2000 + +#define IOSB_CONFIG 0x0 +#define IOSB_CONFIG2 0x100 +#define IOSB_SONIC_SCSI 0x200 +#define IOSB_REVISION 0x300 +#define IOSB_SCSI_RESID 0x400 +#define IOSB_BRIGHTNESS 0x500 +#define IOSB_TIMEOUT 0x600 + + +static uint64_t iosb_read(void *opaque, hwaddr addr, + unsigned size) +{ + IOSBState *s = IOSB(opaque); + uint64_t val = 0; + + switch (addr) { + case IOSB_CONFIG: + case IOSB_CONFIG2: + case IOSB_SONIC_SCSI: + case IOSB_REVISION: + case IOSB_SCSI_RESID: + case IOSB_BRIGHTNESS: + case IOSB_TIMEOUT: + val = s->regs[addr >> 8]; + break; + default: + qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented read addr=0x%"PRIx64 + " val=0x%"PRIx64 " size=%d\n", + addr, val, size); + } + + trace_iosb_read(addr, val, size); + return val; +} + +static void iosb_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + IOSBState *s = IOSB(opaque); + + switch (addr) { + case IOSB_CONFIG: + case IOSB_CONFIG2: + case IOSB_SONIC_SCSI: + case IOSB_REVISION: + case IOSB_SCSI_RESID: + case IOSB_BRIGHTNESS: + case IOSB_TIMEOUT: + s->regs[addr >> 8] = val; + break; + default: + qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented write addr=0x%"PRIx64 + " val=0x%"PRIx64 " size=%d\n", + addr, val, size); + } + + trace_iosb_write(addr, val, size); +} + +static const MemoryRegionOps iosb_mmio_ops = { + .read = iosb_read, + .write = iosb_write, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void iosb_reset_hold(Object *obj) +{ + IOSBState *s = IOSB(obj); + + memset(s->regs, 0, sizeof(s->regs)); + + /* BCLK 33 MHz */ + s->regs[IOSB_CONFIG >> 8] = 1; +} + +static void iosb_init(Object *obj) +{ + IOSBState *s = IOSB(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->mem_regs, obj, &iosb_mmio_ops, s, "IOSB", + IOSB_SIZE); + sysbus_init_mmio(sbd, &s->mem_regs); +} + +static const VMStateDescription vmstate_iosb = { + .name = "IOSB", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IOSBState, IOSB_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static void iosb_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->vmsd = &vmstate_iosb; + rc->phases.hold = iosb_reset_hold; +} + +static const TypeInfo iosb_info_types[] = { + { + .name = TYPE_IOSB, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(IOSBState), + .instance_init = iosb_init, + .class_init = iosb_class_init, + }, +}; + +DEFINE_TYPES(iosb_info_types) diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index 330cfdfa2d6f..64fa70a0db72 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -24,6 +24,7 @@ config Q800 select DP8393X select OR_IRQ select DJMEMC + select IOSB config M68K_VIRT bool diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index cb7857e3ed9e..858277bb6025 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -189,4 +189,7 @@ config AXP2XX_PMU config DJMEMC bool +config IOSB + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index ee5ee376487c..33659313b4bb 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -21,6 +21,7 @@ system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) # Mac devices system_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) system_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c')) +system_ss.add(when: 'CONFIG_IOSB', if_true: files('iosb.c')) # virt devices system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index c71a47d28880..29bc531d4d3e 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -305,3 +305,7 @@ lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" # djmemc.c djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" + +# iosb.c +iosb_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" +iosb_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u" From patchwork Sun Oct 8 06:23:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2BD10E95A67 for ; Sun, 8 Oct 2023 06:27:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCs-00085n-9l; Sun, 08 Oct 2023 02:24:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCp-00083l-7w for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:59 -0400 Received: from mout.kundenserver.de ([217.72.192.74]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCn-0007kh-Et for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:58 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N0F9t-1rlTzx3v4J-00xHyB; Sun, 08 Oct 2023 08:23:55 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Laurent Vivier Subject: [PULL 06/20] q800: allow accesses to RAM area even if less memory is available Date: Sun, 8 Oct 2023 08:23:35 +0200 Message-ID: <20231008062349.2733552-7-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:c1upbkwUH4goI9U/W/eC0rJ7zWjvdUKkrn3UkDFXYssYouDQArr xbtuC2suGB6fCrObZzn3XB1KGOI9Rea3mEY/p19lOkEpRho7fon9VahfWYlfYseeWBmP4ZX j7xx93JqOQZp2QWXIylH5yRZTCbxJyaDwByQsrSpaQcvAyvcRf6XZ2F0BTXmqynxSKawAqV xxhJuN7RqDKb9GONq8Zkw== UI-OutboundReport: notjunk:1;M01:P0:K4wCtnu2NCE=;xxJzv/a414yqd7UwKmKn/qJofUQ IqJ7HVQDISeTJPEOFBWbpducjqzCcxzL5C+ocgOzQWIcvzgiQc2BH8ORvu3qhu55VAGQpQIV6 0FyA7grQHm8+yZG+h030AMdypTtl6gViczbIOsoxumYgbJr3VdJ9uF6SlXtroxkY3l6/AZpU2 fO873p3lzXNr62CZaozCRbUsraiBJ6sCLLMz1pl6+spwoCIHiwbUMqifKcEAwYnDW5Sx7p8Hi rOrDkDw/K+Ad6UaPXbWKzSHZxZHhShhGGiQ+uUkLOqsnWn6n98LwmIMrmIZBeELLU+o8U1Eoz hi0aCnXV4pS29Zo+agAmLagtXtFzvotc6QTOXJIz1n3d0CqTTo5JqgJRtOlJcQRiTvdwnh905 PMr2cEDoKi8yI7x3p11lzAT49J09y9IJIBHpeSUyl3gyLa0QTtaSYj6hWm3AsuFq3KzzJn4U8 V0Tf0N9wNdXsgwyvL2hhRO9PPi7LgChX7Ko/zAdUIG5//xg9tybuQ6a67/KYTgiN+mkA3gnrA 7mZawGZG5KclBJhhIqd5hrD2uTx4rOWkkiUHKzEM8xC5wVq7WcO4V7URZYmACNWETtX+I1Dth ENB44HEdUbdRYnR+mCpLUIPpKhfK79dQGRvTCP+D2QIPQG22nUALmErvvNvul+0FTW9PbzSY3 VPQy3cg3valZnUUh7YnCeTUwLOgusN/1fuIsDF8LqpXQebmjydZIShw/9QbpCvEQRnI39Id0s n0N1SFESORXgN00yM6dQUiVoC0ygvyBiZQOgeTxqn1ljzt/kvwxOivuWhj+aDckHrwRQu9Xg9 hV8POIjDYodygJA6ScV0IZLsbLI8ddFhpME1LVqALokaKnXY/jEKQVIlLNfVwl9xSY6qXQpqi xoVs1ILCdWPHYLA== Received-SPF: none client-ip=217.72.192.74; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland MacOS attempts a series of writes and reads over the entire RAM area in order to determine the amount of RAM within the machine. Allow accesses to the entire RAM area ignoring writes and always reading zero for areas where there is no physical RAM installed to allow MacOS to detect the memory size without faulting. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-7-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800.h | 1 + hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 98097165d954..04e4e0bce35a 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -60,6 +60,7 @@ struct Q800MachineState { MacfbNubusState macfb; DJMEMCState djmemc; IOSBState iosb; + MemoryRegion ramio; MemoryRegion macio; MemoryRegion macio_alias; MemoryRegion machine_id; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 081b95e9cf66..3209309173f3 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -86,6 +86,9 @@ #define MAC_CLOCK 3686418 +/* Size of whole RAM area */ +#define RAM_SIZE 0x40000000 + /* * Slot 0x9 is reserved for use by the in-built framebuffer whilst only * slots 0xc, 0xd and 0xe physically exist on the Quadra 800 @@ -218,6 +221,27 @@ static const MemoryRegionOps machine_id_ops = { }, }; +static uint64_t ramio_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0x0; +} + +static void ramio_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + return; +} + +static const MemoryRegionOps ramio_ops = { + .read = ramio_read, + .write = ramio_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + static void q800_machine_init(MachineState *machine) { Q800MachineState *m = Q800_MACHINE(machine); @@ -262,7 +286,11 @@ static void q800_machine_init(MachineState *machine) qemu_register_reset(main_cpu_reset, &m->cpu); /* RAM */ - memory_region_add_subregion(get_system_memory(), 0, machine->ram); + memory_region_init_io(&m->ramio, OBJECT(machine), &ramio_ops, &m->ramio, + "ram", RAM_SIZE); + memory_region_add_subregion(get_system_memory(), 0x0, &m->ramio); + + memory_region_add_subregion(&m->ramio, 0, machine->ram); /* * Create container for all IO devices From patchwork Sun Oct 8 06:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D566BE95A67 for ; Sun, 8 Oct 2023 06:25:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCt-00086i-Sb; Sun, 08 Oct 2023 02:24:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCs-000864-LY for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:02 -0400 Received: from mout.kundenserver.de ([212.227.17.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCo-0007lF-9r for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:02 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N4Q8u-1rY1b3247q-011Qp4; Sun, 08 Oct 2023 08:23:56 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier , =?utf-8?q?Volker_R=C3=BCmelin?= Subject: [PULL 07/20] audio: add Apple Sound Chip (ASC) emulation Date: Sun, 8 Oct 2023 08:23:36 +0200 Message-ID: <20231008062349.2733552-8-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:qIPBYzOyOQNFkdgLuR6q5ue1AtRwETjM0ClHpTD05wHJX9YGthW CCgau5237JN/QS6QLfgjXqHVUc0m1ngILrp4gOAr4s+P1LzFfxlrx4gHti/O0YcnXadKTYz soTFe7yZmIsGvK38o8V1c8QnBAvNcurQ22evlPuYdplVzq2qFDfhll5fUDgPZvN2ospzkR8 BxzgWijgdgTVZ2ifsEVkA== UI-OutboundReport: notjunk:1;M01:P0:6+JbaCdDOiM=;naIeHUpfpdkcYAvVxNLCU0F9ql1 JxJgYoKis35P6aEC48ahhi6GTrxC8h+/aLPkf9mv2GQK06bKpvKD/9dLaN8WJVBTnxMGOlB90 TxIDRSMwRykyl+T9uABeCLfvqNrFb6JZXv/9i0QP/9j+/5NgiNQh+GvmJbyLRaVMprT3Wl5zp QiTAU1MBrg+omQagSygGi1J/65b5l6ENEJ/XIXhXaXiPS/DvkME5VTzVzFZ7OTaa6nAY2zQpi b+6UnkYk5okG+TADHg6EJffy6NCPHlbqzEFEENQS5Su2hEoZ4MaPfmeKRDf9jsXlFyqjPfeHa 23MOBRbdhift7AD59ON4e6mmNNihDv0+MkQ9+i94woTA6vWBSITWh8IXLrXo8cBz3qj1lyeII EkkaqBCPZ9/dJUcGohGW+uBGOJbdtKz8U9DVkXSyWkTWUfpxy3MZAQhhJX0YfGvCeDXnkEqkk rFIZulQEUePISmRH/2JLq1aoiyPg5gEn+uYjEiSl5HsuM35Bzca4S7e3stlbxFvjqpYSP/5K3 6o2pNvy2G6A4vlN/0+1aWjmMAEowRVT55vUlivBEziZV5k2WT0xUupn504TO2/iaqx3SwL0vI P4nZPy5c5y/UhUqZgs5k/qe4yqGwoOESr5vzAQtLN1+83L4ytYU54a7uLzy5rjiE6ixhEFvD7 xeEXjMZ7RbcfDd3tXZWhXsDPblv+lUuAl1V5tXNTHyriZ7Ia97WsMkKTT7tK7M8EkUc/pi9RL eVIqQH8hDLsiH2QQc0jN+9QFqQHGfIaTcU8bRG96ztkfQThkCUNiUz8FkSzHKrSfAUESkd6VU 50dupCdbvSYGepwcLCQ5EDconyDesAwZdnSh1XIRfyjv7B/LD1BIuL+2rfKLNMGB64OpA6z2q FHb/jmeDX8w8pyw== Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The Apple Sound Chip was primarily used by the Macintosh II to generate sound in hardware which was previously handled by the toolbox ROM with software interrupts. Implement both the standard ASC and also the enhanced ASC (EASC) functionality which is used in the Quadra 800. Note that whilst real ASC hardware uses AUDIO_FORMAT_S8, this implementation uses AUDIO_FORMAT_U8 instead because AUDIO_FORMAT_S8 is rarely used and not supported by some audio backends like PulseAudio and DirectSound when played directly with -audiodev out.mixing-engine=off. Co-developed-by: Laurent Vivier Co-developed-by: Volker Rümelin Signed-off-by: Mark Cave-Ayland Message-ID: <20231004083806.757242-8-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- MAINTAINERS | 2 + include/hw/audio/asc.h | 84 +++++ hw/audio/asc.c | 708 +++++++++++++++++++++++++++++++++++++++++ hw/audio/Kconfig | 3 + hw/audio/meson.build | 1 + hw/audio/trace-events | 10 + hw/m68k/Kconfig | 1 + 7 files changed, 809 insertions(+) create mode 100644 include/hw/audio/asc.h create mode 100644 hw/audio/asc.c diff --git a/MAINTAINERS b/MAINTAINERS index 38fc8e0a22b8..ac865c4e5932 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1231,6 +1231,7 @@ F: hw/display/macfb.c F: hw/block/swim.c F: hw/misc/djmemc.c F: hw/misc/iosb.c +F: hw/audio/asc.c F: hw/m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo.h F: include/standard-headers/asm-m68k/bootinfo-mac.h @@ -1242,6 +1243,7 @@ F: include/hw/m68k/q800.h F: include/hw/m68k/q800-glue.h F: include/hw/misc/djmemc.h F: include/hw/misc/iosb.h +F: include/hw/audio/asc.h virt M: Laurent Vivier diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h new file mode 100644 index 000000000000..d9412815c324 --- /dev/null +++ b/include/hw/audio/asc.h @@ -0,0 +1,84 @@ +/* + * QEMU Apple Sound Chip emulation + * + * Apple Sound Chip (ASC) 344S0063 + * Enhanced Apple Sound Chip (EASC) 343S1063 + * + * Copyright (c) 2012-2018 Laurent Vivier + * Copyright (c) 2022 Mark Cave-Ayland + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_AUDIO_ASC_H +#define HW_AUDIO_ASC_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "audio/audio.h" + +#define ASC_FREQ 22257 + +enum { + ASC_TYPE_ASC = 0, /* original discrete Apple Sound Chip */ + ASC_TYPE_EASC = 1 /* discrete Enhanced Apple Sound Chip */ +}; + +#define ASC_FIFO_OFFSET 0x0 +#define ASC_FIFO_SIZE 0x400 + +#define ASC_REG_OFFSET 0x800 +#define ASC_REG_SIZE 0x60 + +#define ASC_EXTREG_OFFSET 0xf00 +#define ASC_EXTREG_SIZE 0x20 + +typedef struct ASCFIFOState { + int index; + + MemoryRegion mem_fifo; + uint8_t fifo[ASC_FIFO_SIZE]; + uint8_t int_status; + + int cnt; + int wptr; + int rptr; + + MemoryRegion mem_extregs; + uint8_t extregs[ASC_EXTREG_SIZE]; + + int xa_cnt; + uint8_t xa_val; + uint8_t xa_flags; + int16_t xa_last[2]; +} ASCFIFOState; + +struct ASCState { + SysBusDevice parent_obj; + + uint8_t type; + MemoryRegion asc; + MemoryRegion mem_fifo; + MemoryRegion mem_regs; + MemoryRegion mem_extregs; + + QEMUSoundCard card; + SWVoiceOut *voice; + uint8_t *mixbuf; + int samples; + int shift; + + /* Time when we were last able to generate samples */ + int64_t fifo_empty_ns; + + qemu_irq irq; + + ASCFIFOState fifos[2]; + + uint8_t regs[ASC_REG_SIZE]; +}; + +#define TYPE_ASC "apple-sound-chip" +OBJECT_DECLARE_SIMPLE_TYPE(ASCState, ASC) + +#endif diff --git a/hw/audio/asc.c b/hw/audio/asc.c new file mode 100644 index 000000000000..9084708eafab --- /dev/null +++ b/hw/audio/asc.c @@ -0,0 +1,708 @@ +/* + * QEMU Apple Sound Chip emulation + * + * Apple Sound Chip (ASC) 344S0063 + * Enhanced Apple Sound Chip (EASC) 343S1063 + * + * Copyright (c) 2012-2018 Laurent Vivier + * Copyright (c) 2022 Mark Cave-Ayland + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "audio/audio.h" +#include "hw/audio/asc.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "trace.h" + +/* + * Linux doesn't provide information about ASC, see arch/m68k/mac/macboing.c + * and arch/m68k/include/asm/mac_asc.h + * + * best information is coming from MAME: + * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.h + * https://github.com/mamedev/mame/blob/master/src/devices/sound/asc.cpp + * Emulation by R. Belmont + * or MESS: + * http://mess.redump.net/mess/driver_info/easc + * + * 0x800: VERSION + * 0x801: MODE + * 1=FIFO mode, + * 2=wavetable mode + * 0x802: CONTROL + * bit 0=analog or PWM output, + * 1=stereo/mono, + * 7=processing time exceeded + * 0x803: FIFO MODE + * bit 7=clear FIFO, + * bit 1="non-ROM companding", + * bit 0="ROM companding") + * 0x804: FIFO IRQ STATUS + * bit 0=ch A 1/2 full, + * 1=ch A full, + * 2=ch B 1/2 full, + * 3=ch B full) + * 0x805: WAVETABLE CONTROL + * bits 0-3 wavetables 0-3 start + * 0x806: VOLUME + * bits 2-4 = 3 bit internal ASC volume, + * bits 5-7 = volume control sent to Sony sound chip + * 0x807: CLOCK RATE + * 0 = Mac 22257 Hz, + * 1 = undefined, + * 2 = 22050 Hz, + * 3 = 44100 Hz + * 0x80a: PLAY REC A + * 0x80f: TEST + * bits 6-7 = digital test, + * bits 4-5 = analog test + * 0x810: WAVETABLE 0 PHASE + * big-endian 9.15 fixed-point, only 24 bits valid + * 0x814: WAVETABLE 0 INCREMENT + * big-endian 9.15 fixed-point, only 24 bits valid + * 0x818: WAVETABLE 1 PHASE + * 0x81C: WAVETABLE 1 INCREMENT + * 0x820: WAVETABLE 2 PHASE + * 0x824: WAVETABLE 2 INCREMENT + * 0x828: WAVETABLE 3 PHASE + * 0x82C: WAVETABLE 3 INCREMENT + * 0x830: UNKNOWN START + * NetBSD writes Wavetable data here (are there more + * wavetables/channels than we know about?) + * 0x857: UNKNOWN END + */ + +#define ASC_SIZE 0x2000 + +enum { + ASC_VERSION = 0x00, + ASC_MODE = 0x01, + ASC_CONTROL = 0x02, + ASC_FIFOMODE = 0x03, + ASC_FIFOIRQ = 0x04, + ASC_WAVECTRL = 0x05, + ASC_VOLUME = 0x06, + ASC_CLOCK = 0x07, + ASC_PLAYRECA = 0x0a, + ASC_TEST = 0x0f, + ASC_WAVETABLE = 0x10 +}; + +#define ASC_FIFO_STATUS_HALF_FULL 1 +#define ASC_FIFO_STATUS_FULL_EMPTY 2 + +#define ASC_EXTREGS_FIFOCTRL 0x8 +#define ASC_EXTREGS_INTCTRL 0x9 +#define ASC_EXTREGS_CDXA_DECOMP_FILT 0x10 + +#define ASC_FIFO_CYCLE_TIME ((NANOSECONDS_PER_SECOND / ASC_FREQ) * \ + 0x400) + +static void asc_raise_irq(ASCState *s) +{ + qemu_set_irq(s->irq, 1); +} + +static void asc_lower_irq(ASCState *s) +{ + qemu_set_irq(s->irq, 0); +} + +static uint8_t asc_fifo_get(ASCFIFOState *fs) +{ + ASCState *s = container_of(fs, ASCState, fifos[fs->index]); + bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1; + uint8_t val; + + assert(fs->cnt); + + val = fs->fifo[fs->rptr]; + trace_asc_fifo_get('A' + fs->index, fs->rptr, fs->cnt, val); + + fs->rptr++; + fs->rptr &= 0x3ff; + fs->cnt--; + + if (fs->cnt <= 0x1ff) { + /* FIFO less than half full */ + fs->int_status |= ASC_FIFO_STATUS_HALF_FULL; + } else { + /* FIFO more than half full */ + fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL; + } + + if (fs->cnt == 0x1ff && fifo_half_irq_enabled) { + /* Raise FIFO half full IRQ */ + asc_raise_irq(s); + } + + if (fs->cnt == 0) { + /* Raise FIFO empty IRQ */ + fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY; + asc_raise_irq(s); + } + + return val; +} + +static int generate_fifo(ASCState *s, int maxsamples) +{ + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint8_t *buf = s->mixbuf; + int i, wcount = 0; + + while (wcount < maxsamples) { + uint8_t val; + int16_t d, f0, f1; + int32_t t; + int shift, filter; + bool hasdata = false; + + for (i = 0; i < 2; i++) { + ASCFIFOState *fs = &s->fifos[i]; + + switch (fs->extregs[ASC_EXTREGS_FIFOCTRL] & 0x83) { + case 0x82: + /* + * CD-XA BRR mode: decompress 15 bytes into 28 16-bit + * samples + */ + if (!fs->cnt) { + val = 0x80; + break; + } + + if (fs->xa_cnt == -1) { + /* Start of packet, get flags */ + fs->xa_flags = asc_fifo_get(fs); + fs->xa_cnt = 0; + } + + shift = fs->xa_flags & 0xf; + filter = fs->xa_flags >> 4; + f0 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT + + (filter << 1) + 1]; + f1 = (int8_t)fs->extregs[ASC_EXTREGS_CDXA_DECOMP_FILT + + (filter << 1)]; + + if ((fs->xa_cnt & 1) == 0) { + if (!fs->cnt) { + val = 0x80; + break; + } + + fs->xa_val = asc_fifo_get(fs); + d = (fs->xa_val & 0xf) << 12; + } else { + d = (fs->xa_val & 0xf0) << 8; + } + t = (d >> shift) + (((fs->xa_last[0] * f0) + + (fs->xa_last[1] * f1) + 32) >> 6); + if (t < -32768) { + t = -32768; + } else if (t > 32767) { + t = 32767; + } + + /* + * CD-XA BRR generates 16-bit signed output, so convert to + * 8-bit before writing to buffer. Does real hardware do the + * same? + */ + val = (uint8_t)(t / 256) ^ 0x80; + hasdata = true; + fs->xa_cnt++; + + fs->xa_last[1] = fs->xa_last[0]; + fs->xa_last[0] = (int16_t)t; + + if (fs->xa_cnt == 28) { + /* End of packet */ + fs->xa_cnt = -1; + } + break; + + default: + /* fallthrough */ + case 0x80: + /* Raw mode */ + if (fs->cnt) { + val = asc_fifo_get(fs); + hasdata = true; + } else { + val = 0x80; + } + break; + } + + buf[wcount * 2 + i] = val; + } + + if (!hasdata) { + break; + } + + wcount++; + } + + /* + * MacOS (un)helpfully leaves the FIFO engine running even when it has + * finished writing out samples, but still expects the FIFO empty + * interrupts to be generated for each FIFO cycle (without these interrupts + * MacOS will freeze) + */ + if (s->fifos[0].cnt == 0 && s->fifos[1].cnt == 0) { + if (!s->fifo_empty_ns) { + /* FIFO has completed first empty cycle */ + s->fifo_empty_ns = now; + } else if (now > (s->fifo_empty_ns + ASC_FIFO_CYCLE_TIME)) { + /* FIFO has completed entire cycle with no data */ + s->fifos[0].int_status |= ASC_FIFO_STATUS_HALF_FULL | + ASC_FIFO_STATUS_FULL_EMPTY; + s->fifos[1].int_status |= ASC_FIFO_STATUS_HALF_FULL | + ASC_FIFO_STATUS_FULL_EMPTY; + s->fifo_empty_ns = now; + asc_raise_irq(s); + } + } else { + /* FIFO contains data, reset empty time */ + s->fifo_empty_ns = 0; + } + + return wcount; +} + +static int generate_wavetable(ASCState *s, int maxsamples) +{ + uint8_t *buf = s->mixbuf; + int channel, count = 0; + + while (count < maxsamples) { + uint32_t left = 0, right = 0; + uint8_t sample; + + for (channel = 0; channel < 4; channel++) { + ASCFIFOState *fs = &s->fifos[channel >> 1]; + int chanreg = ASC_WAVETABLE + (channel << 3); + uint32_t phase, incr, offset; + + phase = ldl_be_p(&s->regs[chanreg]); + incr = ldl_be_p(&s->regs[chanreg + sizeof(uint32_t)]); + + phase += incr; + offset = (phase >> 15) & 0x1ff; + sample = fs->fifo[0x200 * (channel >> 1) + offset]; + + stl_be_p(&s->regs[chanreg], phase); + + left += sample; + right += sample; + } + + buf[count * 2] = left >> 2; + buf[count * 2 + 1] = right >> 2; + + count++; + } + + return count; +} + +static void asc_out_cb(void *opaque, int free_b) +{ + ASCState *s = opaque; + int samples, generated; + + if (free_b == 0) { + return; + } + + samples = MIN(s->samples, free_b >> s->shift); + + switch (s->regs[ASC_MODE] & 3) { + default: + /* Off */ + generated = 0; + break; + case 1: + /* FIFO mode */ + generated = generate_fifo(s, samples); + break; + case 2: + /* Wave table mode */ + generated = generate_wavetable(s, samples); + break; + } + + if (!generated) { + return; + } + + AUD_write(s->voice, s->mixbuf, generated << s->shift); +} + +static uint64_t asc_fifo_read(void *opaque, hwaddr addr, + unsigned size) +{ + ASCFIFOState *fs = opaque; + + trace_asc_read_fifo('A' + fs->index, addr, size, fs->fifo[addr]); + return fs->fifo[addr]; +} + +static void asc_fifo_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + ASCFIFOState *fs = opaque; + ASCState *s = container_of(fs, ASCState, fifos[fs->index]); + bool fifo_half_irq_enabled = fs->extregs[ASC_EXTREGS_INTCTRL] & 1; + + trace_asc_write_fifo('A' + fs->index, addr, size, fs->wptr, fs->cnt, value); + + if (s->regs[ASC_MODE] == 1) { + fs->fifo[fs->wptr++] = value; + fs->wptr &= 0x3ff; + fs->cnt++; + + if (fs->cnt <= 0x1ff) { + /* FIFO less than half full */ + fs->int_status |= ASC_FIFO_STATUS_HALF_FULL; + } else { + /* FIFO at least half full */ + fs->int_status &= ~ASC_FIFO_STATUS_HALF_FULL; + } + + if (fs->cnt == 0x200 && fifo_half_irq_enabled) { + /* Raise FIFO half full interrupt */ + asc_raise_irq(s); + } + + if (fs->cnt == 0x3ff) { + /* Raise FIFO full interrupt */ + fs->int_status |= ASC_FIFO_STATUS_FULL_EMPTY; + asc_raise_irq(s); + } + } else { + fs->fifo[addr] = value; + } + return; +} + +static const MemoryRegionOps asc_fifo_ops = { + .read = asc_fifo_read, + .write = asc_fifo_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void asc_fifo_reset(ASCFIFOState *fs); + +static uint64_t asc_read(void *opaque, hwaddr addr, + unsigned size) +{ + ASCState *s = opaque; + uint64_t prev, value; + + switch (addr) { + case ASC_VERSION: + switch (s->type) { + default: + case ASC_TYPE_ASC: + value = 0; + break; + case ASC_TYPE_EASC: + value = 0xb0; + break; + } + break; + case ASC_FIFOIRQ: + prev = (s->fifos[0].int_status & 0x3) | + (s->fifos[1].int_status & 0x3) << 2; + + s->fifos[0].int_status = 0; + s->fifos[1].int_status = 0; + asc_lower_irq(s); + value = prev; + break; + default: + value = s->regs[addr]; + break; + } + + trace_asc_read_reg(addr, size, value); + return value; +} + +static void asc_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + ASCState *s = opaque; + + switch (addr) { + case ASC_MODE: + value &= 3; + if (value != s->regs[ASC_MODE]) { + asc_fifo_reset(&s->fifos[0]); + asc_fifo_reset(&s->fifos[1]); + asc_lower_irq(s); + if (value != 0) { + AUD_set_active_out(s->voice, 1); + } else { + AUD_set_active_out(s->voice, 0); + } + } + break; + case ASC_FIFOMODE: + if (value & 0x80) { + asc_fifo_reset(&s->fifos[0]); + asc_fifo_reset(&s->fifos[1]); + asc_lower_irq(s); + } + break; + case ASC_WAVECTRL: + break; + case ASC_VOLUME: + { + int vol = (value & 0xe0); + + AUD_set_volume_out(s->voice, 0, vol, vol); + break; + } + } + + trace_asc_write_reg(addr, size, value); + s->regs[addr] = value; +} + +static const MemoryRegionOps asc_regs_ops = { + .read = asc_read, + .write = asc_write, + .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + } +}; + +static uint64_t asc_ext_read(void *opaque, hwaddr addr, + unsigned size) +{ + ASCFIFOState *fs = opaque; + uint64_t value; + + value = fs->extregs[addr]; + + trace_asc_read_extreg('A' + fs->index, addr, size, value); + return value; +} + +static void asc_ext_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + ASCFIFOState *fs = opaque; + + trace_asc_write_extreg('A' + fs->index, addr, size, value); + + fs->extregs[addr] = value; +} + +static const MemoryRegionOps asc_extregs_ops = { + .read = asc_ext_read, + .write = asc_ext_write, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static int asc_post_load(void *opaque, int version) +{ + ASCState *s = ASC(opaque); + + if (s->regs[ASC_MODE] != 0) { + AUD_set_active_out(s->voice, 1); + } + + return 0; +} + +static const VMStateDescription vmstate_asc_fifo = { + .name = "apple-sound-chip.fifo", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(fifo, ASCFIFOState, ASC_FIFO_SIZE), + VMSTATE_UINT8(int_status, ASCFIFOState), + VMSTATE_INT32(cnt, ASCFIFOState), + VMSTATE_INT32(wptr, ASCFIFOState), + VMSTATE_INT32(rptr, ASCFIFOState), + VMSTATE_UINT8_ARRAY(extregs, ASCFIFOState, ASC_EXTREG_SIZE), + VMSTATE_INT32(xa_cnt, ASCFIFOState), + VMSTATE_UINT8(xa_val, ASCFIFOState), + VMSTATE_UINT8(xa_flags, ASCFIFOState), + VMSTATE_INT16_ARRAY(xa_last, ASCFIFOState, 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_asc = { + .name = "apple-sound-chip", + .version_id = 0, + .minimum_version_id = 0, + .post_load = asc_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(fifos, ASCState, 2, 0, vmstate_asc_fifo, + ASCFIFOState), + VMSTATE_UINT8_ARRAY(regs, ASCState, ASC_REG_SIZE), + VMSTATE_INT64(fifo_empty_ns, ASCState), + VMSTATE_END_OF_LIST() + } +}; + +static void asc_fifo_reset(ASCFIFOState *fs) +{ + fs->wptr = 0; + fs->rptr = 0; + fs->cnt = 0; + fs->xa_cnt = -1; + fs->int_status = 0; +} + +static void asc_fifo_init(ASCFIFOState *fs, int index) +{ + ASCState *s = container_of(fs, ASCState, fifos[index]); + char *name; + + fs->index = index; + name = g_strdup_printf("asc.fifo%c", 'A' + index); + memory_region_init_io(&fs->mem_fifo, OBJECT(s), &asc_fifo_ops, fs, + name, ASC_FIFO_SIZE); + g_free(name); + + name = g_strdup_printf("asc.extregs%c", 'A' + index); + memory_region_init_io(&fs->mem_extregs, OBJECT(s), &asc_extregs_ops, + fs, name, ASC_EXTREG_SIZE); + g_free(name); +} + +static void asc_reset_hold(Object *obj) +{ + ASCState *s = ASC(obj); + + AUD_set_active_out(s->voice, 0); + + memset(s->regs, 0, sizeof(s->regs)); + asc_fifo_reset(&s->fifos[0]); + asc_fifo_reset(&s->fifos[1]); + s->fifo_empty_ns = 0; + + if (s->type == ASC_TYPE_ASC) { + /* FIFO half full IRQs enabled by default */ + s->fifos[0].extregs[ASC_EXTREGS_INTCTRL] = 1; + s->fifos[1].extregs[ASC_EXTREGS_INTCTRL] = 1; + } +} + +static void asc_unrealize(DeviceState *dev) +{ + ASCState *s = ASC(dev); + + g_free(s->mixbuf); + + AUD_remove_card(&s->card); +} + +static void asc_realize(DeviceState *dev, Error **errp) +{ + ASCState *s = ASC(dev); + struct audsettings as; + + if (!AUD_register_card("Apple Sound Chip", &s->card, errp)) { + return; + } + + as.freq = ASC_FREQ; + as.nchannels = 2; + as.fmt = AUDIO_FORMAT_U8; + as.endianness = AUDIO_HOST_ENDIANNESS; + + s->voice = AUD_open_out(&s->card, s->voice, "asc.out", s, asc_out_cb, + &as); + s->shift = 1; + s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift; + s->mixbuf = g_malloc0(s->samples << s->shift); + + /* Add easc registers if required */ + if (s->type == ASC_TYPE_EASC) { + memory_region_add_subregion(&s->asc, ASC_EXTREG_OFFSET, + &s->fifos[0].mem_extregs); + memory_region_add_subregion(&s->asc, + ASC_EXTREG_OFFSET + ASC_EXTREG_SIZE, + &s->fifos[1].mem_extregs); + } +} + +static void asc_init(Object *obj) +{ + ASCState *s = ASC(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + + memory_region_init(&s->asc, OBJECT(obj), "asc", ASC_SIZE); + + asc_fifo_init(&s->fifos[0], 0); + asc_fifo_init(&s->fifos[1], 1); + + memory_region_add_subregion(&s->asc, ASC_FIFO_OFFSET, + &s->fifos[0].mem_fifo); + memory_region_add_subregion(&s->asc, + ASC_FIFO_OFFSET + ASC_FIFO_SIZE, + &s->fifos[1].mem_fifo); + + memory_region_init_io(&s->mem_regs, OBJECT(obj), &asc_regs_ops, s, + "asc.regs", ASC_REG_SIZE); + memory_region_add_subregion(&s->asc, ASC_REG_OFFSET, &s->mem_regs); + + sysbus_init_irq(sbd, &s->irq); + sysbus_init_mmio(sbd, &s->asc); +} + +static Property asc_properties[] = { + DEFINE_AUDIO_PROPERTIES(ASCState, card), + DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC), + DEFINE_PROP_END_OF_LIST(), +}; + +static void asc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->realize = asc_realize; + dc->unrealize = asc_unrealize; + set_bit(DEVICE_CATEGORY_SOUND, dc->categories); + dc->vmsd = &vmstate_asc; + device_class_set_props(dc, asc_properties); + rc->phases.hold = asc_reset_hold; +} + +static const TypeInfo asc_info_types[] = { + { + .name = TYPE_ASC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ASCState), + .instance_init = asc_init, + .class_init = asc_class_init, + }, +}; + +DEFINE_TYPES(asc_info_types) diff --git a/hw/audio/Kconfig b/hw/audio/Kconfig index e76c69ca7e7f..d0993514a18b 100644 --- a/hw/audio/Kconfig +++ b/hw/audio/Kconfig @@ -47,3 +47,6 @@ config PL041 config CS4231 bool + +config ASC + bool diff --git a/hw/audio/meson.build b/hw/audio/meson.build index d0fda1009ed6..8805322f5c8b 100644 --- a/hw/audio/meson.build +++ b/hw/audio/meson.build @@ -1,6 +1,7 @@ system_ss.add(files('soundhw.c')) system_ss.add(when: 'CONFIG_AC97', if_true: files('ac97.c')) system_ss.add(when: 'CONFIG_ADLIB', if_true: files('fmopl.c', 'adlib.c')) +system_ss.add(when: 'CONFIG_ASC', if_true: files('asc.c')) system_ss.add(when: 'CONFIG_CS4231', if_true: files('cs4231.c')) system_ss.add(when: 'CONFIG_CS4231A', if_true: files('cs4231a.c')) system_ss.add(when: 'CONFIG_ES1370', if_true: files('es1370.c')) diff --git a/hw/audio/trace-events b/hw/audio/trace-events index 4dec48a4fd5e..89ef2996e511 100644 --- a/hw/audio/trace-events +++ b/hw/audio/trace-events @@ -17,3 +17,13 @@ via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x" via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char flag, uint32_t len) "curr=0x%x addr=0x%x %c%c%c len=%d" via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64 via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64 + +# asc.c +asc_read_fifo(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64 +asc_read_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64 +asc_read_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64 +asc_fifo_get(const char fifo, int rptr, int cnt, uint64_t value) "fifo %c rptr=0x%x cnt=0x%x value=0x%"PRIx64 +asc_write_fifo(const char fifo, int reg, unsigned size, int wrptr, int cnt, uint64_t value) "fifo %c reg=0x%03x size=%u wptr=0x%x cnt=0x%x value=0x%"PRIx64 +asc_write_reg(int reg, unsigned size, uint64_t value) "reg=0x%03x size=%u value=0x%"PRIx64 +asc_write_extreg(const char fifo, int reg, unsigned size, uint64_t value) "fifo %c reg=0x%03x size=%u value=0x%"PRIx64 +asc_update_irq(int irq, int a, int b) "set IRQ to %d (A: 0x%x B: 0x%x)" diff --git a/hw/m68k/Kconfig b/hw/m68k/Kconfig index 64fa70a0db72..d88741ec9d1c 100644 --- a/hw/m68k/Kconfig +++ b/hw/m68k/Kconfig @@ -25,6 +25,7 @@ config Q800 select OR_IRQ select DJMEMC select IOSB + select ASC config M68K_VIRT bool From patchwork Sun Oct 8 06:23:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 331FDE95A67 for ; Sun, 8 Oct 2023 06:26:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCr-00085J-4h; Sun, 08 Oct 2023 02:24:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCq-000842-50 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:00 -0400 Received: from mout.kundenserver.de ([212.227.17.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCo-0007lQ-Eh for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:23:59 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MfqCF-1rValx1dKj-00gIVt; Sun, 08 Oct 2023 08:23:57 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 08/20] asc: generate silence if FIFO empty but engine still running Date: Sun, 8 Oct 2023 08:23:37 +0200 Message-ID: <20231008062349.2733552-9-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:Nod/Hl+yXfnuP8JYoN5qjxrm6MUcX3vJDxWA01f3ZnFnobZenUE aAwzMQTAedUZDsi0BlnNPXCwtYMVk6fwpxSC2LB2wUhQxN7eufbHURdZUYpaS6/VMrds+pF Y8DBTFW0slGw95uGYXFDFyeCe5c47GxY/xKoJE6nV1BRRww12W/LSOopm7hEb8LLmwI7l5A lLZ9cKVCJJv02e11ZDqug== UI-OutboundReport: notjunk:1;M01:P0:wOZBQy0lR2Q=;+K9KpUlZ9D6wkU6Jy76Uisv9U4G tu1FEfMtoxjl4S/r5FzqdteFt0nJ6p9xp6fS5wqKbXTI9aZ5TFmyW1S42IYjfoYzaL/CqioyX ZcWIVNwxE5aa0UJUvgdm3AZqsyQVKcnmggOMRQ+/pqkYI75lsqS5/q9kwoYdEvJi8238FWscS UdAt5FrzSnYUbpibQ6C5zCQJG5uNTVWiJFlKy0A7rtxfsD7DxCOXTWXeQI83WQiCDY8Mj5Uob RoPKsEPvYnmXpna5kxovk5fgEyom+9fVTxfTINGo9N0j/8f8TvXCDujNvwX10e8xZDULsZin0 XaiDN15yQiKXgVYdSE6Q/HyrGmgX228Wz5Y4IJbmC2nW3euQShuOCCLZwJU5afJwIQGUn9cR+ JWuBc4I4NXq2FpwyQWhjOWcB9JRDGOUawCYG9wn7V/hR0oPkeHRRpjTQQ/qaKxdaBaw38KblU YL9TKXBBL8AJ91AJmNkA/+8uPN7lZUMeDvbNg4xQrJUsLyOhb+bIe2uMDvMT378xYIsr8h9TX gnqpFFKHL9aRTn7LJHyLKIsmKFgiEkOAq9CeJrxYopNOA9RRqi74wWL424U7umnnwwkg/TP+i jKGYn1rT49r5iEzIXystAEifH1+WDMl4y1NibX/l4jEj9c+RHn+AF9WplXmrVBiHKANOrEEnc BmaOYSWlu2yfRW4tF2JKT5D5NeuxxVzB2kmOQKzvIkU1uUHRr7Vry24pfnTFyj+KeLCdkzbfL 95F7CAfMc+gm/XjVN2nQGTZfXuL++UbV9GL91olR3pJV180yyDkOjV6FT7ANXUpctxXJ8ZIq6 NGhDJDf3DlrVhIjsQjLBIE0nOOpr/hTDEoI7TL6ym/bzbOkGh1vQWQgO7QXuhAePk3fFO7RmC vyR/ki5Ls2ZjkOg== Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland MacOS (un)helpfully leaves the FIFO engine running even when all the samples have been written to the hardware, and expects the FIFO status flags and IRQ to be updated continuously. There is an additional problem in that not all audio backends guarantee an all-zero output when there is no FIFO data available, in particular the Windows dsound backend which re-uses its internal circular buffer causing the last played sound to loop indefinitely. Whilst this is effectively a bug in the Windows dsound backend, work around it for now using a simple heuristic: if the FIFO remains empty for half a cycle (~23ms) then continuously fill the generated buffer with empty silence. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-9-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/audio/asc.h | 2 ++ hw/audio/asc.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/hw/audio/asc.h b/include/hw/audio/asc.h index d9412815c324..4741f92c4613 100644 --- a/include/hw/audio/asc.h +++ b/include/hw/audio/asc.h @@ -68,6 +68,8 @@ struct ASCState { int samples; int shift; + uint8_t *silentbuf; + /* Time when we were last able to generate samples */ int64_t fifo_empty_ns; diff --git a/hw/audio/asc.c b/hw/audio/asc.c index 9084708eafab..0f36b4ce9b6f 100644 --- a/hw/audio/asc.c +++ b/hw/audio/asc.c @@ -341,6 +341,21 @@ static void asc_out_cb(void *opaque, int free_b) } if (!generated) { + /* Workaround for audio underflow bug on Windows dsound backend */ + int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int silent_samples = muldiv64(now - s->fifo_empty_ns, + NANOSECONDS_PER_SECOND, ASC_FREQ); + + if (silent_samples > ASC_FIFO_CYCLE_TIME / 2) { + /* + * No new FIFO data within half a cycle time (~23ms) so fill the + * entire available buffer with silence. This prevents an issue + * with the Windows dsound backend whereby the sound appears to + * loop because the FIFO has run out of data, and the driver + * reuses the stale content in its circular audio buffer. + */ + AUD_write(s->voice, s->silentbuf, samples << s->shift); + } return; } @@ -618,6 +633,7 @@ static void asc_unrealize(DeviceState *dev) ASCState *s = ASC(dev); g_free(s->mixbuf); + g_free(s->silentbuf); AUD_remove_card(&s->card); } @@ -642,6 +658,9 @@ static void asc_realize(DeviceState *dev, Error **errp) s->samples = AUD_get_buffer_size_out(s->voice) >> s->shift; s->mixbuf = g_malloc0(s->samples << s->shift); + s->silentbuf = g_malloc0(s->samples << s->shift); + memset(s->silentbuf, 0x80, s->samples << s->shift); + /* Add easc registers if required */ if (s->type == ASC_TYPE_EASC) { memory_region_add_subregion(&s->asc, ASC_EXTREG_OFFSET, From patchwork Sun Oct 8 06:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AC6B4E95A80 for ; Sun, 8 Oct 2023 06:25:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCt-00086g-O1; Sun, 08 Oct 2023 02:24:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCr-00085L-QS for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:01 -0400 Received: from mout.kundenserver.de ([217.72.192.74]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCp-0007lo-0m for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:01 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MPGiR-1rEtKi1he9-00Pb2j; Sun, 08 Oct 2023 08:23:57 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 09/20] q800: add Apple Sound Chip (ASC) audio to machine Date: Sun, 8 Oct 2023 08:23:38 +0200 Message-ID: <20231008062349.2733552-10-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:bYI5H8B71WSDbpoEsuAKT+QU7HuSVRpnQHWQSaHYKJWts+19K6J 3XBheQ8wWmqlTvxWsjYB/bMyoNa4wxLQt2l+Zf3wDSekabnvG9koYHh2AV325m6sEfbbbt0 V3F0yEOs4wfVv+6vf5EqZ8SK+pP5s7ZvQKR2dBlhzpMfDyYS4qu70m625hYAzSzeDxWpSLk z16Q1Jd3045STTOSP2pvA== UI-OutboundReport: notjunk:1;M01:P0:+VbLwkkkRA8=;tb99CyreTsR1idfA92+MSnI/y7p O7CL6pX+gRpoM+PePsRR7+X5x2uh4flC/v/oi+XWeI+ka9EZ+XziicHhoA9IWDITWmsXANGjp +UDbpokatOEsqJ6kKTzNUwHc45wBaIGvh02quktNIA/dyp2SdvgZSovRyIej8o6XPzWanY7vR DVBWECv10hIE/TxqVebBarn6QqcFaDYoT0ZAqtkAoE63Yoq9Rey6rfGcgHXSPjkPzQ63CKn5H BqTA3DZIj5h09T6CaSscMasXneXDZ6OkvvRjI2kqjo9vlM4br6lT90rwnH4z6/JGZWpt7n6rL A/zvopmsTKUor0tnhDMQqjLH575gWRUI3Q6llnmTscNpXztdrMvLZgi+ANUecwYKx9xTmlaqq 3yvT9m+yw45oDQxQMUCrBG1UE1ifgX1ANjDtgKbw5AW/DqtPv8hK30mQS+Pjvs8+YowObeqAW jqnQNkKlUuhEyAtXfsLpSCoqsFWH/597hUtSYzrY7Tqt06txghKwF52/ryMJ+6O8VaBQejN4F Lf+v2+XrxQ1QzmPUmWmRX3b6iSRAllyl7emOzVcOPpbaHJg/1iLAL/WbGC23Kepmeo0K36Mn8 sEtg0N8Rgs/+yATwLh2fWnilPmH83IegvCgS2NDCd4O3VaeMPd5/H260DH2ImaH4zKQ+oLM/t Vrsqfjff0Ls19ECqw34si3gcvSNSz1oh0MVbXVTd+ydX5H7LpQ5DR3rxg331Pe1KxxpWln+y5 CPIDzDLl0KAyW2TtK6KeANizmyjgqNLwk98qULMMR8Ot0mcETrgjazoueJvCdRJmpdLq/trcz r38V7S6i/pyDAJSewlYYF555q34Ap2MHREmid8AwygM2uMEZ/L/4sOGmeR85k+9a7FrgMxTYX PmALGIJk2VfYKkw== Received-SPF: none client-ip=217.72.192.74; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The Quadra 800 has the enhanced ASC (EASC) audio chip which supports both the legacy IRQ routing through VIA2 and also "A/UX" mode routing direct to the CPU. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland Message-ID: <20231004083806.757242-10-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800-glue.h | 4 +++- include/hw/m68k/q800.h | 2 ++ hw/m68k/q800-glue.c | 11 ++++++++++- hw/m68k/q800.c | 21 +++++++++++++++++++++ 4 files changed, 36 insertions(+), 2 deletions(-) diff --git a/include/hw/m68k/q800-glue.h b/include/hw/m68k/q800-glue.h index a35efc1c534d..ceb916d16c14 100644 --- a/include/hw/m68k/q800-glue.h +++ b/include/hw/m68k/q800-glue.h @@ -35,7 +35,7 @@ struct GLUEState { M68kCPU *cpu; uint8_t ipr; uint8_t auxmode; - qemu_irq irqs[1]; + qemu_irq irqs[2]; QEMUTimer *nmi_release; }; @@ -44,7 +44,9 @@ struct GLUEState { #define GLUE_IRQ_IN_SONIC 2 #define GLUE_IRQ_IN_ESCC 3 #define GLUE_IRQ_IN_NMI 4 +#define GLUE_IRQ_IN_ASC 5 #define GLUE_IRQ_NUBUS_9 0 +#define GLUE_IRQ_ASC 1 #endif diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 04e4e0bce35a..790cf433f38d 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -38,6 +38,7 @@ #include "hw/display/macfb.h" #include "hw/misc/djmemc.h" #include "hw/misc/iosb.h" +#include "hw/audio/asc.h" /* * The main Q800 machine @@ -60,6 +61,7 @@ struct Q800MachineState { MacfbNubusState macfb; DJMEMCState djmemc; IOSBState iosb; + ASCState asc; MemoryRegion ramio; MemoryRegion macio; MemoryRegion macio_alias; diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c index 710a5c331ec9..f413b1599a2c 100644 --- a/hw/m68k/q800-glue.c +++ b/hw/m68k/q800-glue.c @@ -97,6 +97,11 @@ static void GLUE_set_irq(void *opaque, int irq, int level) irq = 6; break; + case GLUE_IRQ_IN_ASC: + /* Route to VIA2 instead, negative edge-triggered */ + qemu_set_irq(s->irqs[GLUE_IRQ_ASC], !level); + return; + default: g_assert_not_reached(); } @@ -123,6 +128,10 @@ static void GLUE_set_irq(void *opaque, int irq, int level) irq = 6; break; + case GLUE_IRQ_IN_ASC: + irq = 4; + break; + default: g_assert_not_reached(); } @@ -214,7 +223,7 @@ static void glue_init(Object *obj) qdev_init_gpio_in(dev, GLUE_set_irq, 8); qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1); - qdev_init_gpio_out(dev, s->irqs, 1); + qdev_init_gpio_out(dev, s->irqs, 2); /* NMI release timer */ s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s); diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 3209309173f3..249fedde7a92 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -43,6 +43,7 @@ #include "hw/misc/djmemc.h" #include "hw/misc/iosb.h" #include "hw/input/adb.h" +#include "hw/audio/asc.h" #include "hw/nubus/mac-nubus-bridge.h" #include "hw/display/macfb.h" #include "hw/block/swim.h" @@ -480,6 +481,25 @@ static void q800_machine_init(MachineState *machine) scsi_bus_legacy_handle_cmdline(&esp->bus); + /* Apple Sound Chip */ + + object_initialize_child(OBJECT(machine), "asc", &m->asc, TYPE_ASC); + qdev_prop_set_uint8(DEVICE(&m->asc), "asctype", ASC_TYPE_EASC); + if (machine->audiodev) { + qdev_prop_set_string(DEVICE(&m->asc), "audiodev", machine->audiodev); + } + sysbus = SYS_BUS_DEVICE(&m->asc); + sysbus_realize_and_unref(sysbus, &error_fatal); + memory_region_add_subregion(&m->macio, ASC_BASE - IO_BASE, + sysbus_mmio_get_region(sysbus, 0)); + sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(DEVICE(&m->glue), + GLUE_IRQ_IN_ASC)); + + /* Wire ASC IRQ via GLUE for use in classic mode */ + qdev_connect_gpio_out(DEVICE(&m->glue), GLUE_IRQ_ASC, + qdev_get_gpio_in(DEVICE(&m->via2), + VIA2_IRQ_ASC_BIT)); + /* SWIM floppy controller */ object_initialize_child(OBJECT(machine), "swim", &m->swim, @@ -688,6 +708,7 @@ static void q800_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = 1; mc->block_default_type = IF_SCSI; mc->default_ram_id = "m68k_mac.ram"; + machine_add_audiodev_property(mc); compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len); } From patchwork Sun Oct 8 06:23:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9220E95A80 for ; Sun, 8 Oct 2023 06:26:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCu-00086k-9g; Sun, 08 Oct 2023 02:24:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCs-00086B-Um for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:02 -0400 Received: from mout.kundenserver.de ([212.227.17.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCq-0007mR-5n for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:02 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MkIAB-1rIPUC3qGH-00kiLh; Sun, 08 Oct 2023 08:23:58 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Laurent Vivier Subject: [PULL 10/20] q800: add easc bool machine class property to switch between ASC and EASC Date: Sun, 8 Oct 2023 08:23:39 +0200 Message-ID: <20231008062349.2733552-11-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:z5kHivFIfPWa5li91QFZtd6gZdzjeTycWhJu1OFpRn4NJLBOtyk dYXb+RNCBm0Bz/5+6P9K/tGj8kRrzMp4XImiU/cMhuouDLHy+SenZUz+5stu7DlSQ5yARAd deEcCu1oMWop7t2oLNImumw03liaJ2bZeDApu9Sz4dEd3CAPvd3PLVY//VvyyCy+B3fv5OZ 4Q3hKrkEi+VWxXTRnX2ZQ== UI-OutboundReport: notjunk:1;M01:P0:7kpVW6JFPhg=;C79jfdwdeb2iiZsieBlXtHyTcsB 4z1T30RQyY/vM8cwpwYAw0ye6Pjt6uJL2o3tOYDZGsJGoXYC+guT5h5k0fNhDcbkAidX/lnJg 6p0OaDXKR1aixyvn4btzHgS3q9Q6LuA664r23nLBmjZx8igsOEDC3Q1ZZqhRLt1sD1K3N+pim zZz9P3/dUdlxd6SD8sqdftIxBxsGIS7gBtql1ntLi2PHAJGa98AMplOO76LjQ1ZnGbWOaHhXD jnOO6C9XSEsSNnU4skqsHHe2i9g9LQMWTK/uOTVe4zb6c2ArPMVs087UdZ4k2ftn/iT4weG3w tZ7frvv6l6obtKIqUUeDGzE4f5DZR9sRuUqamcahqFjzDukognUhUuRvSXZN3d7WtZ4IIQlip rGDffiss5Cy0kMIyGHhSA4J+vdRkBS4Wnujzi1mcD6/XR0QGMHxFCUbT+NQgVYKjfRvxBsqPz N07IQBYT7yzuRGKZd5Ioz+xVT/m2H0dSr5GLUzLtvJx9l9tvTuxZvv2RN3vQt3xojRGm/g2IZ +dWVxUk6aDBMP5dUm7rSdp1V7PyjRmklrLoPFgWTg6C1OISgcaH93CH2EJZUWt+xjmwt6BGvm yS/ffVpClwfmFPC2kiaUxCZSfdYjf88jcfD6hzNmmtfW1whE5Ywoz5S7adktwUTF5UZp0sKAZ YFE2hm+5E6KUHmNfYCiSjBTP3uLrGVAjrTw9jVYIphklzXwl6Vq24H9/QEOZtgLEwZ3EW3LmH mBoxKnmjT88Z8aNgvnJ9+JKCrJByG+gdziRO7SRzlPRIvGwLiZILu3aZtXc7u0j4jGBZ2pbre ldFg3ZGHZBQorEd7WlWsIOFSqCtdjFaDXNiG/fi5COWLV2zHZvsAWEkAbF1iSWjIKaUafMLdY Bfp9YyBYFPDrmEw== Received-SPF: none client-ip=212.227.17.13; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland This determines whether the Apple Sound Chip (ASC) is set to enhanced mode (default) or to original mode. The real Q800 hardware used an EASC chip however a lot of older software only works with the older ASC chip. Adding this as a machine parameter allows QEMU to be used as an developer aid for testing and migrating code from ASC to EASC. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-11-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800.h | 1 + hw/m68k/q800.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 790cf433f38d..fbaacd88bd57 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -47,6 +47,7 @@ struct Q800MachineState { MachineState parent_obj; + bool easc; M68kCPU cpu; MemoryRegion rom; GLUEState glue; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 249fedde7a92..ac3115d32844 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -484,7 +484,8 @@ static void q800_machine_init(MachineState *machine) /* Apple Sound Chip */ object_initialize_child(OBJECT(machine), "asc", &m->asc, TYPE_ASC); - qdev_prop_set_uint8(DEVICE(&m->asc), "asctype", ASC_TYPE_EASC); + qdev_prop_set_uint8(DEVICE(&m->asc), "asctype", m->easc ? ASC_TYPE_EASC + : ASC_TYPE_ASC); if (machine->audiodev) { qdev_prop_set_string(DEVICE(&m->asc), "audiodev", machine->audiodev); } @@ -677,6 +678,28 @@ static void q800_machine_init(MachineState *machine) } } +static bool q800_get_easc(Object *obj, Error **errp) +{ + Q800MachineState *ms = Q800_MACHINE(obj); + + return ms->easc; +} + +static void q800_set_easc(Object *obj, bool value, Error **errp) +{ + Q800MachineState *ms = Q800_MACHINE(obj); + + ms->easc = value; +} + +static void q800_init(Object *obj) +{ + Q800MachineState *ms = Q800_MACHINE(obj); + + /* Default to EASC */ + ms->easc = true; +} + static GlobalProperty hw_compat_q800[] = { { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" }, { "scsi-hd", "vendor", " SEAGATE" }, @@ -710,11 +733,16 @@ static void q800_machine_class_init(ObjectClass *oc, void *data) mc->default_ram_id = "m68k_mac.ram"; machine_add_audiodev_property(mc); compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len); + + object_class_property_add_bool(oc, "easc", q800_get_easc, q800_set_easc); + object_class_property_set_description(oc, "easc", + "Set to off to use ASC rather than EASC"); } static const TypeInfo q800_machine_typeinfo = { .name = MACHINE_TYPE_NAME("q800"), .parent = TYPE_MACHINE, + .instance_init = q800_init, .instance_size = sizeof(Q800MachineState), .class_init = q800_machine_class_init, }; From patchwork Sun Oct 8 06:23:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C0D4E95A80 for ; Sun, 8 Oct 2023 06:27:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCu-000870-T9; Sun, 08 Oct 2023 02:24:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCt-00086C-0k for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:03 -0400 Received: from mout.kundenserver.de ([217.72.192.73]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCq-0007mX-Ae for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:02 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MulVd-1rfxgz2d99-00rled; Sun, 08 Oct 2023 08:23:58 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 11/20] swim: add trace events for IWM and ISM registers Date: Sun, 8 Oct 2023 08:23:40 +0200 Message-ID: <20231008062349.2733552-12-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:Ovk+qe9uRj8XUgrVgV6Z2NUaSWC6x19RWRnuw8w14KsDpS7yTcq UJbFCsOETCr4NMDoThYfscnnypLW7lVkjAat/plx2FLfpl4pNWeDpfDRL0QeoVJy2xNpUj9 hWWqibWJbK7kEz0reyrFJuB6kU2IadPcvfk4uvDHBQ8M4LLIK6bMo1dDXVdZr1wjqEqK5o1 lqMvkl79gBqnkWBYHihAA== UI-OutboundReport: notjunk:1;M01:P0:jxvfbnT7NRk=;vRL6d9Pjut06vvQ9Pz/35S4Afjc UAsV1w6PpPAPSgL2EfYNJEy12/Y51W9/i3Q+OttjJVAHc+JYlxm47XON9mKEw7sP81sVtp+xr MD2Svxx/FXsq4MWcz1/SkPxmvtnPpsdw6AXv1ExIc1YH21AHvXPXOjMNM5cfNZPwdPAGoKkNY VEGmgmj2HMezk9Vluub4S8MU6dPbb35I5xZ37ASHMiVKOOtHS20EWA0t3KC3zTFfFAokJH8QA Di2VBiAejwWVtn0Z6dLACtD+qs4D+3hXb/eSg3/wbnwPqdxNSZjCSKJqc/vwQcKM2f2sOaafd //E37UBuWrTdt6YDH+np/9dH6GtmGBPCdTnrYOG46JuascMGQYMXtPX8Vrwa3/kuCMQMWkNF7 maorWCzdm/085kT8Vs4u/V+v84rLw9zdgJbeNOAuohQhwBZJCcEko2+eDJ11JH4W4Cb8KNHQC fNUOVRhxctMWx0DsKZA4APjQ0Rmzhqq5BfB09lyf5y1N+QaLX5nvIBM+rNXzN6/Gqd7VycuhA LCG6SnJuIJ7TNvJ8Fglusdbb0DyNOoCE6VEEmLMps1wAlEeAoSlmzdSLhqd6ehodskQZyqk7t T5N5/oNrd7DlNx4BV4kKgVJFvMT1PMjjuvo9YaImcEW92lP9kW92vG1c8NwvLyCWXD9WPT1cB SURjTbvAtsbABsvlT69t1zRwOONrCqQpQzWGBxTu9yt+VWRpRphAc3n3OWoD9UDbHZLTi0y+6 fsKIQh2FFkpUjzsZUoMDkHnWbqgySD89K7DWdmJBABYwBwdcvIHjDEwaNaqGlkyYPduGRhBC2 1MZl9D0e0sfI1D8FbpPYuInS2DlzK67SxsS3vYObu6+4mSM5UD+gWo7aywufd3jAeRqIk2uv0 XC/Vn7Mf2z+0diQ== Received-SPF: none client-ip=217.72.192.73; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-12-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/block/swim.c | 14 ++++++++++++++ hw/block/trace-events | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/hw/block/swim.c b/hw/block/swim.c index 333da08ce093..7df36ea139cb 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -19,6 +19,7 @@ #include "hw/block/block.h" #include "hw/block/swim.h" #include "hw/qdev-properties.h" +#include "trace.h" /* IWM registers */ @@ -125,6 +126,13 @@ #define SWIM_HEDSEL 0x20 #define SWIM_MOTON 0x80 +static const char *swim_reg_names[] = { + "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER", + "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1", + "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER", + "READ_PHASE", "READ_SETUP", "READ_STATUS", "READ_HANDSHAKE" +}; + static void fd_recalibrate(FDrive *drive) { } @@ -267,6 +275,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; swimctrl->regs[reg >> 1] = reg & 1; + trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1)); if (swimctrl->regs[IWM_Q6] && swimctrl->regs[IWM_Q7]) { @@ -297,6 +306,7 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, if (value == 0x57) { swimctrl->mode = SWIM_MODE_SWIM; swimctrl->iwm_switch = 0; + trace_swim_iwm_switch(); } break; } @@ -312,6 +322,7 @@ static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) swimctrl->regs[reg >> 1] = reg & 1; + trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1)); return 0; } @@ -327,6 +338,8 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; + trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value); + switch (reg) { case SWIM_WRITE_PHASE: swimctrl->swim_phase = value; @@ -376,6 +389,7 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) break; } + trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value); return value; } diff --git a/hw/block/trace-events b/hw/block/trace-events index 34be8b9135f5..c041ec45e312 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -90,3 +90,10 @@ m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0 m25p80_read_sfdp(void *s, uint32_t addr, uint8_t v) "[%p] Read SFDP 0x%"PRIx32"=0x%"PRIx8 m25p80_binding(void *s) "[%p] Binding to IF_MTD drive" m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM" + +# swim.c +swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 +swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 +swim_iwm_switch(void) "switch from IWM to SWIM mode" From patchwork Sun Oct 8 06:23:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B571CE95A80 for ; Sun, 8 Oct 2023 06:27:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCx-00088c-NI; Sun, 08 Oct 2023 02:24:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCu-00086j-8D for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:04 -0400 Received: from mout.kundenserver.de ([212.227.17.24]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCs-0007mx-6D for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:03 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1Mdv2u-1rPGBd1hzS-00b4Fa; Sun, 08 Oct 2023 08:23:59 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 12/20] swim: split into separate IWM and ISM register blocks Date: Sun, 8 Oct 2023 08:23:41 +0200 Message-ID: <20231008062349.2733552-13-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:t3HIZh8jiXfosNAjs4CGjOMQvKCrdJfoGKJ8r94IfcaHDDCD2c0 hZTkhXHsUuDL2ugOnDT+i1nvh82X+AtV7/uVpyFKb31xP8Sbux5Yce1tq2ei3nqvb8egEnp B6NtVpVfo4h+rXXFDM+JHIvhK2sHAGj+Qk/B4Y5GkrFM/VVtjlljGRi5BGgx5UfIQqlmtld vVn15Ehja4W4dhL0JNBWA== UI-OutboundReport: notjunk:1;M01:P0:aRYgWmEI1yA=;aGQ99OSg8RJmhjFs7DhHLUSAMgr EUgMEAtRnZB90jpkMG/uvR6MF9IO4bAzzdWj9Iq/Zn/4qLCszwyhDU0RHd6+YtOYMMU746ac8 EXWRIrhaoicwYoLBLa7GUbXm1aApy2pCx1xwJleBXE5tMCyN2Dj9c6Zj2G5hOl0jbb4CRv8x7 GEDHE2+blNzf8xdT99rN+5Rvr7xUT7G/U0aUSylUonzv0XeoJunMnybWv+V54WYfFQL15DhY9 QGU3gTHlUxHhIyRbBKki00jKR82IIlZ1JQbaJPRkl/JjHHsuq1OoZ+avO2LwdXlWd49x5kyJ2 fruZGF3biWuVlCdGuSK5wRPVARXllqyQXxPuDXVhGCHnLKcy6AAcPDcVL3tH/90Ap/PvQkh7O b44kigHCD8Zuk3dR8H4qT2qt8yqy7lPdszPe24YRNVB+1ecnfivEu6iIBi6CbDjccu0P6ckfA hgPUH1uOjP0NyHsPJplwVT2t2KklAxTDH6DR/WmK/R58s2ycoirYTZHyHjM5NCJTLkmHuFiHe wgp7HUAWBq+7HGcUJIuPukOfq+uk3eOCIBAUZwUUZkx8U2XnoyRthWUUv00pdWJfZkAL+lkFA VAMPtB3O44+aKK0OJYJKmMqEFWUCYFYQ1OAbrP2s3Kgs3m4Rtb13qZ8CpfeAO8LPB6a4diMEX 66USa3xtIKTquAGHSVRipzpUYoSz+vC0kLuI0HJyW5sLdgUMZ50QQpeJrGxIV74bobpvK158O jyysAGBxonQPt/owQSdPuxMXv4PzNk+j1aEvvFnIvpUVhGjlZuETRshbD1B6OAtgByHv0XwKg YamsJcWJMSVu8A5a0t6O+NHPDnfDAflL75CPHZ8vxvddJOjIC5AijSdP15DwXa6jHT7ONh3bl Q7kjuq58WbU72fHke6rxTDW6yBEkGxefXJQM= Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The swim chip provides an implementation of both Apple's IWM and ISM floppy disk controllers. Split the existing implementation into separate register banks for each controller, whilst also switching the IWM registers from 16-bit to 8-bit as implemented in real hardware. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-13-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/block/swim.h | 15 +++----- hw/block/swim.c | 85 ++++++++++++++++++++++++----------------- hw/block/trace-events | 4 +- 3 files changed, 58 insertions(+), 46 deletions(-) diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h index 9b3dcb029d3f..1bc7635d0212 100644 --- a/include/hw/block/swim.h +++ b/include/hw/block/swim.h @@ -43,23 +43,18 @@ typedef struct FDrive { } FDrive; struct SWIMCtrl { - MemoryRegion iomem; + MemoryRegion swim; + MemoryRegion iwm; + MemoryRegion ism; FDrive drives[SWIM_MAX_FD]; int mode; /* IWM mode */ int iwm_switch; - uint16_t regs[8]; -#define IWM_PH0 0 -#define IWM_PH1 1 -#define IWM_PH2 2 -#define IWM_PH3 3 -#define IWM_MTR 4 -#define IWM_DRIVE 5 -#define IWM_Q6 6 -#define IWM_Q7 7 + uint8_t iwmregs[16]; uint8_t iwm_data; uint8_t iwm_mode; /* SWIM mode */ + uint8_t ismregs[16]; uint8_t swim_phase; uint8_t swim_mode; SWIMBus bus; diff --git a/hw/block/swim.c b/hw/block/swim.c index 7df36ea139cb..505718bdae3f 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -126,7 +126,14 @@ #define SWIM_HEDSEL 0x20 #define SWIM_MOTON 0x80 -static const char *swim_reg_names[] = { +static const char *iwm_reg_names[] = { + "PH0L", "PH0H", "PH1L", "PH1H", + "PH2L", "PH2H", "PH3L", "PH3H", + "MTROFF", "MTRON", "INTDRIVE", "EXTDRIVE", + "Q6L", "Q6H", "Q7L", "Q7H" +}; + +static const char *ism_reg_names[] = { "WRITE_DATA", "WRITE_MARK", "WRITE_CRC", "WRITE_PARAMETER", "WRITE_PHASE", "WRITE_SETUP", "WRITE_MODE0", "WRITE_MODE1", "READ_DATA", "READ_MARK", "READ_ERROR", "READ_PARAMETER", @@ -274,12 +281,11 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; - swimctrl->regs[reg >> 1] = reg & 1; - trace_swim_iwmctrl_write((reg >> 1), size, (reg & 1)); + swimctrl->iwmregs[reg] = value; + trace_swim_iwmctrl_write(reg, iwm_reg_names[reg], size, value); - if (swimctrl->regs[IWM_Q6] && - swimctrl->regs[IWM_Q7]) { - if (swimctrl->regs[IWM_MTR]) { + if (swimctrl->iwmregs[IWM_Q7H]) { + if (swimctrl->iwmregs[IWM_MTRON]) { /* data register */ swimctrl->iwm_data = value; } else { @@ -307,6 +313,12 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, swimctrl->mode = SWIM_MODE_SWIM; swimctrl->iwm_switch = 0; trace_swim_iwm_switch(); + + /* Switch to ISM registers */ + memory_region_del_subregion(&swimctrl->swim, + &swimctrl->iwm); + memory_region_add_subregion(&swimctrl->swim, 0x0, + &swimctrl->ism); } break; } @@ -317,28 +329,30 @@ static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) { SWIMCtrl *swimctrl = opaque; + uint8_t value; reg >>= REG_SHIFT; - swimctrl->regs[reg >> 1] = reg & 1; + value = swimctrl->iwmregs[reg]; + trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value); - trace_swim_iwmctrl_read((reg >> 1), size, (reg & 1)); - return 0; + return value; } -static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, - unsigned size) +static const MemoryRegionOps swimctrl_iwm_ops = { + .write = iwmctrl_write, + .read = iwmctrl_read, + .endianness = DEVICE_BIG_ENDIAN, +}; + +static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value, + unsigned size) { SWIMCtrl *swimctrl = opaque; - if (swimctrl->mode == SWIM_MODE_IWM) { - iwmctrl_write(opaque, reg, value, size); - return; - } - reg >>= REG_SHIFT; - trace_swim_swimctrl_write(reg, swim_reg_names[reg], size, value); + trace_swim_swimctrl_write(reg, ism_reg_names[reg], size, value); switch (reg) { case SWIM_WRITE_PHASE: @@ -359,15 +373,11 @@ static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value, } } -static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) +static uint64_t ismctrl_read(void *opaque, hwaddr reg, unsigned size) { SWIMCtrl *swimctrl = opaque; uint32_t value = 0; - if (swimctrl->mode == SWIM_MODE_IWM) { - return iwmctrl_read(opaque, reg, size); - } - reg >>= REG_SHIFT; switch (reg) { @@ -389,14 +399,14 @@ static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size) break; } - trace_swim_swimctrl_read(reg, swim_reg_names[reg], size, value); + trace_swim_swimctrl_read(reg, ism_reg_names[reg], size, value); return value; } -static const MemoryRegionOps swimctrl_mem_ops = { - .write = swimctrl_write, - .read = swimctrl_read, - .endianness = DEVICE_NATIVE_ENDIAN, +static const MemoryRegionOps swimctrl_ism_ops = { + .write = ismctrl_write, + .read = ismctrl_read, + .endianness = DEVICE_BIG_ENDIAN, }; static void sysbus_swim_reset(DeviceState *d) @@ -407,13 +417,13 @@ static void sysbus_swim_reset(DeviceState *d) ctrl->mode = 0; ctrl->iwm_switch = 0; - for (i = 0; i < 8; i++) { - ctrl->regs[i] = 0; - } ctrl->iwm_data = 0; ctrl->iwm_mode = 0; + memset(ctrl->iwmregs, 0, 16); + ctrl->swim_phase = 0; ctrl->swim_mode = 0; + memset(ctrl->ismregs, 0, 16); for (i = 0; i < SWIM_MAX_FD; i++) { fd_recalibrate(&ctrl->drives[i]); } @@ -425,9 +435,12 @@ static void sysbus_swim_init(Object *obj) Swim *sbs = SWIM(obj); SWIMCtrl *swimctrl = &sbs->ctrl; - memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimctrl, - "swim", 0x2000); - sysbus_init_mmio(sbd, &swimctrl->iomem); + memory_region_init(&swimctrl->swim, obj, "swim", 0x2000); + memory_region_init_io(&swimctrl->iwm, obj, &swimctrl_iwm_ops, swimctrl, + "iwm", 0x2000); + memory_region_init_io(&swimctrl->ism, obj, &swimctrl_ism_ops, swimctrl, + "ism", 0x2000); + sysbus_init_mmio(sbd, &swimctrl->swim); } static void sysbus_swim_realize(DeviceState *dev, Error **errp) @@ -437,6 +450,9 @@ static void sysbus_swim_realize(DeviceState *dev, Error **errp) qbus_init(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev, NULL); swimctrl->bus.ctrl = swimctrl; + + /* Default register set is IWM */ + memory_region_add_subregion(&swimctrl->swim, 0x0, &swimctrl->iwm); } static const VMStateDescription vmstate_fdrive = { @@ -456,10 +472,11 @@ static const VMStateDescription vmstate_swim = { VMSTATE_INT32(mode, SWIMCtrl), /* IWM mode */ VMSTATE_INT32(iwm_switch, SWIMCtrl), - VMSTATE_UINT16_ARRAY(regs, SWIMCtrl, 8), + VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 16), VMSTATE_UINT8(iwm_data, SWIMCtrl), VMSTATE_UINT8(iwm_mode, SWIMCtrl), /* SWIM mode */ + VMSTATE_UINT8_ARRAY(ismregs, SWIMCtrl, 16), VMSTATE_UINT8(swim_phase, SWIMCtrl), VMSTATE_UINT8(swim_mode, SWIMCtrl), /* Drives */ diff --git a/hw/block/trace-events b/hw/block/trace-events index c041ec45e312..ea84ad6c77ed 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -94,6 +94,6 @@ m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM" # swim.c swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 -swim_iwmctrl_read(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 -swim_iwmctrl_write(int reg, unsigned size, uint64_t value) "reg=%d size=%u value=0x%"PRIx64 +swim_iwmctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_iwmctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 swim_iwm_switch(void) "switch from IWM to SWIM mode" From patchwork Sun Oct 8 06:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D4C6E95A80 for ; Sun, 8 Oct 2023 06:25:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCw-000880-Fz; Sun, 08 Oct 2023 02:24:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCu-00086r-FK for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:04 -0400 Received: from mout.kundenserver.de ([217.72.192.75]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCs-0007n3-6t for qemu-devel@nongnu.org; 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envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland Update the IWM/ISM register block decoding to match the description given in the "SWIM Chip Users Reference". This allows us to validate the device response to the guest OS which currently only does just enough to indicate that the floppy drive is unavailable. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-14-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/block/swim.h | 8 +- hw/block/swim.c | 212 +++++++++++++++++++++++++--------------- hw/block/trace-events | 7 +- 3 files changed, 143 insertions(+), 84 deletions(-) diff --git a/include/hw/block/swim.h b/include/hw/block/swim.h index 1bc7635d0212..5f567e8d5957 100644 --- a/include/hw/block/swim.h +++ b/include/hw/block/swim.h @@ -50,13 +50,15 @@ struct SWIMCtrl { int mode; /* IWM mode */ int iwm_switch; - uint8_t iwmregs[16]; - uint8_t iwm_data; - uint8_t iwm_mode; + uint8_t iwm_latches; + uint8_t iwmregs[8]; /* SWIM mode */ uint8_t ismregs[16]; uint8_t swim_phase; uint8_t swim_mode; + uint8_t swim_status; + uint8_t pram[16]; + uint8_t pram_idx; SWIMBus bus; }; diff --git a/hw/block/swim.c b/hw/block/swim.c index 505718bdae3f..fd65c59f8a10 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -21,24 +21,28 @@ #include "hw/qdev-properties.h" #include "trace.h" + +/* IWM latch bits */ + +#define IWMLB_PHASE0 0 +#define IWMLB_PHASE1 1 +#define IWMLB_PHASE2 2 +#define IWMLB_PHASE3 3 +#define IWMLB_MOTORON 4 +#define IWMLB_DRIVESEL 5 +#define IWMLB_L6 6 +#define IWMLB_L7 7 + /* IWM registers */ -#define IWM_PH0L 0 -#define IWM_PH0H 1 -#define IWM_PH1L 2 -#define IWM_PH1H 3 -#define IWM_PH2L 4 -#define IWM_PH2H 5 -#define IWM_PH3L 6 -#define IWM_PH3H 7 -#define IWM_MTROFF 8 -#define IWM_MTRON 9 -#define IWM_INTDRIVE 10 -#define IWM_EXTDRIVE 11 -#define IWM_Q6L 12 -#define IWM_Q6H 13 -#define IWM_Q7L 14 -#define IWM_Q7H 15 +#define IWM_READALLONES 0 +#define IWM_READDATA 1 +#define IWM_READSTATUS0 2 +#define IWM_READSTATUS1 3 +#define IWM_READWHANDSHAKE0 4 +#define IWM_READWHANDSHAKE1 5 +#define IWM_WRITESETMODE 6 +#define IWM_WRITEDATA 7 /* SWIM registers */ @@ -62,8 +66,9 @@ #define REG_SHIFT 9 -#define SWIM_MODE_IWM 0 -#define SWIM_MODE_SWIM 1 +#define SWIM_MODE_STATUS_BIT 6 +#define SWIM_MODE_IWM 0 +#define SWIM_MODE_ISM 1 /* bits in phase register */ @@ -127,10 +132,8 @@ #define SWIM_MOTON 0x80 static const char *iwm_reg_names[] = { - "PH0L", "PH0H", "PH1L", "PH1H", - "PH2L", "PH2H", "PH3L", "PH3H", - "MTROFF", "MTRON", "INTDRIVE", "EXTDRIVE", - "Q6L", "Q6H", "Q7L", "Q7H" + "READALLONES", "READDATA", "READSTATUS0", "READSTATUS1", + "READWHANDSHAKE0", "READWHANDSHAKE1", "WRITESETMODE", "WRITEDATA" }; static const char *ism_reg_names[] = { @@ -274,68 +277,99 @@ static const TypeInfo swim_bus_info = { .instance_size = sizeof(SWIMBus), }; -static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value, +static void iwmctrl_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { SWIMCtrl *swimctrl = opaque; + uint8_t latch, reg, ism_bit; - reg >>= REG_SHIFT; + addr >>= REG_SHIFT; + + /* A3-A1 select a latch, A0 specifies the value */ + latch = (addr >> 1) & 7; + if (addr & 1) { + swimctrl->iwm_latches |= (1 << latch); + } else { + swimctrl->iwm_latches &= ~(1 << latch); + } + + reg = (swimctrl->iwm_latches & 0xc0) >> 5 | + (swimctrl->iwm_latches & 0x10) >> 4; swimctrl->iwmregs[reg] = value; trace_swim_iwmctrl_write(reg, iwm_reg_names[reg], size, value); - if (swimctrl->iwmregs[IWM_Q7H]) { - if (swimctrl->iwmregs[IWM_MTRON]) { - /* data register */ - swimctrl->iwm_data = value; - } else { - /* mode register */ - swimctrl->iwm_mode = value; - /* detect sequence to switch from IWM mode to SWIM mode */ - switch (swimctrl->iwm_switch) { - case 0: - if (value == 0x57) { - swimctrl->iwm_switch++; - } - break; - case 1: - if (value == 0x17) { - swimctrl->iwm_switch++; - } - break; - case 2: - if (value == 0x57) { - swimctrl->iwm_switch++; - } - break; - case 3: - if (value == 0x57) { - swimctrl->mode = SWIM_MODE_SWIM; - swimctrl->iwm_switch = 0; - trace_swim_iwm_switch(); - - /* Switch to ISM registers */ - memory_region_del_subregion(&swimctrl->swim, - &swimctrl->iwm); - memory_region_add_subregion(&swimctrl->swim, 0x0, - &swimctrl->ism); - } - break; + switch (reg) { + case IWM_WRITESETMODE: + /* detect sequence to switch from IWM mode to SWIM mode */ + ism_bit = (value & (1 << SWIM_MODE_STATUS_BIT)); + + switch (swimctrl->iwm_switch) { + case 0: + if (ism_bit) { /* 1 */ + swimctrl->iwm_switch++; + } + break; + case 1: + if (!ism_bit) { /* 0 */ + swimctrl->iwm_switch++; + } + break; + case 2: + if (ism_bit) { /* 1 */ + swimctrl->iwm_switch++; } + break; + case 3: + if (ism_bit) { /* 1 */ + swimctrl->iwm_switch++; + + swimctrl->mode = SWIM_MODE_ISM; + swimctrl->swim_mode |= (1 << SWIM_MODE_STATUS_BIT); + swimctrl->iwm_switch = 0; + trace_swim_switch_to_ism(); + + /* Switch to ISM registers */ + memory_region_del_subregion(&swimctrl->swim, &swimctrl->iwm); + memory_region_add_subregion(&swimctrl->swim, 0x0, + &swimctrl->ism); + } + break; } + break; + default: + break; } } -static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size) +static uint64_t iwmctrl_read(void *opaque, hwaddr addr, unsigned size) { SWIMCtrl *swimctrl = opaque; - uint8_t value; + uint8_t latch, reg, value; - reg >>= REG_SHIFT; + addr >>= REG_SHIFT; - value = swimctrl->iwmregs[reg]; - trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value); + /* A3-A1 select a latch, A0 specifies the value */ + latch = (addr >> 1) & 7; + if (addr & 1) { + swimctrl->iwm_latches |= (1 << latch); + } else { + swimctrl->iwm_latches &= ~(1 << latch); + } + + reg = (swimctrl->iwm_latches & 0xc0) >> 5 | + (swimctrl->iwm_latches & 0x10) >> 4; + + switch (reg) { + case IWM_READALLONES: + value = 0xff; + break; + default: + value = 0; + break; + } + trace_swim_iwmctrl_read(reg, iwm_reg_names[reg], size, value); return value; } @@ -352,7 +386,7 @@ static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value, reg >>= REG_SHIFT; - trace_swim_swimctrl_write(reg, ism_reg_names[reg], size, value); + trace_swim_ismctrl_write(reg, ism_reg_names[reg], size, value); switch (reg) { case SWIM_WRITE_PHASE: @@ -360,14 +394,31 @@ static void ismctrl_write(void *opaque, hwaddr reg, uint64_t value, break; case SWIM_WRITE_MODE0: swimctrl->swim_mode &= ~value; + /* Any access to MODE0 register resets PRAM index */ + swimctrl->pram_idx = 0; + + if (!(swimctrl->swim_mode & (1 << SWIM_MODE_STATUS_BIT))) { + /* Clearing the mode bit switches to IWM mode */ + swimctrl->mode = SWIM_MODE_IWM; + swimctrl->iwm_latches = 0; + trace_swim_switch_to_iwm(); + + /* Switch to IWM registers */ + memory_region_del_subregion(&swimctrl->swim, &swimctrl->ism); + memory_region_add_subregion(&swimctrl->swim, 0x0, + &swimctrl->iwm); + } break; case SWIM_WRITE_MODE1: swimctrl->swim_mode |= value; break; + case SWIM_WRITE_PARAMETER: + swimctrl->pram[swimctrl->pram_idx++] = value; + swimctrl->pram_idx &= 0xf; + break; case SWIM_WRITE_DATA: case SWIM_WRITE_MARK: case SWIM_WRITE_CRC: - case SWIM_WRITE_PARAMETER: case SWIM_WRITE_SETUP: break; } @@ -390,16 +441,24 @@ static uint64_t ismctrl_read(void *opaque, hwaddr reg, unsigned size) value = SWIM_SENSE; } break; + case SWIM_READ_PARAMETER: + value = swimctrl->pram[swimctrl->pram_idx++]; + swimctrl->pram_idx &= 0xf; + break; + case SWIM_READ_STATUS: + value = swimctrl->swim_status & ~(1 << SWIM_MODE_STATUS_BIT); + if (swimctrl->swim_mode == SWIM_MODE_ISM) { + value |= (1 << SWIM_MODE_STATUS_BIT); + } + break; case SWIM_READ_DATA: case SWIM_READ_MARK: case SWIM_READ_ERROR: - case SWIM_READ_PARAMETER: case SWIM_READ_SETUP: - case SWIM_READ_STATUS: break; } - trace_swim_swimctrl_read(reg, ism_reg_names[reg], size, value); + trace_swim_ismctrl_read(reg, ism_reg_names[reg], size, value); return value; } @@ -417,13 +476,11 @@ static void sysbus_swim_reset(DeviceState *d) ctrl->mode = 0; ctrl->iwm_switch = 0; - ctrl->iwm_data = 0; - ctrl->iwm_mode = 0; - memset(ctrl->iwmregs, 0, 16); + memset(ctrl->iwmregs, 0, sizeof(ctrl->iwmregs)); ctrl->swim_phase = 0; ctrl->swim_mode = 0; - memset(ctrl->ismregs, 0, 16); + memset(ctrl->ismregs, 0, sizeof(ctrl->ismregs)); for (i = 0; i < SWIM_MAX_FD; i++) { fd_recalibrate(&ctrl->drives[i]); } @@ -472,9 +529,8 @@ static const VMStateDescription vmstate_swim = { VMSTATE_INT32(mode, SWIMCtrl), /* IWM mode */ VMSTATE_INT32(iwm_switch, SWIMCtrl), - VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 16), - VMSTATE_UINT8(iwm_data, SWIMCtrl), - VMSTATE_UINT8(iwm_mode, SWIMCtrl), + VMSTATE_UINT8(iwm_latches, SWIMCtrl), + VMSTATE_UINT8_ARRAY(iwmregs, SWIMCtrl, 8), /* SWIM mode */ VMSTATE_UINT8_ARRAY(ismregs, SWIMCtrl, 16), VMSTATE_UINT8(swim_phase, SWIMCtrl), diff --git a/hw/block/trace-events b/hw/block/trace-events index ea84ad6c77ed..bab21d3a1ca8 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -92,8 +92,9 @@ m25p80_binding(void *s) "[%p] Binding to IF_MTD drive" m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM" # swim.c -swim_swimctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 -swim_swimctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_ismctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 +swim_ismctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 swim_iwmctrl_read(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 swim_iwmctrl_write(int reg, const char *name, unsigned size, uint64_t value) "reg=%d [%s] size=%u value=0x%"PRIx64 -swim_iwm_switch(void) "switch from IWM to SWIM mode" +swim_switch_to_ism(void) "switch from IWM to ISM mode" +swim_switch_to_iwm(void) "switch from ISM to IWM mode" From patchwork Sun Oct 8 06:23:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EB65E95A80 for ; Sun, 8 Oct 2023 06:27:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCx-000889-2O; Sun, 08 Oct 2023 02:24:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCu-000871-Td for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:04 -0400 Received: from mout.kundenserver.de ([217.72.192.73]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCs-0007nI-Ur for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:04 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MAP77-1qiWOQ0GGB-00BvUp; Sun, 08 Oct 2023 08:24:01 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 14/20] mac_via: work around underflow in TimeDBRA timing loop in SETUPTIMEK Date: Sun, 8 Oct 2023 08:23:43 +0200 Message-ID: <20231008062349.2733552-15-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:p+vj7gnh0rVDtLP+EXazS12NzyHD7epKzxM62FUSFiEFU+umWes HyC8Y77DNSGOFsqT5Fm/ruvfDU5ZQuG1ymiXQlVqgfHGaLnvaARUZo7zjC4aVOsx+0loMDz vTA/aepNn4fJjLDMBK+1x1wrKcJbQekSqoqrodFanM+Cugj+rLH7bjmKDNN5LAClnzuBLDJ xAbD2SA0jbf753bg84GAg== UI-OutboundReport: notjunk:1;M01:P0:iZGMJlO5NSA=;EyDWnZ/XBuB7DUaGNAKByvdJSqy 4UqM9mDECsO7Mkdi0DXe6YAN0eZ7Qm23PN8bFePUZpGJHzVgenu2uD8RFpvSuQMNlwlS0qhpJ CA1lSOgJU2s/FEXOU2TgzGP0unM2ww8mcR+IwmSC46/RF3cq9QLxCwp3MaAOerAypWqEGtC41 y7WFGFUfbxDMddu/n5ROpOW1xfCw1JHlbNRsb6NwvaKs8zWd41dJbcwu3cJhg0f9S4xcvCdCZ TdytXiknA1lCQektAvUqoyw8fCO6ylEDCleKSLJ+opMGyhfwrwamjKLx0uGZ9P2HS/Z8Ar/wo d3bimUWMjHQMFMD9LUpe2M7ys73x8Fk5O2+Y0OjQT5e8uok+SU8gZT9BX5vGRZrYIC0skNPWd 6s+og/0EidjJsG5fK+hlXWf3Nm8zGDTjfalp3FmhMDDx8Y1oI/VkE3rGODsBBGUZvqhi8w4DX 0C1SC73sqIULspKdm7Cf1LIXDgEs5Arb04kgvrlmuvmJk+eulCgY84VHlH+D1Tj1wcFONph8p c+7WtXNtNQRR0jVOSfBIlG1tYlJhUxTnNX1EoD9AiQhfHt5Vx3/RnlBEnKLteYQL9LTp+upwV cqy3Su3hOXs8dXR7tKIb4Pt33yHggG/0sFQv9AeN8wm5xAEO2Jbn6hr9yN3WkQ2o2DaXvJyh/ C1HTymsHFsH7g8xYnN7Cp++8UGfVfIy2+7lRsAcVS79+gcd2d9rHWKxHc0L6BpGMr4Zz3/Xoh kVZyk9lUSd9r1lCACKzTVc2GQYCUDSsHIWyniVtVibAA2Fo2/K3MIot3XoPim/1Bl/AK6L5ar e50HLLZBbgnzOZB9dtp5C4fYw3I8pLD4S9KejdL5IseAcw0raDLNkhbNnRRftfHsNfnXZDcHy NkuJTo4FuWgEV6A== Received-SPF: none client-ip=217.72.192.73; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The MacOS toolbox ROM calculates the number of branches that can be executed per millisecond as part of its timer calibration. Since modern hosts are considerably quicker than original hardware, the negative counter reaches zero before the calibration completes leading to division by zero later in CALCULATESLOD. Instead of trying to fudge the timing loop (which won't work for TimeDBRA/TimeSCCDB anyhow), use the pattern of access to the VIA1 registers to detect when SETUPTIMEK has finished executing and write some well-known good timer values to TimeDBRA and TimeSCCDB taken from real hardware with a suitable scaling factor. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-15-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/misc/mac_via.h | 3 + hw/misc/mac_via.c | 115 ++++++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 1 + 3 files changed, 119 insertions(+) diff --git a/include/hw/misc/mac_via.h b/include/hw/misc/mac_via.h index 422da43bf90a..63cdcf7c69c9 100644 --- a/include/hw/misc/mac_via.h +++ b/include/hw/misc/mac_via.h @@ -74,6 +74,9 @@ struct MOS6522Q800VIA1State { int64_t next_second; QEMUTimer *sixty_hz_timer; int64_t next_sixty_hz; + + /* SETUPTIMEK hack */ + int timer_hack_state; }; diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index e87a1b82d8c5..f2ccb12d643b 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -16,6 +16,7 @@ */ #include "qemu/osdep.h" +#include "exec/address-spaces.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/irq.h" @@ -871,6 +872,112 @@ static void via1_auxmode_update(MOS6522Q800VIA1State *v1s) } } +/* + * Addresses and real values for TimeDBRA/TimeSCCB to allow timer calibration + * to succeed (NOTE: both values have been multiplied by 3 to cope with the + * speed of QEMU execution on a modern host + */ +#define MACOS_TIMEDBRA 0xd00 +#define MACOS_TIMESCCB 0xd02 + +#define MACOS_TIMEDBRA_VALUE (0x2a00 * 3) +#define MACOS_TIMESCCB_VALUE (0x079d * 3) + +static bool via1_is_toolbox_timer_calibrated(void) +{ + /* + * Indicate whether the MacOS toolbox has been calibrated by checking + * for the value of our magic constants + */ + uint16_t timedbra = lduw_be_phys(&address_space_memory, MACOS_TIMEDBRA); + uint16_t timesccdb = lduw_be_phys(&address_space_memory, MACOS_TIMESCCB); + + return (timedbra == MACOS_TIMEDBRA_VALUE && + timesccdb == MACOS_TIMESCCB_VALUE); +} + +static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr, + uint64_t val, int size) +{ + /* + * Work around timer calibration to ensure we that we have non-zero and + * known good values for TIMEDRBA and TIMESCCDB. + * + * This works by attempting to detect the reset and calibration sequence + * of writes to VIA1 + */ + int old_timer_hack_state = v1s->timer_hack_state; + + switch (v1s->timer_hack_state) { + case 0: + if (addr == VIA_REG_PCR && val == 0x22) { + /* VIA_REG_PCR: configure VIA1 edge triggering */ + v1s->timer_hack_state = 1; + } + break; + case 1: + if (addr == VIA_REG_T2CL && val == 0xc) { + /* VIA_REG_T2CL: low byte of 1ms counter */ + if (!via1_is_toolbox_timer_calibrated()) { + v1s->timer_hack_state = 2; + } else { + v1s->timer_hack_state = 0; + } + } + break; + case 2: + if (addr == VIA_REG_T2CH && val == 0x3) { + /* + * VIA_REG_T2CH: high byte of 1ms counter (very likely at the + * start of SETUPTIMEK) + */ + if (!via1_is_toolbox_timer_calibrated()) { + v1s->timer_hack_state = 3; + } else { + v1s->timer_hack_state = 0; + } + } + break; + case 3: + if (addr == VIA_REG_IER && val == 0x20) { + /* + * VIA_REG_IER: update at end of SETUPTIMEK + * + * Timer calibration has finished: unfortunately the values in + * TIMEDBRA (0xd00) and TIMESCCDB (0xd02) are so far out they + * cause divide by zero errors. + * + * Update them with values obtained from a real Q800 but with + * a x3 scaling factor which seems to work well + */ + stw_be_phys(&address_space_memory, MACOS_TIMEDBRA, + MACOS_TIMEDBRA_VALUE); + stw_be_phys(&address_space_memory, MACOS_TIMESCCB, + MACOS_TIMESCCB_VALUE); + + v1s->timer_hack_state = 4; + } + break; + case 4: + /* + * This is the normal post-calibration timer state: we should + * generally remain here unless we detect the A/UX calibration + * loop, or a write to VIA_REG_PCR suggesting a reset + */ + if (addr == VIA_REG_PCR && val == 0x22) { + /* Looks like there has been a reset? */ + v1s->timer_hack_state = 1; + } + break; + default: + g_assert_not_reached(); + } + + if (old_timer_hack_state != v1s->timer_hack_state) { + trace_via1_timer_hack_state(v1s->timer_hack_state); + } +} + static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) { MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); @@ -896,6 +1003,9 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, MOS6522State *ms = MOS6522(v1s); addr = (addr >> 9) & 0xf; + + via1_timer_calibration_hack(v1s, addr, val, size); + mos6522_write(ms, addr, val, size); switch (addr) { @@ -1008,6 +1118,9 @@ static void mos6522_q800_via1_reset_hold(Object *obj) adb_set_autopoll_enabled(adb_bus, true); v1s->cmd = REG_EMPTY; v1s->alt = REG_EMPTY; + + /* Timer calibration hack */ + v1s->timer_hack_state = 0; } static void mos6522_q800_via1_realize(DeviceState *dev, Error **errp) @@ -1100,6 +1213,8 @@ static const VMStateDescription vmstate_q800_via1 = { VMSTATE_INT64(next_second, MOS6522Q800VIA1State), VMSTATE_TIMER_PTR(sixty_hz_timer, MOS6522Q800VIA1State), VMSTATE_INT64(next_sixty_hz, MOS6522Q800VIA1State), + /* Timer hack */ + VMSTATE_INT32(timer_hack_state, MOS6522Q800VIA1State), VMSTATE_END_OF_LIST() } }; diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 29bc531d4d3e..5a998f5e4e38 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -272,6 +272,7 @@ via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s da via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" via1_auxmode(int mode) "setting auxmode to %d" +via1_timer_hack_state(int state) "setting timer_hack_state to %d" # grlib_ahb_apb_pnp.c grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x" From patchwork Sun Oct 8 06:23:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3857E95A67 for ; Sun, 8 Oct 2023 06:27:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCx-00088A-3e; Sun, 08 Oct 2023 02:24:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCv-00087U-Cs for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:05 -0400 Received: from mout.kundenserver.de ([212.227.17.24]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCt-0007ne-Ll for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:05 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1MVMJ7-1qyxsc40hT-00SMzH; Sun, 08 Oct 2023 08:24:02 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 15/20] mac_via: workaround NetBSD ADB bus enumeration issue Date: Sun, 8 Oct 2023 08:23:44 +0200 Message-ID: <20231008062349.2733552-16-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:v4IxPU9uPZV6gC7Dl+yog1tVLzzvEkppU8r3gOYvwuEEqDO6rL0 WOfOInyYIvC6b4B1m2TjLrVQF7vy5DFjdxF5rUpsgPGR7x4bZnqBClD5U8dTjrmjq1FX5Pc kFP7f1ESKQAN9Ee78+NzttCiszGTPkBrlY8bu8PFImCa8w139LbB9/8/YQYWPonNMX4wEfg bR2E2RD8NcBNJaZwg9aSQ== UI-OutboundReport: notjunk:1;M01:P0:Vyfj6YTztmw=;VTZHvP2kyY2pQL2yO4fStZrWg1j u79AylKF6LpmdxX51Z2OgldxaA+HyvLSSUAF8mdAkP5uDKOpE3jGptUzqP0RJZkjnZ50nLmO7 w8JGWBloGLMkU1QRziRRoXD6zfmS9UfuvMesfFk2c4UtTYxr3Er8NfIS1PznEwUyRFJ8Itt9i e2QHXfom9LsNLzpN/6jOVSEnpQ0yTD2Rr15sNQ6c26zn9oo3yTKCFRnr1DxpWMr/c68YtLZsx 88UxOdTOjUaCTlcfvx3LIWHqSS4Lu4XQktezmVWmTABPKjEinxahiYpU84o3ER35VINKniX0L Ry9VrnEUGB6M5hHHkdzhUUGVedZakzuE5kycrmY5K0cJRomTDY5npuN1B4oFcxVuHE1ULVnFH Q8qMr4jCsAW2eExdZKUMZOuXKaBy4TrU3i+/w0AAa0QXBUwC1NpGscKHzYCNf8I9fTKgvFzoe /lNahyyuWiD/0nmTVqva1+e0u4A4NnQjG5xc7YHdFk+wwGUeMzs5KbzPcSkHZyksCEZQ24TQo NJDU+z4c2hDN7i9Y2B988iIvo+mqzRKSEnA6M81jTNI6Ylga8diFgN/LrJwRtBTx+tBFOuQvl +4iieDreDHfrYtiNttf3NGWWsZ49eg+v38wohhrp8Hxnu1ayjQB8Dv5X1cFsAbAdrhSBIRTG4 kgijQh4wmBaGXO6qI1by/oJwCmgqDq+N5iEbMZNq/+YS+e+MrH8mB8X7DHfi1bY2UL09723dY 9vYOHLELNIHaNA30HMh9naD5YBz3KjeV3YeobxxNN3TGTVFD20fHFC+WZwpCssMa5xUvL3ZaX iE1LDeO9BHEFEul8H++A0o9q5tpY/0VK0inf/9yI690YfpsW3cpOXhwpEOknFso4h+3u8DuR0 jN0mlB0eIXyA3dA== Received-SPF: none client-ip=212.227.17.24; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE first as detailed in the ADB protocol. Add a workaround to detect this condition at the start of ADB enumeration and send the next command written to SR after a ADB_BUSRESET onto the bus regardless, even if we don't detect a state transition to ADB_STATE_NEW. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-16-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/misc/mac_via.c | 34 ++++++++++++++++++++++++++++++++++ hw/misc/trace-events | 1 + 2 files changed, 35 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index f2ccb12d643b..9f9c2815d0e9 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1001,6 +1001,8 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, { MOS6522Q800VIA1State *v1s = MOS6522_Q800_VIA1(opaque); MOS6522State *ms = MOS6522(v1s); + int oldstate, state; + int oldsr = ms->sr; addr = (addr >> 9) & 0xf; @@ -1016,6 +1018,38 @@ static void mos6522_q800_via1_write(void *opaque, hwaddr addr, uint64_t val, v1s->last_b = ms->b; break; + + case VIA_REG_SR: + { + /* + * NetBSD assumes it can send its first ADB command after sending + * the ADB_BUSRESET command in ADB_STATE_NEW without changing the + * state back to ADB_STATE_IDLE first as detailed in the ADB + * protocol. + * + * Add a workaround to detect this condition at the start of ADB + * enumeration and send the next command written to SR after a + * ADB_BUSRESET onto the bus regardless, even if we don't detect a + * state transition to ADB_STATE_NEW. + * + * Note that in my tests the NetBSD state machine takes one ADB + * operation to recover which means the probe for an ADB device at + * address 1 always fails. However since the first device is at + * address 2 then this will work fine, without having to come up + * with a more complicated and invasive solution. + */ + oldstate = (v1s->last_b & VIA1B_vADB_StateMask) >> + VIA1B_vADB_StateShift; + state = (ms->b & VIA1B_vADB_StateMask) >> VIA1B_vADB_StateShift; + + if (oldstate == ADB_STATE_NEW && state == ADB_STATE_NEW && + (ms->acr & VIA1ACR_vShiftOut) && + oldsr == 0 /* ADB_BUSRESET */) { + trace_via1_adb_netbsd_enum_hack(); + adb_via_send(v1s, state, ms->sr); + } + } + break; } } diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 5a998f5e4e38..24ba7cc4d0e9 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -271,6 +271,7 @@ via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "secto via1_adb_send(const char *state, uint8_t data, const char *vadbint) "state %s data=0x%02x vADBInt=%s" via1_adb_receive(const char *state, uint8_t data, const char *vadbint, int status, int index, int size) "state %s data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size) "data=0x%02x vADBInt=%s status=0x%x index=%d size=%d" +via1_adb_netbsd_enum_hack(void) "using NetBSD enum hack" via1_auxmode(int mode) "setting auxmode to %d" via1_timer_hack_state(int state) "setting timer_hack_state to %d" From patchwork Sun Oct 8 06:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68F16E95A67 for ; Sun, 8 Oct 2023 06:26:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCy-00089J-LI; Sun, 08 Oct 2023 02:24:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCw-000882-OG for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:06 -0400 Received: from mout.kundenserver.de ([217.72.192.73]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCv-0007oD-6m for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:06 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N7yuz-1rbc5Q0ct9-0151C7; Sun, 08 Oct 2023 08:24:03 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 16/20] mac_via: implement ADB_STATE_IDLE state if shift register in input mode Date: Sun, 8 Oct 2023 08:23:45 +0200 Message-ID: <20231008062349.2733552-17-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:qF0L7i4wM1AvWGjYWZcBEbtH6ZZI79csFVpFJXbWrWjpKtsWYq8 7D6dKBugAPDdPjqdeMAGaigp+G7dZhGdfhlxwie1gs6h5EppA9BjUHUhLNfwN0sbe3MEvi+ oGnGtEpivLM69GDGr30FFjqxxoGieiJ4TfYeWBvBkOeMWGVJbUEmQQ7CjoBgTz3NhMe89mM DrKMiTTMdeOOCZyEwSKbQ== UI-OutboundReport: notjunk:1;M01:P0:EP++qngpSiU=;x+42k7SvSYhcywH/DpVOtBv8kb5 jMpgkvr2EqFa5HxbeTlKGXdG13GqJNZPpiXbMbNUdltTCUbWljkwyCgyUqWyyRLuCMLYA2Cr9 3uHcApMRNTsprPU1SXWgaJEnwQIynHsiC5D+8l139zC4LoXprTYLa0YiAfyX5SztnF2s6g1Z5 lwiV1AA3WDO7yAcBpO+IHVtmwqwc+920ULqspT+NailSkicjBc5gXxOQqTifGvmZiAkQRNbYr SNTIt/TbKfrtBNVVhKAqP1sLdOkWKIQeOncCMqgXONfdWAwWy0uIbIwmGHUH5BvRczDr/JHwo alKe/Ny2/HPlYH3tzjNj1FYrQHLyKxQAl0IxQMs5RonITHo7L9n3S386L1pa8nSkkxBK9M+DO mTQp/FN/ChqTycGzQ3N/C6gXCwo1Ex7JwVUiqA4bYjuTOt9TvyWPoTSyQM+fNh4szcGF1Cbeh Zwy/Cbhr/vwqfB3cqHM0NR5TRdAc1GqrYw1dLtmovaJ4cBgvleI6+fFpw7ygsqGUaat230BID 6zUPbwLkHhZHVtkoVafn7admRfbgZYMCKbKKRW5diWu6AEZvmKtMjXdlffd0WnpNRtyMDlTkK APhIYtfd9khIcZTWeT/vITvC248kJdIQ3xvwq8zYyVCcRL2DahA3Y63WhXojRQSwMMfC6dgHa aF4aMmHP4CjpBVO7JUVPpL5jH8hf6LiaeD9DTI07EMfnFxNxeZEtXx+f5iBmALqqsKgqVsnP3 Wq+imCote+NGfxiVm9h16H4Yz9F7c18at/hgIeQhT128AlUVxaU9ZHktXY6oyXsX6P9+uQNgN mH5aFQy9kHsiYdGvmR3iisI9N+nHZUmENlADLfKYQol9HixKCT56pgWw0LCTF1UmUGIBprDoP BIIoOLmwdFT0eiw== Received-SPF: none client-ip=217.72.192.73; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland NetBSD switches directly to IDLE state without switching the shift register to input mode. Duplicate the existing ADB_STATE_IDLE logic in input mode from when the shift register is in output mode which allows the ADB autopoll handler to handle the response. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-17-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/misc/mac_via.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 9f9c2815d0e9..3c41d6263d45 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -702,6 +702,12 @@ static void adb_via_send(MOS6522Q800VIA1State *v1s, int state, uint8_t data) break; case ADB_STATE_IDLE: + ms->b |= VIA1B_vADBInt; + adb_autopoll_unblock(adb_bus); + + trace_via1_adb_send("IDLE", data, + (ms->b & VIA1B_vADBInt) ? "+" : "-"); + return; } From patchwork Sun Oct 8 06:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52C2BE95A67 for ; Sun, 8 Oct 2023 06:26:16 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpND1-0008AV-BQ; Sun, 08 Oct 2023 02:24:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCx-00088C-6a for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:07 -0400 Received: from mout.kundenserver.de ([217.72.192.73]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCv-0007oe-Ja for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:06 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1McYP5-1rSHKY3uBR-00cz7l; Sun, 08 Oct 2023 08:24:04 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 17/20] mac_via: always clear ADB interrupt when switching to A/UX mode Date: Sun, 8 Oct 2023 08:23:46 +0200 Message-ID: <20231008062349.2733552-18-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:BMXWP8Q34Sevebo8reZLo4kp0iF+VOdKjvSubFk/7siirdb48rW TXD14h7xqEI75GQCstmIm/thKPUroHl+46tqSrH+6jWQChKd1fn1CtOtpEZWL1ErPFyQElZ Dr6dMcgm+B5wPutYsRWM+b1SYjyhss3SHPcn3UrcnoOYe0Jt4J7KW5vFlz1RHc0cS/r4UeV dgffNTAOq0NNAL24NY0iQ== UI-OutboundReport: notjunk:1;M01:P0:U6M/anJJmTQ=;7B77d0RO5+zDTjLzu47e44auR6S w9ZinduBgCuPyl+C/IddLuCEpBh83T73S8eMfMzSyW1vnHd52kIBaVk0VxfFB4PmHfdeNBRpv LTsi16D4m/LWstLlmaUS8l5TETY1aAHbVkmPIfAIDMJkg7NBT4eoK0+rSIeWS0KzO2cLKna3O qBUAnYGOnuiyTR1w/VvNUZJRRFdby03UmnHyl9uckQnQZJR3KoEy1LUSSgSC0S45ydKyLsoG2 2GqMtl8WHwIfBeutU2S5BzYUinoa3k798/13/li5bxse4HM+deRStRiBfudBrBZ96wRx4Ro34 mNlvVNIEtH57LEPnpn31cr6gDG6qRNB57ZbqGZxIsucTH+R4+Ondr9bp7gV8JOteN18B8kcxq 1rMogLhgb/zexGFUwKZmIl/mjWFejDiQG2tzdwgH+Dur5J6KIRQ45x7HP3Iw8fxX21qd/4elr s9PpPe4IBWFJB2li9FXJGDVVTqdKMTdB/02bdqlCiPEc2VN7nYo3Ml6YIphcgqsYX+3IOc0ZW 69vKfErV16yUkwcsJflCqRtierGbORGuf9eMi2HI9J8RLdulm9x5Z6ee7UTs7T9MB8OmSmgSJ uumcG288xwnVOsZT5nuaRO5BoWQeBYo4GmVeKCRWau0plHVoqqq7gX9K5LUUb3gnNBgVbcLSl 8ICTBeVUg4S6x1EO1rxy8XxCv254EEVvGj5Hqg/ebDMrawDu1YvOX2177ad5thLeVn/owQWr8 8UOGZeKhj7CJkC8PMNRii/SqFEor4vxr4SWXKxJWxx05rNMNEvQ6ddpZLOyU6Pv0ZYAt1n752 9obVd0ovLp8aCvkdCKYjJTZJNPGoYPp4iyMciEXjSelMMADAlgCSy2beuxsWyxarX7DCs1CVA j/IU8rt6RbQvniQ== Received-SPF: none client-ip=217.72.192.73; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland When the NetBSD kernel initialises it can leave the ADB interrupt asserted depending upon where in the ADB poll cycle the MacOS ADB interrupt handler is when the NetBSD kernel disables interrupts. The NetBSD ADB driver uses the ADB interrupt state to determine if the ADB is busy and refuses to send ADB commands unless it is clear. To ensure that this doesn't happen, always clear the ADB interrupt when switching to A/UX mode to ensure that the bus enumeration always occurs. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-18-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/misc/mac_via.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 3c41d6263d45..500ece5872bd 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -875,6 +875,15 @@ static void via1_auxmode_update(MOS6522Q800VIA1State *v1s) if (irq != oldirq) { trace_via1_auxmode(irq); qemu_set_irq(v1s->auxmode_irq, irq); + + /* + * Clear the ADB interrupt. MacOS can leave VIA1B_vADBInt asserted + * (low) if a poll sequence doesn't complete before NetBSD disables + * interrupts upon boot. Fortunately NetBSD switches to the so-called + * "A/UX" interrupt mode after it initialises, so we can use this as + * a convenient place to clear the ADB interrupt for now. + */ + s->b |= VIA1B_vADBInt; } } From patchwork Sun Oct 8 06:23:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53F65E95A67 for ; Sun, 8 Oct 2023 06:26:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpNCz-00089Y-5l; Sun, 08 Oct 2023 02:24:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCx-00088g-W4 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:08 -0400 Received: from mout.kundenserver.de ([212.227.17.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCw-0007p8-AW for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:07 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue107 [212.227.15.183]) with ESMTPSA (Nemesis) id 1N94qX-1rciY72iYR-0167ep; Sun, 08 Oct 2023 08:24:04 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 18/20] q800: add ESCC alias at 0xc000 Date: Sun, 8 Oct 2023 08:23:47 +0200 Message-ID: <20231008062349.2733552-19-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:vw+iz5BEXXobm8IH3FdHr+I+rMOfjc2Op2xLhAK5La5DmrIZelH weyZYpZbYNQzAs6IGfmkNjpFrf6MGYL3U0c97aLe87HQUebUSRwRUvCi1Pz8EDbYdTZSkwL LJXryU/f6eK4A2WJxRvn09JhDlVUc2pVr+oHakXGNXOQaKg3DWJd0+28JHPsx6LL9rNFrK8 2Xr6OsdpBbLbBKhlU8Klg== UI-OutboundReport: notjunk:1;M01:P0:+aUfgHWY+1A=;Ym33FCTJFlzpCLLvrX8K/Mf7slB jNoE7iWOkMCF+EYP9bWLAosmbFEOj+iJeK+ZyQ6F4Uv14FtdZygIbHvTupUNgMpjMur9V7OA4 eqTQiRn4/I+EhSMVFiPthzBztzHvqhwxsURuLh09WTYSs+yWbX9I6nGByGQZfLX8OFNOBT5dR bglEnBN/bufwR4f7RggF1Rdy1DqiQqO6ZSk4OOtNIlcFFMxe9HdZ7an8JnB+Vfgx6suipsAB7 QsNBzk2W1652zeJgLJdLs9UQqq2DywCrH0+jaDN/z5mp6OYNmUYCgsi1RwrRWvk/kf6lrjsTL 8BXR9f1cY6vIE+Bbfx9eWXUzkIx/71NR+NzAAUec/R9sHJ7bsUuJxpCDCxJaMpIYw7mBO2XfL wuGD0FJNtsw2B0PH8Y6oYs8pJ0jRVGnnNmgL5LUcEnGSdJCmFEFTyBEzz3Ei8z8yMx33C0aAD Ef3zgYYWVZjkVRix1MtI18A7noKDVkOIDJue5ir+QZtI1+UaDDt45e23ECvNCjEoZPkeytnPd mMuRJUiXZbxLg0HsUwF1YVhoRvTXMiAixnYns7PkLAZg8TFYb2AlyznAqa4yex1V8DOimJQQm nT7otXXjs+HlT6VINwtpQ3weFD2esfr8vl55dKVdtdkCJhP49et21dOiz6WxOKTV8KfF3HAiv zKFUhpOv2FSpPqiAA2nYzpI2v8S47bYSQWvdE2ghuKXXHKpuYIDY4cxg/Se1+Qf4HOPsZ0GHH xt03ysYOYPcfsWv21srIYoRBEB6O8ryLI2zANuCwN8ZHXeV6GwB+PJf+JpKpYSqRsWxoeapZp SAKwk7LoEZ3s2XzWuLJ5r9tYEXpRGs4NXVGhnSMQT/FwQCaAGtmjD6LLeR4T96oem2eI0eJpz 0pGi6D/wPO/+SXQ== Received-SPF: none client-ip=212.227.17.10; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland Tests on real Q800 hardware show that the ESCC is addressable at multiple locations within the ESCC memory region - at least 0xc000, 0xc020 (as expected by the MacOS toolbox ROM) and 0xc040. All released NetBSD kernels before 10 use the 0xc000 address which causes a fatal error when running the MacOS booter. Add a single memory region alias at 0xc000 to enable NetBSD kernels to start booting under QEMU. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-19-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800.h | 1 + hw/m68k/q800.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index fbaacd88bd57..348eaf4703d0 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -67,6 +67,7 @@ struct Q800MachineState { MemoryRegion macio; MemoryRegion macio_alias; MemoryRegion machine_id; + MemoryRegion escc_alias; }; #define TYPE_Q800_MACHINE MACHINE_TYPE_NAME("q800") diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index ac3115d32844..27a0b3c08a98 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -451,6 +451,12 @@ static void q800_machine_init(MachineState *machine) memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE, sysbus_mmio_get_region(sysbus, 0)); + /* Create alias for NetBSD */ + memory_region_init_alias(&m->escc_alias, OBJECT(machine), "escc-alias", + sysbus_mmio_get_region(sysbus, 0), 0, 0x8); + memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE - 0x20, + &m->escc_alias); + /* SCSI */ object_initialize_child(OBJECT(machine), "esp", &m->esp, From patchwork Sun Oct 8 06:23:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC498E95A67 for ; Sun, 8 Oct 2023 06:26:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpND1-0008Ar-UC; Sun, 08 Oct 2023 02:24:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCz-00089p-P3 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:09 -0400 Received: from mout.kundenserver.de ([212.227.126.130]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCy-0007pn-60 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:09 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1MDQRy-1qhA0m1WNS-00ATk2; Sun, 08 Oct 2023 08:24:06 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 19/20] q800: add alias for MacOS toolbox ROM at 0x40000000 Date: Sun, 8 Oct 2023 08:23:48 +0200 Message-ID: <20231008062349.2733552-20-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:ebkkFYN3NtMW/4LIxJ7zKsqOeMgf+f+VxuV7K14xNgkWdrGeBgv orLxSP3vG4i3jtAGLxivjfbzmh98ekqLJGi+oHAqhHrkhX0FxtQtWBqmjaKZ0ARYSZHFE+l w7Z/+7U36qSXTJ+ELACb0SoZtWtI5O/AbIokp5KRWijfoe9Ggs9P+dPTJ293OvNsGNsqSXY sTRNEGrr6O7FojfTPlx3Q== UI-OutboundReport: notjunk:1;M01:P0:rnRbITuxG/Y=;YXfBgYgZA1nKzB7s/+iU6+j3N5Y BY0AMU8AsL7h5v98FDohBKoOo0NnVmvCUfS4+Oqljwggk/u2viQZUKIJr6jkdOE1xYP6qXOE3 cLNr7B3e4jDrbtyIPhsjHIohCMCJh919/QJRhBJnBxxNI+doU1r2uip1WIw36Y+8VOQ/BHX0Q ybBWQedtox6MW7q7wHSlrmfRf/fda5fcjR6LE3F0oxVUU8+EjKpSssxmEUSdUbQrLbf0w3fCf CzZtl+NhH1FzsfDL8mIl2wFq4EqId4AI/drYQLZtgJJlnjNoj0hMOQD2g/Yy7GDLVL2snsIa3 nm+svXp4aw1JzrEV7/be947pbZQ6cO/0KL5eLqCy/zrIY0k8JOWBhPrQ0qr8hsP/KHKW1EopB nLX1pP7l7tMY50KkQp3BCB9e+s+4Zkma8MuUF7lV/MJAx3EaLeKXt5ispA2OX6Yfdz9M0fEgK 6lrO7MUI97kGB1epTUHiZEH3STerMsxjipAgPcQAPXQn8kWqvRbBa97T9jLdaaGpJZAioPE8J wjzB4hAs9Ailo5qMW4Lms+A4gCKX0umG9rVZ5oSyQwvD/SD3HlGwh8FhbxxRd5DOmf+uUOq8u qQGBWjHgfMKHs47EAGIHF3S16emdn3Z8+2Vn/BwC9hO0tkPVeE5cDtarWEMtmYV+kWb5HXeHs IrW5jQLWdgEMFpreLPb+Jm9eeC9le9gABPPHGOhqwVuQ8C/KcCfdhimGT0zOkqYxcAXkeVTqt R6BMfqtMsbSZYQ+6SAFTvn8mtYhkFr9kr8Cj+ICvmafHx3YAnsNB2pD4vpjeyOeUk84imdHVQ kzBCaX4dVyHexzXAPNCxLwe2UwIw8NGYY1p5zt/9hgTfOSsrWU6lU4L3jzAlwFY+UzRLq72NS AvN3CW9qnDoZFNw== Received-SPF: none client-ip=212.227.126.130; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland According to the Apple Quadra 800 Developer Note document, the Quadra 800 ROM consists of 2 ROM code sections based at offsets 0x0 and 0x800000. A/UX attempts to access the toolbox ROM at the lower offset during startup, so provide a memory alias to allow the access to succeed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-20-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- include/hw/m68k/q800.h | 1 + hw/m68k/q800.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/include/hw/m68k/q800.h b/include/hw/m68k/q800.h index 348eaf4703d0..a9661f65f695 100644 --- a/include/hw/m68k/q800.h +++ b/include/hw/m68k/q800.h @@ -50,6 +50,7 @@ struct Q800MachineState { bool easc; M68kCPU cpu; MemoryRegion rom; + MemoryRegion rom_alias; GLUEState glue; MOS6522Q800VIA1State via1; MOS6522Q800VIA2State via2; diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 27a0b3c08a98..1d7cd5ff1c31 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -660,6 +660,11 @@ static void q800_machine_init(MachineState *machine) filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom); + memory_region_init_alias(&m->rom_alias, NULL, "m68k_mac.rom-alias", + &m->rom, 0, MACROM_SIZE); + memory_region_add_subregion(get_system_memory(), 0x40000000, + &m->rom_alias); + /* Load MacROM binary */ if (filename) { bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE); From patchwork Sun Oct 8 06:23:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Vivier X-Patchwork-Id: 13412579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B8C1FE95A80 for ; Sun, 8 Oct 2023 06:25:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qpND2-0008BE-Ry; Sun, 08 Oct 2023 02:24:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpND0-0008AN-W9 for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:11 -0400 Received: from mout.kundenserver.de ([212.227.126.187]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qpNCz-0007qC-AD for qemu-devel@nongnu.org; Sun, 08 Oct 2023 02:24:10 -0400 Received: from quad ([82.142.8.70]) by mrelayeu.kundenserver.de (mreue011 [212.227.15.167]) with ESMTPSA (Nemesis) id 1M2ep5-1qsOHQ0msx-004BHv; Sun, 08 Oct 2023 08:24:07 +0200 From: Laurent Vivier To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier Subject: [PULL 20/20] mac_via: extend timer calibration hack to work with A/UX Date: Sun, 8 Oct 2023 08:23:49 +0200 Message-ID: <20231008062349.2733552-21-laurent@vivier.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231008062349.2733552-1-laurent@vivier.eu> References: <20231008062349.2733552-1-laurent@vivier.eu> MIME-Version: 1.0 X-Provags-ID: V03:K1:muxX34OZPlG+tVM/KErZKWneQNQtd7qKzYRCqKlq+ZtowYKTrUz dv7BnJpnSZvnJocMVMLjK5fJQ40GsKQmyoXeM/hennNymblbO7kPjs6BQK8RsQNOmuVZy1n kfmUhdsgh2JE9iPnkQ8zzxReGCDsiJfNHr+0nY9iRHDaMp5Qxwk/Zux39Gn3HJoboKRtgyu YA9QXUyNQM7F/53fWELhg== UI-OutboundReport: notjunk:1;M01:P0:5uwZ6rjD1r0=;Vxq0cRCaJFKq24MqyCO1RHFgs3U 3kXbJ+slURz1pJEmw8XlfVx57j4/AEKF6SWmtRBF8mRVaIhCmwnRWkyCUXUbRxsoGZ8Q4fVHX 3uqWOBgRm2NGJsNQ9aEwfA53LpKbuYEJUggI6JeBr0zB8/fyUDR78OkrcexYuaeC1IvPVuBJJ GxAWFRXI1RLCQkFL/z2CW1lyq/XODfuQ2fWZfWUohPOt9S9xR+rB0lLw/MJDAbsQesF/Md+s2 vQRWryttvhCbCKBkSP1g8fgAxS5hWTuaaS2DETjO+8yrwW3Cy6F9zC0hYgem1lzRC0sYQQTu6 g6dKMW6lAc83iiPrPQC+S+ZVvL97w/YI4inFZvByiRrPfoVrcWEvcQogqghBYGQzXJgQlV9p/ xaT4sEUbllMiwup5g4vckK4u3lGzv518ufcMsYztxEEmVHAy7Bv5+hPrtkwwnYrMPA9DgsJa3 pNRTrhqWxWxD92eOHjwdHHnZMQGxXAGd1xUEefiiABqpMHlknzhK2bh96uUC+AbcvJ1WdL5cJ vQxWWG4MuAZm9Cglnkq37qvss57V59tVmNj0HQPjtIOcArkDhyLO7Z702hNOLSMDbpLNMaiat 9b/fwknrXapkEXWy3WDWAHWzv9MjWC2MmF7xDJ0ri+6lBFoSytZ0GCuUyinCqp9sI6yYWZdyy yns5eWUDYO7Mb6bj5fqUKPyCpxtL981TM84T+Ey2j1n7PMKvbpvdX24qZ2w/CGKbtg+8W+xm+ LrYEiHKjRhx0FBIvnJb2DbZwBviG0MEBvazxXGCFmOvUBDhRuPGxoO5huyQUhSo7wMkVG66jR Zl5o8tE3e2FUxTP4X81O3fEufrAdAB5aWzNPcb+WQKf0mZ4uo0WCDKm0PRpkUbPgpaXhrSBTe emaFz2ZcDyRfZEg== Received-SPF: none client-ip=212.227.126.187; envelope-from=laurent@vivier.eu; helo=mout.kundenserver.de X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.376, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Mark Cave-Ayland The A/UX timer calibration loop runs continuously until 2 consecutive iterations differ by at least 0x492 timer ticks. Modern hosts execute the timer calibration loop so fast that this situation never occurs causing a hang on boot. Use a similar method to Shoebill which is to randomly add 0x500 to the T2 counter value during calibration to enable it to eventually succeed. Signed-off-by: Mark Cave-Ayland Reviewed-by: Laurent Vivier Message-ID: <20231004083806.757242-21-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier --- hw/misc/mac_via.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 500ece5872bd..b6206ef73ca7 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -983,6 +983,44 @@ static void via1_timer_calibration_hack(MOS6522Q800VIA1State *v1s, int addr, /* Looks like there has been a reset? */ v1s->timer_hack_state = 1; } + + if (addr == VIA_REG_T2CL && val == 0xf0) { + /* VIA_REG_T2CL: low byte of counter (A/UX) */ + v1s->timer_hack_state = 5; + } + break; + case 5: + if (addr == VIA_REG_T2CH && val == 0x3c) { + /* + * VIA_REG_T2CH: high byte of counter (A/UX). We are now extremely + * likely to be in the A/UX timer calibration routine, so move to + * the next state where we enable the calibration hack. + */ + v1s->timer_hack_state = 6; + } else if ((addr == VIA_REG_IER && val == 0x20) || + addr == VIA_REG_T2CH) { + /* We're doing something else with the timer, not calibration */ + v1s->timer_hack_state = 0; + } + break; + case 6: + if ((addr == VIA_REG_IER && val == 0x20) || addr == VIA_REG_T2CH) { + /* End of A/UX timer calibration routine, or another write */ + v1s->timer_hack_state = 7; + } else { + v1s->timer_hack_state = 0; + } + break; + case 7: + /* + * This is the normal post-calibration timer state once both the + * MacOS toolbox and A/UX have been calibrated, until we see a write + * to VIA_REG_PCR to suggest a reset + */ + if (addr == VIA_REG_PCR && val == 0x22) { + /* Looks like there has been a reset? */ + v1s->timer_hack_state = 1; + } break; default: g_assert_not_reached(); @@ -998,6 +1036,7 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) MOS6522Q800VIA1State *s = MOS6522_Q800_VIA1(opaque); MOS6522State *ms = MOS6522(s); uint64_t ret; + int64_t now; addr = (addr >> 9) & 0xf; ret = mos6522_read(ms, addr, size); @@ -1007,6 +1046,23 @@ static uint64_t mos6522_q800_via1_read(void *opaque, hwaddr addr, unsigned size) /* Quadra 800 Id */ ret = (ret & ~VIA1A_CPUID_MASK) | VIA1A_CPUID_Q800; break; + case VIA_REG_T2CH: + if (s->timer_hack_state == 6) { + /* + * The A/UX timer calibration loop runs continuously until 2 + * consecutive iterations differ by at least 0x492 timer ticks. + * Modern hosts execute the timer calibration loop so fast that + * this situation never occurs causing a hang on boot. Use a + * similar method to Shoebill which is to randomly add 0x500 to + * the T2 counter value during calibration to enable it to + * eventually succeed. + */ + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + if (now & 1) { + ret += 0x5; + } + } + break; } return ret; }