From patchwork Mon Oct 9 13:22:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13413738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5468CE95A96 for ; Mon, 9 Oct 2023 13:22:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F15B10E112; Mon, 9 Oct 2023 13:22:10 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2202510E117 for ; Mon, 9 Oct 2023 13:22:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696857728; x=1728393728; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=/Qfdhh3ZvKynqsCf2Q2O8rJBCDAq4mvRIfexmX5lFck=; b=arozZTxXh4YP+63KlK8fyfs2fDoSkNqXLKp6ZwONalc70j6rSqQyVcyj 3iDiBOqc/kNDrELq8yojpWMD/JRMsDdWWpmwJ3tCHRwzky2OK0as4kcJf Q/hkbiUrWw151ZCYVPrR8kMydbZCse3BTrDeqO7fv7TZUNBrWe3OzjkJB aMkje2C6tYI5kUYBOq2qSUK/GD0Adr0WU9u0CHOcZIbN7EunQ0Ney3dBB oY/1/ox7Rs+rfEB9VebqJd096ZJCXfpwt5/pTM+6x8qO+22kq5IlMlTRh glicicxT90Csg803Lb+SeAviYc6hz6T/QYXsZCCr57kbqfCZIYtZD7TiP w==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="384014437" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="384014437" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 06:22:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="788162040" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="788162040" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.153]) by orsmga001.jf.intel.com with SMTP; 09 Oct 2023 06:22:04 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 09 Oct 2023 16:22:04 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2023 16:22:01 +0300 Message-ID: <20231009132204.15098-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/4] drm/i915/dsb: Allocate command buffer from local memory X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Using system memory for the DSB command buffer doesn't appear to work. On DG2 it seems like the hardware internally replaces the actual memory reads with zeroes, and so we end up executing a bunch of NOOPs instead of whatever commands we put in the buffer. To determine that I measured the time it takes to execute the instructions, and the results are always more or less consistent with executing a buffer full of NOOPs from local memory. Another theory I considered was some kind of cache coherency issue. Looks like i915_gem_object_pin_map_unlocked() will in fact give you a WB mapping for system memory on DGFX regardless of what mapping mode was requested (WC in case of the DSB code). But clflush did not change the behaviour at all, so that theory seems moot. On DG1 it looks like the hardware might actually be fetching data from system memory as the logs indicate that we just get underruns. But that is equally bad, so doens't look like we can really use system memory on DG1 either. Thus always allocate the DSB command buffer from local memory on discrete GPUs. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 3e32aa49b8eb..7410ba3126f9 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -5,6 +5,7 @@ */ #include "gem/i915_gem_internal.h" +#include "gem/i915_gem_lmem.h" #include "i915_drv.h" #include "i915_irq.h" @@ -461,7 +462,11 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, /* ~1 qword per instruction, full cachelines */ size = ALIGN(max_cmds * 8, CACHELINE_BYTES); - obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); + if (HAS_LMEM(i915)) + obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), + I915_BO_ALLOC_CONTIGUOUS); + else + obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); if (IS_ERR(obj)) goto out_put_rpm; From patchwork Mon Oct 9 13:22:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13413739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52586E95A97 for ; Mon, 9 Oct 2023 13:22:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E95CF10E0FB; Mon, 9 Oct 2023 13:22:13 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D57710E112 for ; Mon, 9 Oct 2023 13:22:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696857730; x=1728393730; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cTj+H8aCUxnzZLa4kJbMD6nzBOn+hVdJiDdQ+N1svY8=; b=Mh/RAtVe/Inq8RNAU+6e0YkPAHefcyHfyvVlQA9z8pCq0mpkpMfnL9sD Jq5HzjViGaUsPUrx21u+/tftsJCT5/v+KuSqPe6QPJ+Uwf6AcXZxkc23e sbR6T/RCRsDcZKeLBJQbRalA5wT+j1j5JuwW10TOWAlXta7gI7LnoVlaM DsqMY/E2jdPEx5kkPcPSwiVzuOeEOCx3mRYBebNA3itC9Q/1QJBH54zj6 6piFdbc6cUNPsh9gr2Ml/6uw95zsqRybU2KlZan9b3QPx4LbkNFISZpsg MaXVYlL/81XBjKAaPHkaXKLAJgs6FpAMpg3W0h98MOwsg+8M1eMcPRLFW g==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="384014456" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="384014456" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 06:22:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="788162056" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="788162056" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.153]) by orsmga001.jf.intel.com with SMTP; 09 Oct 2023 06:22:07 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 09 Oct 2023 16:22:07 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2023 16:22:02 +0300 Message-ID: <20231009132204.15098-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009132204.15098-1-ville.syrjala@linux.intel.com> References: <20231009132204.15098-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/4] drm/i915/dsb: Correct DSB command buffer cache coherency settings X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The display engine does not snoop the caches so shoukd to mark the DSB command buffer as I915_CACHE_NONE. i915_gem_object_create_internal() always gives us I915_CACHE_LLC on LLC platforms. And to make things 100% correct we should also clflush at the end, if necessary. Note that currently this is a non-issue as we always write the command buffer through a WC mapping, so a cache flush is not actually needed. But we might actually want to consider a WB mapping since we also end up reading from the command buffer (in the indexed reg write handling). Either that or we should do something else to avoid those reads (might actually be even more sensible on DGFX since we end up reading over PCIe). But we should measure the overhead first... Anyways, no real harm in adding the belts and suspenders here so that the code will work correctly regardless of how we map the buffer. If we do get a WC mapping (as we request) i915_gem_object_flush_map() will be a nop. Well, apart form a wmb() which may just flush the WC buffer a bit earlier than would otherwise happen (at the latest the mmio accesses would trigger the WC flush). Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dsb.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 7410ba3126f9..78b6fe24dcd8 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -316,6 +316,8 @@ void intel_dsb_finish(struct intel_dsb *dsb) DSB_FORCE_DEWAKE, 0); intel_dsb_align_tail(dsb); + + i915_gem_object_flush_map(dsb->vma->obj); } static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) @@ -462,13 +464,18 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, /* ~1 qword per instruction, full cachelines */ size = ALIGN(max_cmds * 8, CACHELINE_BYTES); - if (HAS_LMEM(i915)) + if (HAS_LMEM(i915)) { obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), I915_BO_ALLOC_CONTIGUOUS); - else + if (IS_ERR(obj)) + goto out_put_rpm; + } else { obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); - if (IS_ERR(obj)) - goto out_put_rpm; + if (IS_ERR(obj)) + goto out_put_rpm; + + i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); + } vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { From patchwork Mon Oct 9 13:22:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13413740 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1D89E95A96 for ; Mon, 9 Oct 2023 13:22:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5AA3B10E103; Mon, 9 Oct 2023 13:22:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 96F9A10E0FB for ; Mon, 9 Oct 2023 13:22:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696857733; x=1728393733; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E8hQTs0QFjk0o6aQxxfKH0gVIXIZiK2xO7RnagGGpYI=; b=Eo0VXj9sUsT4P9CF435ugC5nvR8Kyui6o+9VxbdWvg8Fnki/3ti8/MKt OE7jK43CLrVeL//vLgWHfCBvWNq7iUgHNOjm4bXDw+Y2S7ad0mrhyqpLc 7+o7GTrbD53LRXT+9vU9JoFvTYOQqly/lFL37txHt7MHHjIKX2k+hAUsg HRZ4wx5ZDqGrNxf3dvWdk4ghQ0QGxeXs8I4Huud0hf02mT2NpH3AUmvjm OYlVJw0DRGyLPXHcNt59XA7qVg0zrUkUzU9KS8kgn6Zoff//cWA9GPYLS jy6C4S5C2xoHfd13wiDfebnBGZR7JjZlK+k6P5NZ44Wec16RZj++meeck Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="384014477" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="384014477" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 06:22:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="788162069" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="788162069" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.153]) by orsmga001.jf.intel.com with SMTP; 09 Oct 2023 06:22:10 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 09 Oct 2023 16:22:10 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2023 16:22:03 +0300 Message-ID: <20231009132204.15098-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009132204.15098-1-ville.syrjala@linux.intel.com> References: <20231009132204.15098-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/4] drm/i915/dsb: Re-instate DSB for LUT updates X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä With all the known issues sorted out we can start to use DSB to load the LUTs. Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4f92fc31059f..40b04aa7d98c 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1895,9 +1895,6 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - /* FIXME DSB has issues loading LUTs, disable it for now */ - return; - if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state)) return; From patchwork Mon Oct 9 13:22:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13413741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 12270E95A99 for ; Mon, 9 Oct 2023 13:22:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BCFC10E0FD; Mon, 9 Oct 2023 13:22:18 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id B288810E113 for ; Mon, 9 Oct 2023 13:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696857736; x=1728393736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ly+KII+m6mQo2Skgb7irTFeRNoqNeoQeDFxR8UadKMU=; b=CrCOWX0T/k2gvRmdouNeBtjXQkNZvxzx7/BGNQ+t7vOTM17RNXi7xwzz axUYL0kZFldDuS4vIP61Hyi+V0Pm4044cirhMCKJPZKzFq9iJk775dSXR lHRZUmBTco4eFtp4mf22Zqe3nVOBhLIMXWX7jayvo9/CSiD7AkeRHr6+4 PUlJ5hb7HPl2hii2kB9YBcDu5RAeynrOqvoyWA5VcOI5yyci/X4NoIJRM AYo8sXpWImO9nv8m2KHrAGArCsZyJR7XPovEn/Y+8kgzLhnqAe8Kec8DW teq0q4XZB9vIdS1SrHt/+B+m6v9ezN13iw5x4JnlQWVnFYIDBTm/EvW3c g==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="384014488" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="384014488" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 06:22:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="788162079" X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="788162079" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.153]) by orsmga001.jf.intel.com with SMTP; 09 Oct 2023 06:22:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 09 Oct 2023 16:22:13 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Mon, 9 Oct 2023 16:22:04 +0300 Message-ID: <20231009132204.15098-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009132204.15098-1-ville.syrjala@linux.intel.com> References: <20231009132204.15098-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/4] drm/i915: Do state check for color management changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to validate LUT programming more thoroughly let's do a state check for all color management updates as well. Not sure we really want this outside CI. It is rather heavy and color management updates could become rather common with all the HDR/etc. stuff happening. Maybe we should have an extra knob for this that we could enable in CI? v2: Skip for initial_commit to avoid FDI dotclock sanity checks/etc. tripping up Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 303eb68fec11..9b99de3f6640 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -233,6 +233,8 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); if (!intel_crtc_needs_modeset(new_crtc_state) && + (!intel_crtc_needs_color_update(new_crtc_state) || + new_crtc_state->inherited) && !intel_crtc_needs_fastset(new_crtc_state)) return;