From patchwork Tue Oct 10 11:25:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13415221 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DD907CD80A9 for ; Tue, 10 Oct 2023 11:24:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7781810E1E0; Tue, 10 Oct 2023 11:24:42 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 01B4710E1DF for ; Tue, 10 Oct 2023 11:24:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696937081; x=1728473081; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7Vm8dum1QcXW8RhwpvDKNy6psIrv9Pr5JATFCxQlKcI=; b=QHoLSG8ZvOvkLsUq64sGAh/n8WSCj7MMK6L/7rHLSOkDIae6TcaoqTkE 39lhXAKWVyc8OULOL8bUejjL1waotMo1u/stUQRxCwSaYpYfBAL7lEEBp R22IsT2isGQLdTCb6VtDLmxfygM8CBxGWujGRrmMd19HqD57fIqHuaBgp BVb1HYEitG8SXNQCnNcbPxmRsfsvMhRzkg6PaP+sEMzVN2az/lqvozEIH dRiDQ3koPyplOcZMykL7Ub71unnFegKIXH7OmBbvAivzg8g9yZ080GW1e dP7KYUInsFJmhQumAGxF73q//MdZDguO1GSDgQK+PvylZT5vrBEenj5/s Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="387206345" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="387206345" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="757078023" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="757078023" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:38 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2023 14:25:01 +0300 Message-Id: <20231010112504.2156789-1-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231006133727.1822579-2-imre.deak@intel.com> References: <20231006133727.1822579-2-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 01/19] drm/i915/dp: Sanitize DPCD revision check in intel_dp_get_dsc_sink_cap() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Check only the eDP or the DP specific DPCD revision depending on the sink type. Pass the corresponding revision to the function, which allows getting the DSC caps of a branch device (in an MST topology, which has its own DPCD and so DPCD revision). While at it use DP_DPCD_REV_14 instead of open coding it and for clarity add a separate function to read out the DSC capability on eDP. v2: - Use DP_DPCD_REV_14 instead of open coding it. (Stan) - Check EDP_DCPD_REV/DPCD_REV in a clearer way. (Ville) Cc: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 63 +++++++++++++++---------- 1 file changed, 39 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0ef7cb8134b66..f92dff32a174a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3467,7 +3467,23 @@ bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; } -static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) +static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, + DP_DSC_RECEIVER_CAP_SIZE) < 0) { + drm_err(aux->drm_dev, + "Failed to read DPCD register 0x%x\n", + DP_DSC_SUPPORT); + return; + } + + drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", + DP_DSC_RECEIVER_CAP_SIZE, + dsc_dpcd); +} + +static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -3480,30 +3496,27 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) /* Clear fec_capable to avoid using stale values */ intel_dp->fec_capable = 0; - /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ - if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || - intel_dp->edp_dpcd[0] >= DP_EDP_14) { - if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, - intel_dp->dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)) < 0) - drm_err(&i915->drm, - "Failed to read DPCD register 0x%x\n", - DP_DSC_SUPPORT); + if (dpcd_rev < DP_DPCD_REV_14) + return; - drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", - (int)sizeof(intel_dp->dsc_dpcd), - intel_dp->dsc_dpcd); + intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); - /* FEC is supported only on DP 1.4 */ - if (!intel_dp_is_edp(intel_dp) && - drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, - &intel_dp->fec_capable) < 0) - drm_err(&i915->drm, - "Failed to read FEC DPCD register\n"); - - drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", - intel_dp->fec_capable); + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, + &intel_dp->fec_capable) < 0) { + drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); + return; } + + drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", + intel_dp->fec_capable); +} + +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp) +{ + if (edp_dpcd_rev < DP_EDP_14) + return; + + intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3674,7 +3687,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) - intel_dp_get_dsc_sink_cap(intel_dp); + intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], + intel_dp); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5384,7 +5398,8 @@ intel_dp_detect(struct drm_connector *connector, /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ if (HAS_DSC(dev_priv)) - intel_dp_get_dsc_sink_cap(intel_dp); + intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], + intel_dp); intel_dp_configure_mst(intel_dp); From patchwork Tue Oct 10 11:25:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13415222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18B3DCD80A9 for ; Tue, 10 Oct 2023 11:24:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CED6310E1DF; Tue, 10 Oct 2023 11:24:42 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2A81B10E1E3 for ; Tue, 10 Oct 2023 11:24:41 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="757078028" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:39 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2023 14:25:02 +0300 Message-Id: <20231010112504.2156789-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231006133727.1822579-3-imre.deak@intel.com> References: <20231006133727.1822579-3-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 02/19] drm/i915/dp: Store DSC DPCD capabilities in the connector X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In an MST topology the DSC capabilities are specific to each connector, retrieved either from the sink if it decompresses the stream, or from a branch device between the source and the sink in case this branch device does the decompression. Accordingly each connector needs to cache its own DSC DPCD and FEC capabilities, along with the AUX device through which the decompression can be enabled. This patch prepares for that by storing the capabilities and the DSC AUX device in the connector, for now these just matching the version stored in intel_dp. The follow-up patches will convert all users to look up these in the connector instead of intel_dp, after which the intel_dp copies are removed. v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in previous patch. Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 6 +++ drivers/gpu/drm/i915/display/intel_dp.c | 52 ++++++++++++++----- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8d8b2f8d37a99..d6600079bcf74 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -620,6 +620,12 @@ struct intel_connector { struct intel_dp *mst_port; + struct { + struct drm_dp_aux *dsc_decompression_aux; + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; + u8 fec_capability; + } dp; + /* Work struct to schedule a uevent on link train failure */ struct work_struct modeset_retry_work; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f92dff32a174a..5b2b0db5c24ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3483,7 +3483,8 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) +static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -3491,32 +3492,46 @@ static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) * Clear the cached register set to avoid using stale values * for the sinks that do not support DSC. */ - memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); /* Clear fec_capable to avoid using stale values */ - intel_dp->fec_capable = 0; + connector->dp.fec_capability = 0; if (dpcd_rev < DP_DPCD_REV_14) return; - intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); + intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, + connector->dp.dsc_dpcd); - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, - &intel_dp->fec_capable) < 0) { + if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, + &connector->dp.fec_capability) < 0) { drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); return; } drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", - intel_dp->fec_capable); + connector->dp.fec_capability); + + /* + * TODO: remove the following intel_dp copies once all users + * are converted to look up DSC DPCD/FEC capability via the + * connector. + */ + memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, + sizeof(intel_dp->dsc_dpcd)); + intel_dp->fec_capable = connector->dp.fec_capability; } -static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp) +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { if (edp_dpcd_rev < DP_EDP_14) return; - intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); + intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); + + memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, + sizeof(intel_dp->dsc_dpcd)); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3608,7 +3623,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) } static bool -intel_edp_init_dpcd(struct intel_dp *intel_dp) +intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); @@ -3688,7 +3703,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp); + intel_dp, + connector); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5358,7 +5374,9 @@ intel_dp_detect(struct drm_connector *connector, bool force) { struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + struct intel_connector *intel_connector = + to_intel_connector(connector); + struct intel_dp *intel_dp = intel_attached_dp(intel_connector); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; enum drm_connector_status status; @@ -5381,7 +5399,12 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); + /* + * TODO: Remove clearing the DPCD in intel_dp, once all + * user are converted to using the DPCD in connector. + */ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -5399,7 +5422,7 @@ intel_dp_detect(struct drm_connector *connector, /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ if (HAS_DSC(dev_priv)) intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - intel_dp); + intel_dp, intel_connector); intel_dp_configure_mst(intel_dp); @@ -5984,7 +6007,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, intel_hpd_enable_detection(encoder); /* Cache DPCD and EDID for edp. */ - has_dpcd = intel_edp_init_dpcd(intel_dp); + has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); if (!has_dpcd) { /* if this fails, presume the device is a ghost */ @@ -6158,6 +6181,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); intel_dp_aux_init(intel_dp); + intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; drm_dbg_kms(&dev_priv->drm, "Adding %s connector on [ENCODER:%d:%s]\n", From patchwork Tue Oct 10 11:25:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13415223 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 446D7CD80AA for ; Tue, 10 Oct 2023 11:24:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D7CB910E1E3; Tue, 10 Oct 2023 11:24:45 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6062910E1DF for ; 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a="757078040" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="757078040" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:41 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2023 14:25:03 +0300 Message-Id: <20231010112504.2156789-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231006133727.1822579-4-imre.deak@intel.com> References: <20231006133727.1822579-4-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 03/19] drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Similarly to eDP and SST-DP connectors read out the DSC capabilities for MST connectors as well. Atm these will match the root port's DSC caps and only used after a follow-up change enables the decompression for each stream separately (vs. the current way of enabling it only globally in the first branch device downstream of the root port). Reviewed-by: Stanislav Lisovskiy Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++++++++++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5b2b0db5c24ec..2b9af92fb8cf8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3483,8 +3483,8 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 2cf3681bac64a..bd9cb9680b4cd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -162,4 +162,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits); +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector); + #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 73e3977364632..e01f669d2c8a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1126,6 +1126,21 @@ static int intel_dp_mst_add_properties(struct intel_dp *intel_dp, return drm_connector_set_path_property(connector, pathprop); } +static void +intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, + struct intel_connector *connector) +{ + u8 dpcd_caps[DP_RECEIVER_CAP_SIZE]; + + if (!connector->dp.dsc_decompression_aux) + return; + + if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0) + return; + + intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], intel_dp, connector); +} + static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) @@ -1159,6 +1174,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); + /* + * TODO: set the AUX for the actual MST port decompressing the stream. + * At the moment the driver only supports enabling this globally in the + * first downstream MST branch, via intel_dp's (root port) AUX. + */ + intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; + intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector); + for_each_pipe(dev_priv, pipe) { struct drm_encoder *enc = &intel_dp->mst_encoders[pipe]->base.base; From patchwork Tue Oct 10 11:25:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13415224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0AB2CD80A8 for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="387206349" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="387206349" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10858"; a="757078045" X-IronPort-AV: E=Sophos;i="6.03,212,1694761200"; d="scan'208";a="757078045" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2023 04:24:42 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 10 Oct 2023 14:25:04 +0300 Message-Id: <20231010112504.2156789-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231006133727.1822579-20-imre.deak@intel.com> References: <20231006133727.1822579-20-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 19/19] drm/i915/dp: Remove unused DSC caps from intel_dp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The previous patches converted all users of the DSC DPCD caps to look these up from the connector, so remove the version stored in intel_dp. A follow-up patchset will read out the MST connector specific capabilities in intel_dp_add_mst_connector() -> intel_dp_mst_read_decompression_port_dsc_caps(). v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in the patchset. Reviewed-by: Stanislav Lisovskiy (v1) Signed-off-by: Imre Deak --- .../drm/i915/display/intel_display_types.h | 2 -- drivers/gpu/drm/i915/display/intel_dp.c | 28 +++---------------- drivers/gpu/drm/i915/display/intel_dp.h | 3 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 4 files changed, 6 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d6600079bcf74..65ea37fe8cff3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1725,10 +1725,8 @@ struct intel_dp { u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; - u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; - u8 fec_capable; u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; /* source rates */ int num_source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3ef9cc6e8c88c..b801df1f2ee8f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3490,10 +3490,9 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *i915 = to_i915(connector->base.dev); /* * Clear the cached register set to avoid using stale values @@ -3518,27 +3517,14 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", connector->dp.fec_capability); - - /* - * TODO: remove the following intel_dp copies once all users - * are converted to look up DSC DPCD/FEC capability via the - * connector. - */ - memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)); - intel_dp->fec_capable = connector->dp.fec_capability; } -static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) { if (edp_dpcd_rev < DP_EDP_14) return; intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); - - memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3710,7 +3696,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp, connector); /* @@ -5406,11 +5391,6 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); - /* - * TODO: Remove clearing the DPCD in intel_dp, once all - * user are converted to using the DPCD in connector. - */ - memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); if (intel_dp->is_mst) { @@ -5429,7 +5409,7 @@ intel_dp_detect(struct drm_connector *connector, /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ if (HAS_DSC(dev_priv)) intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - intel_dp, intel_connector); + intel_connector); intel_dp_configure_mst(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 51edb587e4d24..484aea215a251 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -163,7 +163,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits); -void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector); +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a065388c2199f..47f1efb50ea26 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1136,7 +1136,7 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0) return; - intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], intel_dp, connector); + intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector); } static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,