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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343E.mail.protection.outlook.com (10.167.18.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Tue, 10 Oct 2023 20:03:15 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 10 Oct 2023 15:03:14 -0500 From: Ben Cheatham To: , , , CC: , Subject: [PATCH v6 1/5] cxl/port: Add EINJ debugfs files and callback support Date: Tue, 10 Oct 2023 15:02:50 -0500 Message-ID: <20231010200254.764273-2-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> References: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|PH7PR12MB6465:EE_ X-MS-Office365-Filtering-Correlation-Id: 30d6e208-0629-4782-750a-08dbc9cbf0ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 20:03:15.6415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30d6e208-0629-4782-750a-08dbc9cbf0ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6465 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add creation of debugfs directories for ports and dports under /sys/kernel/debug/cxl when EINJ support is enabled. The dport directories will contain files for injecting CXL protocol errors. These files are only usable once the EINJ module has loaded and registered callback functions with the CXL core module, before that occurs (or if the EINJ module isn't loaded) the files will do nothing and return an ENODEV error. Signed-off-by: Ben Cheatham --- Documentation/ABI/testing/debugfs-cxl | 27 +++++++++ drivers/cxl/core/port.c | 84 +++++++++++++++++++++++++++ drivers/cxl/cxl.h | 10 ++++ 3 files changed, 121 insertions(+) diff --git a/Documentation/ABI/testing/debugfs-cxl b/Documentation/ABI/testing/debugfs-cxl index fe61d372e3fa..e87cb687cb1c 100644 --- a/Documentation/ABI/testing/debugfs-cxl +++ b/Documentation/ABI/testing/debugfs-cxl @@ -33,3 +33,30 @@ Description: device cannot clear poison from the address, -ENXIO is returned. The clear_poison attribute is only visible for devices supporting the capability. + +What: /sys/kernel/debug/cxl/portX/dportY/einj_types +Date: October, 2023 +KernelVersion: v6.7 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Prints the CXL protocol error types made available by + the platform in the format "0x ". + The can be written to einj_inject to inject + into dportY. This file is only visible if + CONFIG_ACPI_APEI_EINJ is enabled, and the EINJ module must + be able to reach one (or both) of the CXL_ACPI or CXL_PORT + modules to be functional. + +What: /sys/kernel/debug/cxl/portX/dportY/einj_inject +Date: October, 2023 +KernelVersion: v6.7 +Contact: linux-cxl@vger.kernel.org +Description: + (WO) Writing an integer to this file injects the corresponding + CXL protocol error into dportY (integer to type mapping is + available by reading from einj_types). If the dport was + enumerated in RCH mode, a CXL 1.1 error is injected, otherwise + a CXL 2.0 error is injected. This file is only visible if + CONFIG_ACPI_APEI_EINJ is enabled, and the EINJ module must + be able to reach one (or both) of the CXL_ACPI or CXL_PORT + modules to be functional. diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 7ca01a834e18..005c5cf4618e 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -725,6 +725,72 @@ static int cxl_dport_setup_regs(struct cxl_dport *dport, component_reg_phys); } +static struct cxl_einj_ops einj_ops; +void cxl_einj_set_ops_cbs(struct cxl_einj_ops *ops) +{ + if (!IS_REACHABLE(CONFIG_ACPI_APEI_EINJ) || !ops) + return; + + einj_ops = *ops; +} +EXPORT_SYMBOL_NS_GPL(cxl_einj_set_ops_cbs, CXL); + +static int cxl_einj_type_show(struct seq_file *f, void *data) +{ + if (!einj_ops.einj_type) + return -ENODEV; + + return einj_ops.einj_type(f, data); +} + +static int cxl_einj_inject(void *data, u64 type) +{ + struct cxl_dport *dport = data; + + if (!einj_ops.einj_inject) + return -ENODEV; + + return einj_ops.einj_inject(dport, type); +} +DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject, "%llx\n"); + +static int cxl_debugfs_create_dport_dir(struct dentry *port_dir, + struct cxl_dport *dport) +{ + struct dentry *dir; + char dir_name[32]; + + snprintf(dir_name, 31, "dport%d", dport->port_id); + dir = debugfs_create_dir(dir_name, port_dir); + if (IS_ERR(dir)) + return PTR_ERR(dir); + + debugfs_create_devm_seqfile(dport->dport_dev, "einj_types", dir, + cxl_einj_type_show); + + debugfs_create_file("einj_inject", 0x200, dir, dport, + &cxl_einj_inject_fops); + return 0; +} + +static struct dentry *cxl_debugfs_create_port_dir(struct cxl_port *port) +{ + const char *dir_name = dev_name(&port->dev); + struct dentry *dir; + + if (!IS_ENABLED(CONFIG_ACPI_APEI_EINJ)) + return ERR_PTR(-ENODEV); + + dir = cxl_debugfs_create_dir(dir_name); + if (IS_ERR(dir)) { + dev_dbg(&port->dev, "Failed to create port debugfs dir: %ld\n", + PTR_ERR(dir)); + return dir; + } + + return dir; +} + static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, @@ -788,6 +854,7 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct cxl_dport *parent_dport) { struct cxl_port *port, *parent_port; + struct dentry *dir; port = __devm_cxl_add_port(host, uport_dev, component_reg_phys, parent_dport); @@ -805,6 +872,10 @@ struct cxl_port *devm_cxl_add_port(struct device *host, parent_port ? " to " : "", parent_port ? dev_name(&parent_port->dev) : "", parent_port ? "" : " (root port)"); + + dir = cxl_debugfs_create_port_dir(port); + if (!IS_ERR(dir)) + port->debug_dir = dir; } return port; @@ -1045,6 +1116,7 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, resource_size_t component_reg_phys) { struct cxl_dport *dport; + int rc; dport = __devm_cxl_add_dport(port, dport_dev, port_id, component_reg_phys, CXL_RESOURCE_NONE); @@ -1054,6 +1126,11 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "dport added to %s\n", dev_name(&port->dev)); + + rc = cxl_debugfs_create_dport_dir(port->debug_dir, dport); + if (rc) + dev_dbg(dport_dev, + "Failed to create dport debugfs dir: %d\n", rc); } return dport; @@ -1074,6 +1151,7 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, resource_size_t rcrb) { struct cxl_dport *dport; + int rc; if (rcrb == CXL_RESOURCE_NONE) { dev_dbg(&port->dev, "failed to add RCH dport, missing RCRB\n"); @@ -1088,6 +1166,12 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "RCH dport added to %s\n", dev_name(&port->dev)); + + rc = cxl_debugfs_create_dport_dir(port->debug_dir, dport); + if (rc) + dev_dbg(dport_dev, + "Failed to create rch dport debugfs dir: %d\n", + rc); } return dport; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 76d92561af29..12025ed6b64e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -581,6 +581,7 @@ struct cxl_dax_region { * @depth: How deep this port is relative to the root. depth 0 is the root. * @cdat: Cached CDAT data * @cdat_available: Should a CDAT attribute be available in sysfs + * @debug_dir: dentry for port in cxl debugfs (optional) */ struct cxl_port { struct device dev; @@ -604,6 +605,7 @@ struct cxl_port { size_t length; } cdat; bool cdat_available; + struct dentry *debug_dir; }; static inline struct cxl_dport * @@ -795,6 +797,14 @@ bool is_cxl_nvdimm_bridge(struct device *dev); int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd); struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd); +struct cxl_einj_ops { + int (*einj_type)(struct seq_file *f, void *data); + int (*einj_inject)(struct cxl_dport *dport, u64 type); +}; + +void cxl_einj_set_ops_cbs(struct cxl_einj_ops *ops); + + #ifdef CONFIG_CXL_REGION bool is_cxl_pmem_region(struct device *dev); struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev); From patchwork Tue Oct 10 20:02:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13415964 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B8A92745F; Tue, 10 Oct 2023 20:03:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="gksTjaIG" Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2049.outbound.protection.outlook.com [40.107.94.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50747FB; 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Tue, 10 Oct 2023 20:03:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343C.mail.protection.outlook.com (10.167.18.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Tue, 10 Oct 2023 20:03:28 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 10 Oct 2023 15:03:26 -0500 From: Ben Cheatham To: , , , CC: , Subject: [PATCH v6 2/5] ACPI: Add CXL protocol error defines Date: Tue, 10 Oct 2023 15:02:51 -0500 Message-ID: <20231010200254.764273-3-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> References: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|DS7PR12MB5960:EE_ X-MS-Office365-Filtering-Correlation-Id: 97caa6a6-6a7d-42d9-0359-08dbc9cbf82e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 20:03:28.1585 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 97caa6a6-6a7d-42d9-0359-08dbc9cbf82e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5960 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add CXL protocol error defines to include/actbl1.h to be used in later commits. Signed-off-by: Ben Cheatham --- I made a pull request for adding this support into the acpica project that has already been merged [1], Feel free to discard this commit and use the acpica changes instead. [1]: Link: https://github.com/acpica/acpica/pull/884 include/acpi/actbl1.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 8d5572ad48cb..9741f1c40a4e 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1093,6 +1093,12 @@ enum acpi_einj_command_status { #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) #define ACPI_EINJ_PLATFORM_FATAL (1<<11) +#define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) +#define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) +#define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) +#define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) +#define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) +#define ACPI_EINJ_CXL_MEM_FATAL (1<<17) #define ACPI_EINJ_VENDOR_DEFINED (1<<31) /******************************************************************************* From patchwork Tue Oct 10 20:02:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13415965 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA33A2745F; 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Tue, 10 Oct 2023 15:03:39 -0500 From: Ben Cheatham To: , , , CC: , Subject: [PATCH v6 3/5] EINJ: Separate CXL errors from other EINJ errors Date: Tue, 10 Oct 2023 15:02:52 -0500 Message-ID: <20231010200254.764273-4-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> References: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|CY5PR12MB6083:EE_ X-MS-Office365-Filtering-Correlation-Id: 361e08da-2e64-454c-ae8b-08dbc9cbffaf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: I8DJsY1GkPks3JAxu243ekhKPjPi9bm57PQJuC/U1ktV0Hr7jJTkyJNA8m0IsNOoCoZ+tT2kgS5Pzn+L2zXI07/mHnmdURlQcSHJHxKD0CZjm1WSwL4VJgoYyuqxrK4puX9LYf2DDgBit4a2q8wJHRq1NPul668tXcub0Op/qpQHf9l2MqqWc/yKefhYwWbvth/DMilbSnLZqspi5Uq+FbPy2ibJvKBwLSANjbZixnsQfPkQwdEsDBQmlmXpHWu7v6wxFQxfsVukzUY5hSiqlVTGqMcsi+G1IQT4I1lgA6z+njkxGYfCXfrYkXxMidw6fxSR6JMvqTvH4hSDFS9ACoj6jFnLY5Ot14ZpwCB0jSAIXMraL/b/3yOcZFiybPs4MiMuEU3iERILsa2lcuJA4YFHDmQt0IFxsOo8jV+O9D39qCrnj3dxLrTCprHOE3Ekoi8EUcHC/bC5TcUcdwACjHl5oNhajGofM0JnEOHDm95KpjH5IYMNw4ByjLgjfYwexlqEhXLG+enyPrDYA8NlpE+RmXE+kY15T+qoEkXQBzORDvj/cm8f9Y51nibU8zcFIchnXwjvlSfT3WiwdEHNNoCwYFyndoqNFoa/tiKiTFuqkNjCpd7hsLn8R3Eb/hacfqpW2ASsAQSQRh8jbGEFRdQf8BHTx178fqNOUGHrBOYz2rKpJn9nCW37sLYuvSxyZSozPeTGmwO47qRsLF0ZzFhXLJWR2h1cglEKNdwj5oUxZ8iYGDz0cVEopIY+JolGgwsaDivaAN/JMP+XbWnrqg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(136003)(376002)(396003)(230922051799003)(64100799003)(451199024)(1800799009)(82310400011)(186009)(40470700004)(46966006)(36840700001)(6666004)(1076003)(40460700003)(356005)(40480700001)(70586007)(36756003)(82740400003)(81166007)(36860700001)(86362001)(426003)(7696005)(16526019)(336012)(2616005)(41300700001)(478600001)(8936002)(2906002)(47076005)(8676002)(4326008)(83380400001)(5660300002)(26005)(316002)(110136005)(70206006)(54906003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 20:03:40.7367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 361e08da-2e64-454c-ae8b-08dbc9cbffaf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6083 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Separate CXL error types from other EINJ error types and disallow them in the legacy EINJ interface under /sys/kernel/debug/apei/einj. Support for the CXL error types will be added under /sys/kernel/debug/cxl in the next commit. Signed-off-by: Ben Cheatham --- drivers/acpi/apei/einj.c | 56 +++++++++++++++++++++++++++++----------- 1 file changed, 41 insertions(+), 15 deletions(-) diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 013eb621dc92..330329ac2f1f 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -36,6 +36,12 @@ #define MEM_ERROR_MASK (ACPI_EINJ_MEMORY_CORRECTABLE | \ ACPI_EINJ_MEMORY_UNCORRECTABLE | \ ACPI_EINJ_MEMORY_FATAL) +#define CXL_ERROR_MASK (ACPI_EINJ_CXL_CACHE_CORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_UNCORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_FATAL | \ + ACPI_EINJ_CXL_MEM_CORRECTABLE | \ + ACPI_EINJ_CXL_MEM_UNCORRECTABLE | \ + ACPI_EINJ_CXL_MEM_FATAL) /* * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action. @@ -537,8 +543,11 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, if (type & ACPI5_VENDOR_BIT) { if (vendor_flags != SETWA_FLAGS_MEM) goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) + } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { goto inject; + } else if ((type & CXL_ERROR_MASK) && (flags & SETWA_FLAGS_MEM)) { + goto inject; + } /* * Disallow crazy address masks that give BIOS leeway to pick @@ -590,6 +599,9 @@ static const char * const einj_error_type_string[] = { "0x00000200\tPlatform Correctable\n", "0x00000400\tPlatform Uncorrectable non-fatal\n", "0x00000800\tPlatform Uncorrectable fatal\n", +}; + +static const char * const einj_cxl_error_type_string[] = { "0x00001000\tCXL.cache Protocol Correctable\n", "0x00002000\tCXL.cache Protocol Uncorrectable non-fatal\n", "0x00004000\tCXL.cache Protocol Uncorrectable fatal\n", @@ -615,29 +627,21 @@ static int available_error_type_show(struct seq_file *m, void *v) DEFINE_SHOW_ATTRIBUTE(available_error_type); -static int error_type_get(void *data, u64 *val) -{ - *val = error_type; - - return 0; -} - -static int error_type_set(void *data, u64 val) +static int validate_error_type(u64 type) { + u32 tval, vendor, available_error_type = 0; int rc; - u32 available_error_type = 0; - u32 tval, vendor; /* Only low 32 bits for error type are valid */ - if (val & GENMASK_ULL(63, 32)) + if (type & GENMASK_ULL(63, 32)) return -EINVAL; /* * Vendor defined types have 0x80000000 bit set, and * are not enumerated by ACPI_EINJ_GET_ERROR_TYPE */ - vendor = val & ACPI5_VENDOR_BIT; - tval = val & 0x7fffffff; + vendor = type & ACPI5_VENDOR_BIT; + tval = type & 0x7fffffff; /* Only one error type can be specified */ if (tval & (tval - 1)) @@ -646,9 +650,31 @@ static int error_type_set(void *data, u64 val) rc = einj_get_available_error_type(&available_error_type); if (rc) return rc; - if (!(val & available_error_type)) + if (!(type & available_error_type)) return -EINVAL; } + + return 0; +} + +static int error_type_get(void *data, u64 *val) +{ + *val = error_type; + + return 0; +} + +static int error_type_set(void *data, u64 val) +{ + int rc; + + if (val & CXL_ERROR_MASK && !(val & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(val); + if (rc) + return rc; + error_type = val; return 0; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS2PEPF0000343A.mail.protection.outlook.com (10.167.18.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Tue, 10 Oct 2023 20:03:53 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 10 Oct 2023 15:03:52 -0500 From: Ben Cheatham To: , , , CC: , Subject: [PATCH v6 4/5] cxl/port, EINJ: Add CXL EINJ callback functions Date: Tue, 10 Oct 2023 15:02:53 -0500 Message-ID: <20231010200254.764273-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> References: <20231010200254.764273-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|MW3PR12MB4348:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e5b8413-0bf3-45d6-e2bf-08dbc9cc075f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 20:03:53.6511 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e5b8413-0bf3-45d6-e2bf-08dbc9cc075f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4348 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add functions to the EINJ module to be used in the CXL module for CXL protocol error injection. The callbacks implement the einj_types and einj_inject files under /sys/kernel/debug/cxl/portX/dportY. These two files work in the same way as the available_error_types and error_inject files under /sys/kernel/debug/apei/einj, but only for CXL error types. If the dport is enumerated in RCH (CXL 1.1) mode, a CXL 1.1 error is injected into the dport; a CXL 2.0 error is injected otherwise. Signed-off-by: Ben Cheatham --- drivers/acpi/apei/Kconfig | 3 ++ drivers/acpi/apei/einj.c | 103 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 6b18f8bc7be3..100c27beb581 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -11,6 +11,9 @@ config ACPI_APEI select PSTORE select UEFI_CPER depends on HAVE_ACPI_APEI + imply CXL_BUS + imply CXL_ACPI + imply CXL_PORT help APEI allows to report errors (for example from the chipset) to the operating system. This improves NMI handling diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 330329ac2f1f..801b159b505f 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -21,9 +21,11 @@ #include #include #include +#include #include #include "apei-internal.h" +#include "../../cxl/cxl.h" #undef pr_fmt #define pr_fmt(fmt) "EINJ: " fmt @@ -627,6 +629,22 @@ static int available_error_type_show(struct seq_file *m, void *v) DEFINE_SHOW_ATTRIBUTE(available_error_type); +static int cxl_einj_available_error_type(struct seq_file *m, void *v) +{ + int rc; + u32 available_error_type = 0; + + rc = einj_get_available_error_type(&available_error_type); + if (rc) + return rc; + + for (int pos = 0; pos < ARRAY_SIZE(einj_cxl_error_type_string); pos++) + if (available_error_type & BIT(pos + 12)) + seq_puts(m, einj_cxl_error_type_string[pos]); + + return 0; +} + static int validate_error_type(u64 type) { u32 tval, vendor, available_error_type = 0; @@ -657,6 +675,69 @@ static int validate_error_type(u64 type) return 0; } +static int cxl_dport_get_sbdf(struct cxl_dport *dport, u64 *sbdf) +{ + struct pci_dev *pdev; + struct pci_bus *pbus; + struct pci_host_bridge *bridge; + u64 seg = 0, bus, devfn; + + if (!dev_is_pci(dport->dport_dev)) + return -EINVAL; + + pdev = to_pci_dev(dport->dport_dev); + pbus = pdev->bus; + bridge = pci_find_host_bridge(pbus); + + if (!bridge) + return -ENODEV; + + if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET) + seg = bridge->domain_nr << 24; + + bus = pbus->number << 16; + devfn = (PCI_DEVFN(PCI_SLOT(pdev->devfn),PCI_FUNC(pdev->devfn)) << 8); + *sbdf = seg | bus | devfn; + + return 0; +} + +static int cxl_einj_inject_error(struct cxl_dport *dport, u64 type) +{ + u64 param1 = 0, param2 = 0, param4 = 0; + u32 flags; + int rc; + + /* Only CXL error types can be specified */ + if (type & ~CXL_ERROR_MASK || (type & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(type); + if (rc) + return rc; + + /* + * If dport is in restricted mode, inject a CXL 1.1 error, + * otherwise inject a CXL 2.0 error + */ + if (dport->rch) { + if (dport->rcrb.base == CXL_RESOURCE_NONE) + return -EINVAL; + + param1 = (u64) dport->rcrb.base; + param2 = 0xfffffffffffff000; + flags = 0x2; + } else { + rc = cxl_dport_get_sbdf(dport, ¶m4); + if (rc) + return rc; + + flags = 0x4; + } + + return einj_error_inject(type, flags, param1, param2, 0, param4); +} + static int error_type_get(void *data, u64 *val) { *val = error_type; @@ -668,6 +749,7 @@ static int error_type_set(void *data, u64 val) { int rc; + /* CXL error types have to be injected from cxl debugfs */ if (val & CXL_ERROR_MASK && !(val & ACPI5_VENDOR_BIT)) return -EINVAL; @@ -714,6 +796,7 @@ static int __init einj_init(void) { int rc; acpi_status status; + struct cxl_einj_ops cxl_ops; struct apei_exec_context ctx; if (acpi_disabled) { @@ -793,6 +876,15 @@ static int __init einj_init(void) einj_debug_dir, &vendor_flags); } + if (IS_REACHABLE(CONFIG_CXL_ACPI) || IS_REACHABLE(CONFIG_CXL_PORT)) { + cxl_ops = (struct cxl_einj_ops) { + .einj_type = cxl_einj_available_error_type, + .einj_inject = cxl_einj_inject_error, + }; + + cxl_einj_set_ops_cbs(&cxl_ops); + } + pr_info("Error INJection is initialized.\n"); return 0; @@ -810,8 +902,18 @@ static int __init einj_init(void) static void __exit einj_exit(void) { + struct cxl_einj_ops cxl_ops; struct apei_exec_context ctx; + if (IS_REACHABLE(CONFIG_CXL_ACPI) || IS_REACHABLE(CONFIG_CXL_PORT)) { + cxl_ops = (struct cxl_einj_ops) { + .einj_type = NULL, + .einj_inject = NULL, + }; + + cxl_einj_set_ops_cbs(&cxl_ops); + } + if (einj_param) { acpi_size size = (acpi5) ? sizeof(struct set_error_type_with_address) : @@ -832,4 +934,5 @@ module_exit(einj_exit); MODULE_AUTHOR("Huang Ying"); MODULE_DESCRIPTION("APEI Error INJection support"); +MODULE_IMPORT_NS(CXL); MODULE_LICENSE("GPL"); From patchwork Tue Oct 10 20:02:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 13415967 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B54A329CEB; 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Signed-off-by: Ben Cheatham --- Documentation/firmware-guide/acpi/apei/einj.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index d6b61d22f525..83afe3bac793 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -181,6 +181,18 @@ You should see something like this in dmesg:: [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) +CXL error types are supported from ACPI 6.5 onwards. These error types +are not available in the legacy interface at /sys/kernel/debug/apei/einj, +but are instead at /sys/kernel/debug/cxl/portX/dportY. Inside the dportY +directory are two files, einj_types and einj_inject. These files work the +same as the available_error_type and error_inject files (read the error +types from einj_types and write the type to inject to einj_inject). + +To use these error types one of (or both) ``CONFIG_CXL_ACPI`` or +``CONFIG_CXL_PORT`` must be reachable by the EINJ module; if +``CONFIG_ACPI_APEI_EINJ`` == y/m, then at least one of ``CONFIG_CXL_ACPI`` +or ``CONFIG_CXL_PORT`` must also be set to y/m. + Special notes for injection into SGX enclaves: There may be a separate BIOS setup option to enable SGX injection.