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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:25 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 1/6] target/riscv: Propagate error from PMU setup Date: Fri, 13 Oct 2023 11:54:43 +0100 Message-ID: <20231013110111.34619-2-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 8 +++++++- target/riscv/pmu.c | 19 +++++++++---------- target/riscv/pmu.h | 3 ++- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2b94b6a6..c9d8fc12fe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1488,7 +1488,13 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) } if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { + riscv_pmu_init(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + if (cpu->cfg.ext_sscofpmf) { cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 36f6307d28..13801ccb78 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -434,22 +434,21 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) } -int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { - return -1; + uint8_t pmu_num = cpu->cfg.pmu_num; + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; } cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal); if (!cpu->pmu_event_ctr_map) { - /* PMU support can not be enabled */ - qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); - cpu->cfg.pmu_num = 0; - return -1; + error_setg(errp, "Unable to allocate PMU event hash table"); + return; } /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, num_counters); - - return 0; + cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 2bfb71ba87..88e0713296 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -17,13 +17,14 @@ */ #include "cpu.h" +#include "qapi/error.h" bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); void riscv_pmu_timer_cb(void *priv); -int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); From patchwork Fri Oct 13 10:54:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13420688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DDD7DC41513 for ; Fri, 13 Oct 2023 11:03:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrFvb-0000Lj-66; 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:27 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous Date: Fri, 13 Oct 2023 11:54:44 +0100 Message-ID: <20231013110111.34619-3-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 85a31dc420..4383805fa3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -182,7 +182,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - int pmu_num = riscv_cpu_cfg(env)->pmu_num; + RISCVCPU *cpu = env_archcpu(env); + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; int ctr_index; int base_csrno = CSR_MHPMCOUNTER3; @@ -191,7 +192,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; - if (!pmu_num || ctr_index >= pmu_num) { + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } From patchwork Fri Oct 13 10:54:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13420685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 51260C41513 for ; Fri, 13 Oct 2023 11:03:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrFvI-0000GU-Gi; Fri, 13 Oct 2023 07:01:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrFvF-0000GD-EN for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:37 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrFvA-00029G-BO for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:37 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-307d20548adso1789966f8f.0 for ; Fri, 13 Oct 2023 04:01:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697194890; x=1697799690; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+T1o7c6jOO1qih6JAKenu+zKIks7hzIqe4wyjYwbkaU=; b=J+S0x5REs25IiK8jvvQkMn2Kf8FPLK//BnpHSqA1Spqkm/Lo1XmPwFko4dJDRIzH2z r/vdXosmBJFi8XuDojgurQsZzDVSinsftOmqM+sg6mpZNAT+IYhiQ+SjiJj7uuntjEE1 wWWu224bQ/iixaRIWWQReSaUTI8258P+GcqxELZm+Ky+BIdTgtod1tDvpHKZhuZvetOB uoe+Mxs7n07Vm0cvuuHFQTQpUYpoMiTCB3vBjopgA9nnzG9oM105SGDkR1fpdh4R2odC fVKdEag2J40rqvfv7yAarbs6Rmjv3tM7oo8ZrP3b5u5jHJTMsYg2itYcID2nGUFfsh8J 58xQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697194890; x=1697799690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+T1o7c6jOO1qih6JAKenu+zKIks7hzIqe4wyjYwbkaU=; b=mlj7a6Dj40zIH/XoblWxr+DH3y2c8BHyzjx41vZagSECBQRkUuybXjbkOjRCyK0w/S kw2k/CwwZt/6rJd61GbCCCrzozYKA3bRDTLlBxI2rcGXX9NXkKvj78N46QduemE82MJX t5om2NSShvC9j6D8Sv68cygF2DM8PTp+gomeH+2nOyK/dwQjTPT0kV0tJnD3u2aXmFqX G/HVB8mRg5+T3bLznOQ/vAITZ4B3CUILZyqhu8CbKnWr/tTfs71Sesy1Pq222fAxcUYa ZbQlrjLxg5Gc7l15vnBhBQAFmepnsCgJGJYOpcPToLQGGXJZMeHjLdlUWdBl4Ykwc7Ua JV6A== X-Gm-Message-State: AOJu0YyN6mvZCAAQXijgJ0p2b3VKFSHO0D+GliA0LtQjDbcD2wH4ERjJ NnFZ3wnKgXlRbaddSVjNo9iwhAp6Zvnu3iF6hdI= X-Google-Smtp-Source: AGHT+IEXFZuM/MmF+AOp9KRP86//Dw437EDivy1ExFV195og1C+ZU8YvW9o2VcfhNISkkxn7kGQH8A== X-Received: by 2002:a5d:4fd2:0:b0:31f:f829:49aa with SMTP id h18-20020a5d4fd2000000b0031ff82949aamr20768512wrw.23.1697194890067; Fri, 13 Oct 2023 04:01:30 -0700 (PDT) Received: from rockhopper.. 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:29 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation Date: Fri, 13 Oct 2023 11:54:45 +0100 Message-ID: <20231013110111.34619-4-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 2 +- target/riscv/pmu.c | 6 +----- target/riscv/pmu.h | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5edc1d98d2..acdbaf9da5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) pmu_name = g_strdup_printf("/pmu"); qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); + riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); g_free(pmu_name); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 13801ccb78..7ddf4977b1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -34,13 +34,9 @@ * to provide the correct value as well. Heterogeneous PMU per hart is not * supported yet. Thus, number of counters are same across all harts. */ -void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] = {}; - uint32_t cmask; - - /* All the programmable counters can map to any event */ - cmask = MAKE_32BIT_MASK(3, num_ctrs); /* * The event encoding is specified in the SBI specification diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 88e0713296..505fc850d3 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -28,6 +28,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); From patchwork Fri Oct 13 10:54:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13420684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2EADDC41513 for ; Fri, 13 Oct 2023 11:03:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrFvY-0000Kg-UP; Fri, 13 Oct 2023 07:01:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrFvK-0000Hp-8p for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:43 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrFvC-0002A8-2n for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:42 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-32d80ae19f8so1599912f8f.2 for ; Fri, 13 Oct 2023 04:01:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697194892; x=1697799692; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T2umt+7OFn/qt6ZAkoTUCWSOYO+xVn32zwvp+RkPFAE=; b=aZa7vC8ewCs4NDGyjEeLKHR3zww9xWfJ5VHKaE6M74oken29wn52dPhHoL19VJP2lw rTx2W4qi2zZ0P0ozmzVYNobbLSpP5nvK2BkybzwX1Wbxj4d1jUS9yG2yl/f9VAZPUZWl B9nbVAUe7fk5HUVYBN1JxEue/iwTFI3vmWV0XggyHsF2++6s7K5iPyBpaCtL7Cu6UdH8 1Eu+obs3M9a+kfJCFv37g4xqRtnD2Xmngvmcmn/LuJT5hjOL6ZmYW+2iEYGkJCf32TbQ oPRoquL43448E4ALkWdkEnnhbJSIm2chJz/QKoltLZUWMsmecxtpHaQ9mEf36szY6/1i gzsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697194892; x=1697799692; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T2umt+7OFn/qt6ZAkoTUCWSOYO+xVn32zwvp+RkPFAE=; b=dkWskC8K2Ot1P/5CvWghYVa/F3w8Bfy7YhQd2fehbCbs09PiRpLNNAT2JuqXAcY1W4 NssyIXkxg3WpC7FcOZ865MYzIbulXeNrubgxX+OG2tGwL+VHUYniPEB3vybXTCr4oy8h KeQTy/cFC4lvUTvkobJ34C6erKygXIhhs4NAGV1a2cRw2aiATIWi0aeFIO+ys5Rgt7mc pZJ0NQc4OOj9PkzMUmGg4tz7UQI2j2aHQFqiG5XBkC/6F8WKJlMiED5x+dDpC3SAx8sz T+7VSgn5aI+pKCeYwYrX/T0eN1BzwE5QoZ9WAaocUta3/55PG0ULITrY+1B50VCFwRSs l/Nw== X-Gm-Message-State: AOJu0YyeacQa1+f9uVxT1mrlUC73ygoFdbTQ4RGBjaE11csaxP7A1wNa iJ98KEJeuFjaxtiDRRhziwlAx+LJthQevd8rWCM= X-Google-Smtp-Source: AGHT+IGu/GCjpH3q4/HtjWgoRbijO64osdY04FTQNZO+QFmYRU4SsE5AwbHtlJ4lDtplQPvy3caZDA== X-Received: by 2002:a5d:4d12:0:b0:316:efb9:101d with SMTP id z18-20020a5d4d12000000b00316efb9101dmr23251797wrt.25.1697194891458; Fri, 13 Oct 2023 04:01:31 -0700 (PDT) Received: from rockhopper.. (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:31 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num" Date: Fri, 13 Oct 2023 11:54:46 +0100 Message-ID: <20231013110111.34619-5-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters. Generate a warning if the old property changed from the default but still go ahead and use it to generate the mask if the user has changed it from the default Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 5 +++-- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 20 ++++++++++++++++---- 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c9d8fc12fe..420673b491 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1487,7 +1487,7 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) riscv_timer_init(cpu); } - if (cpu->cfg.pmu_num) { + if (cpu->cfg.pmu_mask) { riscv_pmu_init(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -1812,7 +1812,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) static Property riscv_cpu_extensions[] = { /* Defaults for standard extensions */ - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), /* Deprecated */ + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..d273487040 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -123,7 +123,8 @@ struct RISCVCPUConfig { bool ext_xtheadsync; bool ext_XVentanaCondOps; - uint8_t pmu_num; + uint8_t pmu_num; /* Deprecated */ + uint32_t pmu_mask; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..9f6e3f7a6d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.pmu_num; + return (cpu->cfg.pmu_mask > 0); } static const VMStateDescription vmstate_pmu_ctr_state = { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..9253e5f17a 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" @@ -184,7 +185,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) CPURISCVState *env = &cpu->env; gpointer value; - if (!cpu->cfg.pmu_num) { + if (!cpu->cfg.pmu_mask) { return 0; } value = g_hash_table_lookup(cpu->pmu_event_ctr_map, @@ -434,7 +435,13 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { uint8_t pmu_num = cpu->cfg.pmu_num; - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); + return; + } + + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3) || + (pmu_num > RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } @@ -445,6 +452,11 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } - /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); + /* Check if user set it by comparing against default */ + if (pmu_num != 16) { + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); + cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num); + } + + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; } From patchwork Fri Oct 13 10:54:47 2023 Content-Type: text/plain; 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:34 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , libvir-list@redhat.com (reviewer:Incompatible changes) Subject: [PATCH v3 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation Date: Fri, 13 Oct 2023 11:54:47 +0100 Message-ID: <20231013110111.34619-6-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei --- docs/about/deprecated.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 8b136320e2..37f3414ef8 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -361,6 +361,16 @@ Specifying the iSCSI password in plain text on the command line using the used instead, to refer to a ``--object secret...`` instance that provides a password via a file, or encrypted. +CPU device properties +''''''''''''''''''''' + +``pmu-num=x`` on RISC-V CPUs (since 8.2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to support more flexible counter configurations this has been +replaced by a ``pmu-mask`` property + + Backwards compatibility ----------------------- From patchwork Fri Oct 13 10:54:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13420687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 63E14CDB483 for ; Fri, 13 Oct 2023 11:03:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrFva-0000LT-9y; Fri, 13 Oct 2023 07:01:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrFvM-0000I8-1k for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:45 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrFvH-0002Hl-OK for qemu-devel@nongnu.org; Fri, 13 Oct 2023 07:01:43 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-3248ac76acbso1665789f8f.1 for ; Fri, 13 Oct 2023 04:01:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697194897; x=1697799697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iINLba3Z9IRPyClB9itO+7onNYKObdnht5URrf2joic=; b=xkEl22lYMJW86pqpLEiYF8xRSkNDuuzi5u13mON/MPU5R1AHdu9Y2sYfP2u+b5LsPr YNnC89fH4rPbesRw9YBJ45UQaOoLMI4jz2GZu0A5CSJA/MBiR3JqYeWHYAPi3PZdUXVV drAgMQJy2y04eT8dtrPZQ9VEuZ0KsrisJpBIZ5ZUuGx9VA+16WjX2Rnwaik3YnvFiyWB MdKlO7cTKbBfcgzA5lR2xhM+EgKLV63Es9G8JeuPi50SFAIWqSbaNwAO4h0aUmMH69zL tojMvUEwcCgD6jrfxz/26Rh3CNMuXdA8DWRVsIltWyvIzH9r5IeHmIIxhPQ4EtYZ+9kE c++g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697194897; x=1697799697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iINLba3Z9IRPyClB9itO+7onNYKObdnht5URrf2joic=; b=mgo0MpPRauVeIjM5u/IXzBMUk2ZWA3ULgMHazliWDfpWYYpyb4rzbQvdzgQY2+WWzo PqFHYydizeYeZz3MiSbzegUS14IrO+rapfbZanrNOcUwHWbK7QKt2hYff6gokujd4EQ7 z3XJpP7HhLgLvFDeICxv17qmq0HkQ4pe1KciK/lgdUGsEJpUc0ZpaI4mF0jnCGV5I5h5 iJtzFYi18c7SvQDWZ/KjyVTF9LFg8qhuxdo5xE9lZPon479dRX72xzTUJ51KM8AvNTtF z3Os1fntM2ojm8GCG45Z0uYU21BTwars7rUZRF5B6XWbnZQEO/ifwEL8+awUZz5g87Hl 3MGg== X-Gm-Message-State: AOJu0Yza35+8MJdLbarQP/BOVHxA7w497RWptInRS7Adx590UFSccZSg sGGdLaYtBVZjcujo+ewJ7mbQnXyoaojVmcnR7QQ= X-Google-Smtp-Source: AGHT+IFcI+6OY+haosN8G/SBb++UYo3pMErPptRA0Ak8u46NlvDD3LePkXqeiHLxn72w3kvlzgfobg== X-Received: by 2002:a05:6000:cb:b0:321:7050:6fb6 with SMTP id q11-20020a05600000cb00b0032170506fb6mr21299814wrx.67.1697194897383; Fri, 13 Oct 2023 04:01:37 -0700 (PDT) Received: from rockhopper.. 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:37 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro Date: Fri, 13 Oct 2023 11:54:48 +0100 Message-ID: <20231013110111.34619-7-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 9253e5f17a..052d5b1164 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -25,8 +25,6 @@ #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in @@ -455,7 +453,7 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) /* Check if user set it by comparing against default */ if (pmu_num != 16) { warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); - cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num); + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); } cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;