From patchwork Mon Oct 16 10:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13423021 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6AD2CDB465 for ; Mon, 16 Oct 2023 10:54:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232416AbjJPKyD (ORCPT ); Mon, 16 Oct 2023 06:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232206AbjJPKyC (ORCPT ); Mon, 16 Oct 2023 06:54:02 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34591D9 for ; Mon, 16 Oct 2023 03:54:00 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9c53e8b7cf4so27094866b.1 for ; Mon, 16 Oct 2023 03:54:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1697453638; x=1698058438; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5+MJaAV/gwtH2nOns6YwndFAXtL/h0w6eYvJcO7ucAs=; b=GDbdecguN2TW1xsnb++hpsQgldP19bMQVt3sa9qnAfBtUxQ8TXuJuCguS4Cx/Mtl+1 NY8/rsCLaocthtfgeTf+gvg8P6GS0TlBGqeTQh6slJaT3/+8tlO8gbxzhFi5EXcXgO0b Q5PZ2sS8ATcUVANlgf9LAHQAG+eVJrM+0MAziTHBN+OJC14jCbpGMZuPSYWIggLsiEbB Od1OWQOwdE59EBwLL6dlwKv89DeWTnb7Dv4RaB0RisfsQDlkZCg4xSRitiHyWhw45mlN 5RrcTeaMKD5ZHIC7aqOthT61/Ie0pMEEM2Goxk+UYtvb+PR6s/y7CVEq7WpKXWidKmfD BkjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697453638; x=1698058438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5+MJaAV/gwtH2nOns6YwndFAXtL/h0w6eYvJcO7ucAs=; b=QtrjQcs4x663cXqOnFz5EQvnSCuEDWe14wuhsXHzrR2M7zp4jtuRkSQwwzTLFopsJ/ MsrVqFElaIo1j5TVa9051crPNVwevalNNwDeGqjHpe851yQVwRamd+BzdAeGZaLRvOcn eTngi8GVvLU0GOwAsE4s4z8NSbnEkQlQ0eD3c1O0NcZHcAndq+G9+70t9fyQlApPcH2+ bsgowk4sWt61F9C/QYn6oUvnlIkiu7neObYXQB1eJ5a80Pjo704JVpsOZi3/iDWfjW0Y LwYmdI6pourZWrjprpsELClE/1puDJP/K7z2lQqvsPNlmtfvSV6ASvDoVs1iznaJBAN8 uXZQ== X-Gm-Message-State: AOJu0YwT8+qyMalS7mUZHxwNKW/+JBPQXZcCa5FECFbAjJOddFXwbk8s 7aFslNt2CBi7p31WyeRQiYKoFwRZgK3iXAmPSnc= X-Google-Smtp-Source: AGHT+IG/M+sOmZoqyWo8LSLRIrJctdwi0GeDZl7HCHvP81bWrj6rK4oi5DexO1+wGbnMhcPwlKhZLw== X-Received: by 2002:a17:907:9486:b0:9be:f6c0:7d73 with SMTP id dm6-20020a170907948600b009bef6c07d73mr4528867ejc.74.1697453638630; Mon, 16 Oct 2023 03:53:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.103]) by smtp.gmail.com with ESMTPSA id v2-20020a17090651c200b009a5f7fb51dcsm3818126ejk.42.2023.10.16.03.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 03:53:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 1/2] arm64: dts: renesas: rzg3s-smarc-som: Enable SDHI2 Date: Mon, 16 Oct 2023 13:53:43 +0300 Message-Id: <20231016105344.294096-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231016105344.294096-1-claudiu.beznea.uj@bp.renesas.com> References: <20231016105344.294096-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Add SDHI2 to RZ/G3S Smarc SoM. SDHI2 pins are multiplexed with SCIF1, SSI0, IRQ0, IRQ1. The selection b/w SDHI2 and SCIF1, SSI3, IRQ0, IRQ1 is done with a switch button. To be able to select b/w these a compilation flag has been added (SW_SD2_EN) at the moment being instantiated to select SDHI2. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - remove pinctrl-1 and vqmmc regulator as UHS is not supported by SDHI2 - fixed typos in commit message and code .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index a199de8f8b02..01a4a9da7afc 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -13,14 +13,21 @@ * @SW_SD0_DEV_SEL: * 0 - SD0 is connected to eMMC * 1 - SD0 is connected to uSD0 card + * @SW_SD2_EN: + * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + * 1 - SD2 is connected to SoC */ #define SW_SD0_DEV_SEL 1 +#define SW_SD2_EN 1 / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { mmc0 = &sdhi0; +#if SW_SD2_EN + mmc2 = &sdhi2; +#endif }; chosen { @@ -63,6 +70,15 @@ reg_1p8v: regulator1 { regulator-always-on; }; #endif + + vcc_sdhi2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &extal_clk { @@ -100,6 +116,17 @@ &sdhi0 { }; #endif +#if SW_SD2_EN +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sdhi2>; + bus-width = <4>; + max-frequency = <50000000>; + status = "okay"; +}; +#endif + &pinctrl { sdhi0_pins: sd0 { data { @@ -139,4 +166,26 @@ sdhi0_emmc_pins: sd0-emmc { "SD0_CLK", "SD0_CMD", "SD0_RST#"; power-source = <1800>; }; + + sdhi2_pins: sd2 { + data { + pins = "P11_2", "P11_3", "P12_0", "P12_1"; + input-enable; + }; + + ctrl { + pins = "P11_1"; + input-enable; + }; + + mux { + pinmux = , /* SD2_CLK */ + , /* SD2_CMD */ + , /* SD2_DATA0 */ + , /* SD2_DATA1 */ + , /* SD2_DATA2 */ + , /* SD2_DATA3 */ + ; /* SD2_CD# */ + }; + }; }; From patchwork Mon Oct 16 10:53:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13423022 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D2BC46CA1 for ; Mon, 16 Oct 2023 10:54:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232828AbjJPKyE (ORCPT ); Mon, 16 Oct 2023 06:54:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232495AbjJPKyD (ORCPT ); Mon, 16 Oct 2023 06:54:03 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C29683 for ; Mon, 16 Oct 2023 03:54:01 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9be02fcf268so376637666b.3 for ; Mon, 16 Oct 2023 03:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1697453640; x=1698058440; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LwYnEVWbvuqB6MXp+cQtdDUOxrrKVsKddWrqllszA1o=; b=eXl5/yyCvdQlK5UouywXTfhnTiT9KYVW4ya6G5yPlrHgx25QXsj2Le9bZ4+Vs0H/oA lWbrDE6ABNdvuSFOaPVTQENoP0eWFBRoQlXSH+jkAshUZ7qPP0+Zqd/DidjJu0+Hx0dU CzLc6VGXzZ81gm8y9V+7XtsB5dcGDOPc9bPkc7rsZpCJ4CGjzEzabpva5wfms87Fl71B 98WTdGEBZNcaaWpSILRlgB8l90VB/q8w7o13tnbU4/kUC2YzNuwnF3OsmFhPdqUaqazb 8Wku2PGkoJ8mClF/H+R4V4rbwTqPZLJZhkoEvjnkKn8KCIHpnXJxETLmDuWm8z1W6C6R KdrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697453640; x=1698058440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LwYnEVWbvuqB6MXp+cQtdDUOxrrKVsKddWrqllszA1o=; b=MSIGs96mNJTMiaKIFe+YGkDn5vv5eoa/9g7h1uh1Hjptk3NNyqXgx4bJynXE0jhyjE Y9O4LvdT5b/XsH/60xSViifASdKlJ+Ja2cDjxT2D1P/fmqlZXXZHqiBCoV1m8qnS8U6J 9JV1ajPzJYuWSuBpdGH/Fyz4vZnA9iYKDTb3wYqRQj1RKc0znYTv+JP4XZOReJH5zzGv 0Jmlpb+k3Yuc3x3MFp7faCPjoBPsP3c8Hco0aBtRmk0NwJbmfyDOhZGHLwCzfY6Ack3W oEKGbi2L4RS7zevJy4F5K1BizCHXdcYQ/AowvaeTp8vq1hav92NFWJ72UILxZY+d08b1 W9Vg== X-Gm-Message-State: AOJu0Yy9SG4Sw8ZnAYiJFoNZGHq5sYQCSZ6aDZN/wWKhbcT60I49+ksp miaSiB3tTr8QJMVylxFaKcl33w== X-Google-Smtp-Source: AGHT+IEjIvVc0QCAzuso0fzKKPnIm8JNogGoTmRKjHnxysV8FfESq1C5vOhwCdZDlYc9Ut+uexlXZw== X-Received: by 2002:a17:907:7711:b0:9ae:82b4:e309 with SMTP id kw17-20020a170907771100b009ae82b4e309mr29378148ejc.0.1697453639868; Mon, 16 Oct 2023 03:53:59 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.103]) by smtp.gmail.com with ESMTPSA id v2-20020a17090651c200b009a5f7fb51dcsm3818126ejk.42.2023.10.16.03.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 03:53:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, magnus.damm@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 2/2] arm64: dts: renesas: rzg3s-smarc: Enable SDHI1 Date: Mon, 16 Oct 2023 13:53:44 +0300 Message-Id: <20231016105344.294096-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231016105344.294096-1-claudiu.beznea.uj@bp.renesas.com> References: <20231016105344.294096-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org From: Claudiu Beznea Add SDHI1 to RZ/G3S Smarc Carrier-II board. This is connected to a uSD interface. Although Vccq doesn't cross the boundary of SoM it has been added to RZ/G3S Smarc Carrier-II dtsi to have all the bits related to SDHI1 in a single place. At the moment SoM is used only with RZ/G3S Smarc Carrier-II board. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven --- Changes in v2: - change regulators' names to regulator-vcc-sdhi1 and regulator-vccq-sdhi1 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 65 ++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index e7073a09ed2e..214520137230 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,26 @@ / { aliases { serial0 = &scif0; + mmc1 = &sdhi1; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(4, 2) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; }; }; @@ -19,6 +39,38 @@ scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ }; + + sdhi1_pins: sd1 { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1-uhs { + data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD1_CD */ + }; + }; }; &scif0 { @@ -26,3 +78,16 @@ &scif0 { pinctrl-0 = <&scif0_pins>; status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <125000000>; + status = "okay"; +};