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Mon, 16 Oct 2023 10:36:18 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id lv15-20020a056871318f00b001e0fd4c9b9asm2092936oac.6.2023.10.16.10.36.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 10:36:18 -0700 (PDT) From: Charlie Jenkins Date: Mon, 16 Oct 2023 10:36:09 -0700 Subject: [PATCH v3 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Message-Id: <20231016-module_relocations-v3-1-a667fd6071e9@rivosinc.com> References: <20231016-module_relocations-v3-0-a667fd6071e9@rivosinc.com> In-Reply-To: <20231016-module_relocations-v3-0-a667fd6071e9@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 8CB5A20012 X-Rspam-User: X-Stat-Signature: zaasg8fc8wo6ypn147tgpx8i6e7mt466 X-Rspamd-Server: rspam01 X-HE-Tag: 1697477779-573243 X-HE-Meta: U2FsdGVkX18r5I1AU2xKf08w0SkrLCf0m2aKfNHS3W1TR4/aGZM3Lk//HCBJj88ArPmTqDYwx0MkSY7tmZW7RZXnS4W+w+5B5d5/+eU/zQ2/EOFvaFMzgm4lWVuORZnBSPvgUbNWoR7d/s8aGemq52e0Utdtitqv6ipH+yYPDFrxJQ87x1bKa+DS2AuwcdqIwbq4vhfRQMFuhX6yPvpLc7pbFBGkpA5lrwe0T+f/FuIUg5C56BMqBG+yMGctl7oExFyxF8fAzCv4lHR3eZKn+9Y9Qq2+yFhCspsQ6jOc2ma9S+v8mQZ8d7BrT8llxVFkdgaiyIZU+mk2mHIvr8PR2vcGE6np/ee1caHFRk58suBjUi/gFsELKdhf+HIWHr4pTQ/xnr3uqTnErz+7zAaVc9hAxtcPZjgotrfnRo0mpsm4Goh5kGXJtgtTFzWhX/VYWzu3b4bnlJIfrkHvMsBHnEPJfVARWLUyqvNaBnmU24MPGHWA24RgsGHk37D9UKmccOUYJW/0pb0bacmW6SM0Utx3hSp6+1NEhT40JF9iajDJt7Cx6ej4wYBsh8dowWyRJQFNSZ+TCwMO1Li3zliBkwJqxr7igvTQk5EWzpZP/TJx0WkrnXooIFJHVKqfi38j0Rt3sOo/Zg/C9TQGzCrGBilmOfLC1dP2K7MbcAA5A3jWF+8QVtfu0Wq8Wrp8kxTyQEqvNfb2J1RbBHiZ8DUbp8xTeLa9wkTutoguC5AYpADM2iNCPVxvFknYm3bMcJgw0OC2Lp2SVRZ8D19H2MdUUAhizVKQEbd0e/ho8B8O06gR5IgyB6gc/kCw4SOIXIJQXvvaZ7JQXrYOqjhKOf2oQ9OeHtzDVH/+O04mSQfayVzTdU+a1WNfPos3vEJE8V1hDnbHdJbUqKaiNRh0WWF2XSCBJ7acMZvclme4aFlomwGVNI1fW5CUg3jXAwtMVVUd3fWAAursqvp7uX1PHwI lGSIS9Ju I3U5Ex8Ft1fQdl52QWRz0oRs/vYs3o40Zjo4EngtR9qdX8gkRzmEJKlCM4DWXe2Rj5kzoW5oclKGea1sVnmYr3e8Xr7Bmw1EQbu4FeuUsRIneR09pyE0RBzwPbikwtsJ/uLq9fv3ZTwl/El1JGEGAmvT2uZ1zpIzhx+vI0t5pyE8JVPA0yW0SVaY/pH4bk6UXIUL5gSvEMuRo2z7kD7yMY23vPUl5k3v8jhIrMWire8TtB7DPix4K26Kz3Zx2Qy81FTm7+rMh2aOhabSinN83yqyw+BSxja+VETO2pYdWDoNXeLpuHGd9MTKOp7GzFqaQfn6/1acww0TRTrIi/rTTh3v1NlaBsUfPOllh2iV8s/PbRo4= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000046, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 6 +- arch/riscv/kernel/module.c | 207 +++++++++++++++++++++++++++++++++----- 2 files changed, 187 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..a9307a1c9ceb 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 +#define R_RISCV_RVC_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +94,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..73f47de538d2 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -268,6 +269,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location += (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +296,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +323,149 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) = { - [R_RISCV_32] = apply_r_riscv_32_rela, - [R_RISCV_64] = apply_r_riscv_64_rela, - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, - [R_RISCV_JAL] = apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] = apply_r_riscv_call_rela, - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location = (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + if (v >= 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC = %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *location = v; + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) = { + [R_RISCV_32] = apply_r_riscv_32_rela, + [R_RISCV_64] = apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, + [R_RISCV_COPY] = dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, + [R_RISCV_JAL] = apply_r_riscv_jal_rela, + [R_RISCV_CALL] = apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, + [R_RISCV_TLS_GD_HI20] = tls_not_supported, + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] = tls_not_supported, + [R_RISCV_TPREL_LO12_I] = tls_not_supported, + [R_RISCV_TPREL_LO12_S] = tls_not_supported, + [R_RISCV_TPREL_ADD] = tls_not_supported, + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, + /* 46-50 reserved for future standard use */ + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, + [R_RISCV_SET6] = apply_r_riscv_set6_rela, + [R_RISCV_SET8] = apply_r_riscv_set8_rela, + [R_RISCV_SET16] = apply_r_riscv_set16_rela, + [R_RISCV_SET32] = apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] = apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] = apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -348,6 +479,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int i, type; Elf_Addr v; int res; + bool uleb128_set_exists = false; + u32 *uleb128_set_loc; + unsigned long uleb128_set_sym_val; + pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); @@ -425,6 +560,28 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, me->name); return -EINVAL; } + } else if (type == R_RISCV_SET_ULEB128) { + if (uleb128_set_exists) { + pr_err("%s: riscv psABI requires the next ULEB128 relocation to come after a R_RISCV_SET_ULEB128 is an R_RISCV_SUB_ULEB128, not another R_RISCV_SET_ULEB128.\n", + me->name); + return -EINVAL; + } + uleb128_set_exists = true; + uleb128_set_loc = location; + uleb128_set_sym_val = + ((Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[i].r_info)) + ->st_value + + rel[i].r_addend; + } else if (type == R_RISCV_SUB_ULEB128) { + if (uleb128_set_exists && uleb128_set_loc == location) { + /* Calculate set and subtraction */ + v = uleb128_set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with the first R_RISCV_SET_ULEB128 that comes before it. PC = %p\n", + me->name, location); + return -EINVAL; + } } res = handler(me, location, v); From patchwork Mon Oct 16 17:36:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13423885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BDB7CDB483 for ; Mon, 16 Oct 2023 17:36:24 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id F18188E000D; Mon, 16 Oct 2023 13:36:22 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id EC7A880008; Mon, 16 Oct 2023 13:36:22 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id CF3888E0011; Mon, 16 Oct 2023 13:36:22 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id C09CE8E000D for ; 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Mon, 16 Oct 2023 10:36:19 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id lv15-20020a056871318f00b001e0fd4c9b9asm2092936oac.6.2023.10.16.10.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 10:36:19 -0700 (PDT) From: Charlie Jenkins Date: Mon, 16 Oct 2023 10:36:10 -0700 Subject: [PATCH v3 2/2] riscv: Add tests for riscv module loading MIME-Version: 1.0 Message-Id: <20231016-module_relocations-v3-2-a667fd6071e9@rivosinc.com> References: <20231016-module_relocations-v3-0-a667fd6071e9@rivosinc.com> In-Reply-To: <20231016-module_relocations-v3-0-a667fd6071e9@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: B01D4A002F X-Rspam-User: X-Stat-Signature: m46heriwdzoj9ow3ydwqo7igygg6up46 X-Rspamd-Server: rspam01 X-HE-Tag: 1697477780-608532 X-HE-Meta: U2FsdGVkX1/Em7uzkPA9EJHYUBzKe4cpjuKjR6M4uWlbMlQ2edlkA5cPWH9R0rZqA27ibGYeK44zc4ODIHaDvem5EhtUW1H2YUBXXfmOruarJ2aHVOtWxakie3wZHr9nJlFrFudTWZlDIWPBt5y6YrYtwOLqoMlTTZJXiG7pxHgJskcwC6WinV3osdTPh0s2F3eVzh1EDdLm7BAG347H+F46BFhObj97ppEZ62BYZq1cYIO30vIm0E9zJvuqzutjLctFkO3pLnEi43/+Y+aGCAn426M7zb6wpF1FV/dBhIFRGbGamLUEfedpADYAo9gcyzOEczdzaBZo+tXF4Mhk+ZMarD+HI0iZKRQknxqhUUNEWjOJiumtLd7dl1P+Jxcot7z6BKEURp0Ku9Isecqx7hwq0nVmsUwn39DRBEoQ8TN87glO9KhMvL+/PmIKXyVrMay8rMlsgqgeA2OLZtpEkpHKCPQzqa85D+EvzQgUZaz9rxR3YO/LQ6VaaL0wFJrN+QaxUslQlODXXs0r/MK/QzcNri3tFbmft2LTOR0ZrALFkUSbhd+4/9KxZSorqiiCSaRknyu5Ojm8Al9EiBOa4wSXs9ba4k41GKVQtuSQ2IjyBH7N7/c19C6GufSXejrHHSl5jhqdRW0DI1zc6U8ucjSI8PRj6uiwYTfN4NErr5e2C/0oiXdjiEdDyH/rDOCFOEMaojDRJXBUxyeTtlPTRxvV3AAwzTavWwBE7Un0PllX/Ey/6OWxYgO6ElsvEm4bxzfSM0BYvbsgFQHkD9uY1U4v5sxOI05ZgS0r44UkMSIJUI9SUdSCuoPzyXKnzyT6CnFSAlS7f+rASYQrNwsD53c8JdGpEkW+Ht5vavF7+6pdK7b/ROc/jmTa7xq6rBf/l06x3GiwB6caQJU51/DEKZVTfvSR/uSuEbaEokUmpdNfGeESYZwVGYJy1ibdAIZky2Y3VWR5F6Jqp/yflJ4 nfgJ8+6H /LJyZ5+CkgZI/U4vCHU1AgoZStT3j6ZAC0RfkQCDt6Qvx6Toobb7OU3ktkLl6KxyZofuclBYENtUgSrpZV8P8UGQdjtwr38eaPZSjwEa0b2eVb7mLJ3Wrk526jWK0/2R8vhn2UoKpP3Q6DCVk34Wp2wvJGWZkPMs2Q0r3JyR9r+k/AeoCW2GUjR8qqBXPDhOXyrhh7vhjXAXKP0zM4R5FQ0i5wMBAQWyytLRhO1UkGaVnZgtgDiz/Ybj6ox1K5T4bv4Y8Z5V6sGxWPE5spdTWh+YWUbgwsN7Lg8jGUix+Ed39Y2SskKKt6GQmqwtZ2WsW8BJbp7PdHQ24jOqltxDGz5dnt18UWL3c1j3B0jt/g5Qh85yUyvJdXWHH/DYY8+/U9Etmj6dI7GzZNwtAXYvssUeUOvk9kLcDrnxVhjjCTJ0hLEZdnG03qDutDOie50LQ/iS8VY491Y4ZptV6LUOdjBU9mD6q/XMrzKYvC4Ap5BneDUDrJISPtHeGmCHvPDz+aYcfScJ1MXbxe6I= X-Bogosity: Ham, tests=bogofilter, spamicity=0.001058, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128 which is a bit different because SUB and SET are required to happen together. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 32 +++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 +++++ .../tests/module_test/test_module_linking_main.c | 78 ++++++++++++++++++++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 ++++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 +++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 ++++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 20 ++++++ 16 files changed, 352 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ +obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug new file mode 100644 index 000000000000..05ca55fb4645 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug log + in TAP format (http://testanything.org/). Only useful for kernel devs + running the KUnit test harness, and not intended for inclusion into a + production build. + + For more information on KUnit and unit tests in general please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Makefile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kernel/tests/module_test/Makefile new file mode 100644 index 000000000000..cacd50cd1127 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m += test_module_linking.o + +test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o + +test_set := test_set6.o test_set8.o test_set16.o test_set32.o + +test_uleb := test_uleb128.o + +test_module_linking-objs += $(test_sub) + +test_module_linking-objs += $(test_set) + +test_module_linking-objs += $(test_uleb) + +test_module_linking-objs += test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..dd1cfc03040e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Test module linking"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); +extern int test_uleb(void); + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test); +void run_test_sub(struct kunit *test); +void run_test_uleb(struct kunit *test); + +void run_test_set(struct kunit *test) +{ + int val32 = test_set32(); + int val16 = test_set16(); + int val8 = test_set8(); + int val6 = test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 = test_sub64(); + int val32 = test_sub32(); + int val16 = test_sub16(); + int val8 = test_sub8(); + int val6 = test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_uleb(struct kunit *test) +{ + int valuleb = test_uleb(); + + CHECK_EQ(valuleb, 0); +} + +static struct kunit_case __refdata riscv_module_linking_test_cases[] = { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), + KUNIT_CASE(run_test_uleb), + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite = { + .name = "riscv_checksum", + .test_cases = riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/kernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/kernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/kernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/kernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..db9f301092d0 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb +test_uleb: + ld a0, second + addi a0, a0, -127 + ret +.data +first: + .rept 127 + .byte 0 + .endr +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0