From patchwork Tue Oct 17 16:01:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 13425589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24B6ACDB482 for ; Tue, 17 Oct 2023 16:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235082AbjJQQBa (ORCPT ); Tue, 17 Oct 2023 12:01:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235046AbjJQQB3 (ORCPT ); Tue, 17 Oct 2023 12:01:29 -0400 Received: from dellerweb.de (dellerweb.de [173.249.48.176]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E70C69E for ; Tue, 17 Oct 2023 09:01:25 -0700 (PDT) Received: from mx3210.localdomain (unknown [142.126.114.79]) by dellerweb.de (Postfix) with ESMTPSA id 672D116002C7; Tue, 17 Oct 2023 18:01:21 +0200 (CEST) Received: by mx3210.localdomain (Postfix, from userid 1000) id 4529E22012C; Tue, 17 Oct 2023 16:01:09 +0000 (UTC) Date: Tue, 17 Oct 2023 16:01:08 +0000 From: John David Anglin To: linux-parisc@vger.kernel.org Cc: Helge Deller , James Bottomley Subject: [PATCH] parisc: Add nop instructions after TLB inserts Message-ID: MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org Helge wrote recently: In some document I read that newer PA2.0 CPUs had a pipeline of up to 12 instructions (instead of 8?). Could it be that we need to change our code to cope with that, e.g. while switching to/from virt/phys mode, or enabling/disabling IRQs ? Looking up the actual reference, I found this statement: o The PA8800 violates the seven instruction pipeline rule when performing TLB inserts or PxTLBE instructions with the PSW C bit on. The instruction will take effect by the 12th instruction after the insert or purge. While I don't believe we have an issue with the code mentioned by Helge, I believe we have a problem with handling TLB misses. We don't fill the pipeline following TLB inserts. As a result, we likely fault again after returning from the interruption. The above statement indicates that we need at least seven instructions after the insert on pre PA8800 processors and we need 12 instructions on PA8800/PA8900 processors. Here we add macros and code to provide the required number of nop instructions. Tested on c8000. Signed-off-by: John David Anglin diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index 0e5ebfe8d9d2..3412e57dc7b4 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -437,6 +437,64 @@ #endif .endm +/* + * We need seven instructions after a TLB insert for it to take effect. + * The PA8800/PA8900 processors are an exception and need 12 instructions. + * The RFI changes both IAOQ_Back and IAOQ_Front, so it counts as one. + * We need these nops to avoid faulting again after the RFI. + */ + .macro ptl_unlock0_nops +#ifndef CONFIG_TLB_PTLOCK + nop + nop +#endif +#ifdef CONFIG_64BIT + nop + nop + nop + nop + nop +#endif + nop + nop + nop + nop + .endm + + .macro ptl_unlock1_nops +#ifndef CONFIG_TLB_PTLOCK + nop + nop + nop +#endif +#ifdef CONFIG_64BIT + nop + nop + nop + nop + nop +#endif + nop + nop + nop + .endm + + .macro nops +#ifdef CONFIG_64BIT + nop + nop + nop + nop + nop +#endif + nop + nop + nop + nop + nop + nop + .endm + /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and * don't needlessly dirty the cache line if it was already set */ .macro update_accessed ptp,pte,tmp,tmp1 @@ -1126,6 +1184,7 @@ dtlb_miss_20w: idtlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1134,6 +1193,7 @@ dtlb_check_alias_20w: idtlbt pte,prot + nops rfir nop @@ -1152,6 +1212,7 @@ nadtlb_miss_20w: idtlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1160,6 +1221,7 @@ nadtlb_check_alias_20w: idtlbt pte,prot + nops rfir nop @@ -1186,6 +1248,7 @@ dtlb_miss_11: mtsp t1, %sr1 /* Restore sr1 */ ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1195,6 +1258,7 @@ dtlb_check_alias_11: idtlba pte,(va) idtlbp prot,(va) + nops rfir nop @@ -1219,6 +1283,7 @@ nadtlb_miss_11: mtsp t1, %sr1 /* Restore sr1 */ ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1228,6 +1293,7 @@ nadtlb_check_alias_11: idtlba pte,(va) idtlbp prot,(va) + nops rfir nop @@ -1248,6 +1314,7 @@ dtlb_miss_20: idtlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1256,6 +1323,7 @@ dtlb_check_alias_20: idtlbt pte,prot + nops rfir nop @@ -1276,6 +1344,7 @@ nadtlb_miss_20: idtlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1284,6 +1353,7 @@ nadtlb_check_alias_20: idtlbt pte,prot + nops rfir nop @@ -1321,6 +1391,7 @@ itlb_miss_20w: iitlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1345,6 +1416,7 @@ naitlb_miss_20w: iitlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1353,6 +1425,7 @@ naitlb_check_alias_20w: iitlbt pte,prot + nops rfir nop @@ -1379,6 +1452,7 @@ itlb_miss_11: mtsp t1, %sr1 /* Restore sr1 */ ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1403,6 +1477,7 @@ naitlb_miss_11: mtsp t1, %sr1 /* Restore sr1 */ ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1412,6 +1487,7 @@ naitlb_check_alias_11: iitlba pte,(%sr0, va) iitlbp prot,(%sr0, va) + nops rfir nop @@ -1433,6 +1509,7 @@ itlb_miss_20: iitlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1453,6 +1530,7 @@ naitlb_miss_20: iitlbt pte,prot ptl_unlock1 spc,t0 + ptl_unlock1_nops rfir nop @@ -1461,6 +1539,7 @@ naitlb_check_alias_20: iitlbt pte,prot + nops rfir nop @@ -1483,6 +1562,7 @@ dbit_trap_20w: idtlbt pte,prot ptl_unlock0 spc,t0 + ptl_unlock0_nops rfir nop #else @@ -1509,6 +1589,7 @@ dbit_trap_11: mtsp t1, %sr1 /* Restore sr1 */ ptl_unlock0 spc,t0 + ptl_unlock0_nops rfir nop @@ -1529,6 +1610,7 @@ dbit_trap_20: idtlbt pte,prot ptl_unlock0 spc,t0 + ptl_unlock0_nops rfir nop #endif