From patchwork Wed Oct 18 05:34:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13426358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B89ACDB483 for ; Wed, 18 Oct 2023 05:34:24 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 9FFAD8D0135; Wed, 18 Oct 2023 01:34:23 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 989B08D0016; Wed, 18 Oct 2023 01:34:23 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 7DB0E8D0135; Wed, 18 Oct 2023 01:34:23 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 6941D8D0016 for ; Wed, 18 Oct 2023 01:34:23 -0400 (EDT) Received: from smtpin25.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id 079A8A011F for ; Wed, 18 Oct 2023 05:34:23 +0000 (UTC) X-FDA: 81357466806.25.8294B2C Received: from mail-oi1-f170.google.com (mail-oi1-f170.google.com [209.85.167.170]) by imf06.hostedemail.com (Postfix) with ESMTP id 15E0F180009 for ; Wed, 18 Oct 2023 05:34:20 +0000 (UTC) Authentication-Results: imf06.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=TRat4qUz; dmarc=none; spf=pass (imf06.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.167.170 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1697607261; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=OELvmjl8TvVyyYpwL5ZdJ++6dSrSubhhgdZhPRkcjlI=; b=qcBVAv43pWmISd8AXd2KUzeBqEN76zCQztiHHpEciEkavBMwfZmyrU+MLz7iJzyDJwDzkm sSFiHejpV6uzLpTIkyEXEqqG3x4352w8JLFeTeA3M3O++4nQBRM0EA5CBo89Np5rhJ1q/A DqWK15ZuHYzcJmR/KjWAAP7MvQ71RPY= ARC-Authentication-Results: i=1; imf06.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=TRat4qUz; dmarc=none; spf=pass (imf06.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.167.170 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1697607261; a=rsa-sha256; cv=none; b=eTKGVSJQpGh8hsehu33r3vzNlZnKLLXHUNy3vbYRfJkaZiO9rLKKGWrQF6+F3TU0c7ZDYA fYphQAKZZ7OD3g39VXzm/VcBhGwq38Y/cURicO8ZFolR7a6UEUKi3xfwT1QDrAYEQK9qnJ WUz7FDXDvLSt/+87hkbnmJLt+pN0OPM= Received: by mail-oi1-f170.google.com with SMTP id 5614622812f47-3b2b1ad7ee6so3020161b6e.2 for ; Tue, 17 Oct 2023 22:34:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697607260; x=1698212060; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OELvmjl8TvVyyYpwL5ZdJ++6dSrSubhhgdZhPRkcjlI=; b=TRat4qUzvvegPZNGHeNo8U9FYuTO3Y5aUX9jsGOdz+ts6uj9m7dau/66Cc862GAxgK +GAS/ONfPMqP0R/+RneRi6yO3i6NqkzvwQGvL3B7kyc3MHMge/hgSbq/sgskj1v3tH5n ZdYOnISDgN7+HWZzicjL+trKebZQBEIJpb1pdSmD3dmSnU2VMLOe+ut8l8ULuSbr2/N4 2tkh3EhxRl1/3wjMDzytDb3a4UABMMXgIAXKqh0Rhmz5XMNTzGTAxwb2+/nYAeepuQww u/jgCDjeUxpk9lh5qqmP9l7HlcPsyrmAGd4sR6FwJFufaVsvPotlalx4bubp3NtmLVoG SGlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697607260; x=1698212060; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OELvmjl8TvVyyYpwL5ZdJ++6dSrSubhhgdZhPRkcjlI=; b=g+UkJn3QXCKC9F8bEli4zNK8R0GBd6NJYA66FM8caSohbZnVK0p+iiZ3OSuav+j8tR 4/YACD6fhDMmdkIeFqXmNg/cRWhohRICArsqPTjPBOH1afqnaIDt2HN/jq7wu3z7Bc2t VOUOZ2PAAleG3gos0G5gLhXvXANznbJy9mKg8xSSd02+ap28kw0ouM/Cn1h3Bcmn0Se3 Ddd01FjzXxUHPwhjrnTesrROVqPqMwTarS+V/Y8uKhs+EZFHhSAjJhjcR/7PqBbNcQjb vbzZrvM+hTV5aZCkJ9h3krebrhIq2i7H+TUqXTrWM3HjqVG5ZAXg2xMVw8BhRZumyUuR qqPA== X-Gm-Message-State: AOJu0YxukTQjnuHA2QQIcEJSpZevXNvN8KIUq6Qu1+1uXpDOb+SvfF1J C2uBsx+ocLJ2lLDHmuy4MALyiw== X-Google-Smtp-Source: AGHT+IFqqpuoIqNyxa4tR2CImQYcrwRx47GYt06/P6+232P2FtKe7196v3jQIEQBSHtQ/2SCbYzqcA== X-Received: by 2002:a05:6808:2cf:b0:3a7:f153:b5e5 with SMTP id a15-20020a05680802cf00b003a7f153b5e5mr4344090oid.29.1697607260182; Tue, 17 Oct 2023 22:34:20 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z26-20020a54459a000000b003af60f06629sm527977oib.6.2023.10.17.22.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 22:34:19 -0700 (PDT) From: Charlie Jenkins Date: Tue, 17 Oct 2023 22:34:16 -0700 Subject: [PATCH v4 1/2] riscv: Add remaining module relocations MIME-Version: 1.0 Message-Id: <20231017-module_relocations-v4-1-937f5ef316f0@rivosinc.com> References: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> In-Reply-To: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 15E0F180009 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: zibffn8eq7mda4wawtuy6xyxsf31pcp8 X-HE-Tag: 1697607260-917091 X-HE-Meta: U2FsdGVkX19qBLz7SJoNckiAWuMbfjkhZyD5Rq24C9zMx/f4GiKEP/O7OOYfE7bKq2g80VbblnFybIQEldgR2b6mFx3fM0CyjeSr3/I2P1EUX2+vsn9+DzuUmuekZH4zKNHuu1xKAA23AjfZLgei6mYVAaD4cGiw+JMUeFQsl0h6CN3+0BNMOLfb/3bdsUz/vb/3+ZDQUJ4lTu3Owo5cvRntLbb2+DBzrRUyOYTOilcOk7xuCsyfid6pldB59qPYW0gy6aDYkPYfdVFzGZRRSU78AUwr0ML+atvETsHXOGnrbkUOkC+kEq09TTnhltQLG7uifGP3Qbb87UF59w/0w2yAulkeRjg7OgbI5IoQbAWPE+VMokmQbMUtUOBCocZqXbA6/4NtT4pzhsTY8/Tvk11tcDkjD95tsjX9HECBWgucWmuDmhU0uK+ek7txaQQe1RQR03O8dl/tIpixF3Z92of+oq4fx4seYrhJv5n2dcRt5M/vIVSysvDnJlCpGO0ieHtUl0wnkTA0Lz/7uyg1folBoN8KftH8VeeP3oORfX+dJEuMbMqjhcuZgIZxDsYGLcI8W8wkqVDmpu3pommul4Pa3/1YOrmHXItnjMBTKv6ICFZWrhH1OH8nNJV0XXKLLVV+eexvDcOCb9rcFQPHkxWYnxTsFK5YjiAqtRN/DL3MNMEYCaEqgV+sS2KpA13nNl+VZQ4wFTRMS2J3Rv0uiLwoYUX5jwBjSICVx3VbkgbChHifd6ggXR2I7bLawLnDeq5sGcZv6byQEN5RfKfU/kAH/IDbVwS1vMC1ws6g9+4zxZIpxiRi01aFAQQPXoDwR9BVQNhNwdTt72B4f6xXBltf/Zuc8S7g/kzrwSmn2Gth8Uptm+k+6BQ+an4L9i/+LzKAlRZwf5/Nz7F0lwKh0BQa4jwGGBSf/mm6P18yX13ztsOIq+3XJuY5/S9C99NrJaVEr1QMERnup5ynvyh sWOgeiW+ ZG4Tw+bNaNjtb6ZvbR0cUE4TWIoT8SCDiL7Aj5nK2q9kxPN9hTx8Op6L/Du3CN2JTIaZ6DM0LFHA28CjGKSgvnKhIZMvf3bojNt5HRC2JK9Sf2yadz7AHYqCKIzMFncfPRo+bUGZegWsIFqiNSfswiStANPu2eHRMDGoDJXLCHPrFAARKadt87v1Ib3w1NI3o/o2iiiAMPMAYIxCIk0wRnDnhA7Ud/g96s3BPssJE68JIHdcMn4LeTjzIYEbg5n+Thi9Q/nsWeb82cPrPQafDYY0jAn4eRxGg/mRrdHMzCwIyE4zvEpn6ZpPMgI0VHSRkI/EYYjNgJNLcnk7rlNiiwH8nJyjSlnkEnNhaHGAqu2QdTnbU+dJulCLtnSjji2bsacSFCx88qELm7SX35jvoTzradRgAJfwuoWKx7TD7rjYQFTwNAT9B2dxv0jkpUlLm0rI+LT5+j+LuQ3M= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000338, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add all final module relocations and add error logs explaining the ones that are not supported. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 5 +- arch/riscv/kernel/module.c | 207 +++++++++++++++++++++++++++++++++----- 2 files changed, 186 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..11a71b8533d5 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..e860726352ac 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -268,6 +269,12 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } +static int apply_r_riscv_add8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location += (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -289,6 +296,12 @@ static int apply_r_riscv_add64_rela(struct module *me, u32 *location, return 0; } +static int apply_r_riscv_sub8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, Elf_Addr v) { @@ -310,31 +323,149 @@ static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, - Elf_Addr v) = { - [R_RISCV_32] = apply_r_riscv_32_rela, - [R_RISCV_64] = apply_r_riscv_64_rela, - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, - [R_RISCV_JAL] = apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] = apply_r_riscv_call_rela, - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, u32 *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, u32 *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (*location - ((u8)v & 0x3F)) & 0x3F; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (*(u8 *)location & 0xc0) | ((u8)v & 0x3F); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, u32 *location, Elf_Addr v) +{ + *(u8 *)location = (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u16 *)location = (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, u32 *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + /* + * Relocation is only performed if R_RISCV_SET_ULEB128 is followed by + * R_RISCV_SUB_ULEB128 so do computation there + */ + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, u32 *location, Elf_Addr v) +{ + if (v >= 128) { + pr_err("%s: uleb128 must be in [0, 127] (not %ld) at PC = %p\n", + me->name, (unsigned long)v, location); + return -EINVAL; + } + + *location = v; + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static int (*reloc_handlers_rela[])(struct module *me, u32 *location, + Elf_Addr v) = { + [R_RISCV_32] = apply_r_riscv_32_rela, + [R_RISCV_64] = apply_r_riscv_64_rela, + [R_RISCV_RELATIVE] = dynamic_linking_not_supported, + [R_RISCV_COPY] = dynamic_linking_not_supported, + [R_RISCV_JUMP_SLOT] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPMOD64] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_DTPREL64] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL32] = dynamic_linking_not_supported, + [R_RISCV_TLS_TPREL64] = dynamic_linking_not_supported, + /* 12-15 undefined */ + [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, + [R_RISCV_JAL] = apply_r_riscv_jal_rela, + [R_RISCV_CALL] = apply_r_riscv_call_rela, + [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, + [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, + [R_RISCV_TLS_GOT_HI20] = tls_not_supported, + [R_RISCV_TLS_GD_HI20] = tls_not_supported, + [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, + [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, + [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, + [R_RISCV_HI20] = apply_r_riscv_hi20_rela, + [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, + [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, + [R_RISCV_TPREL_HI20] = tls_not_supported, + [R_RISCV_TPREL_LO12_I] = tls_not_supported, + [R_RISCV_TPREL_LO12_S] = tls_not_supported, + [R_RISCV_TPREL_ADD] = tls_not_supported, + [R_RISCV_ADD8] = apply_r_riscv_add8_rela, + [R_RISCV_ADD16] = apply_r_riscv_add16_rela, + [R_RISCV_ADD32] = apply_r_riscv_add32_rela, + [R_RISCV_ADD64] = apply_r_riscv_add64_rela, + [R_RISCV_SUB8] = apply_r_riscv_sub8_rela, + [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, + [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] = apply_r_riscv_align_rela, + [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, + [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, + /* 46-50 reserved for future standard use */ + [R_RISCV_RELAX] = apply_r_riscv_relax_rela, + [R_RISCV_SUB6] = apply_r_riscv_sub6_rela, + [R_RISCV_SET6] = apply_r_riscv_set6_rela, + [R_RISCV_SET8] = apply_r_riscv_set8_rela, + [R_RISCV_SET16] = apply_r_riscv_set16_rela, + [R_RISCV_SET32] = apply_r_riscv_set32_rela, + [R_RISCV_32_PCREL] = apply_r_riscv_32_pcrel_rela, + [R_RISCV_IRELATIVE] = dynamic_linking_not_supported, + [R_RISCV_PLT32] = apply_r_riscv_plt32_rela, + [R_RISCV_SET_ULEB128] = apply_r_riscv_set_uleb128, + [R_RISCV_SUB_ULEB128] = apply_r_riscv_sub_uleb128, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, @@ -348,6 +479,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int i, type; Elf_Addr v; int res; + bool uleb128_set_exists = false; + u32 *uleb128_set_loc; + unsigned long uleb128_set_sym_val; + pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); @@ -425,6 +560,28 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, me->name); return -EINVAL; } + } else if (type == R_RISCV_SET_ULEB128) { + if (uleb128_set_exists) { + pr_err("%s: riscv psABI requires the next ULEB128 relocation to come after a R_RISCV_SET_ULEB128 is an R_RISCV_SUB_ULEB128, not another R_RISCV_SET_ULEB128.\n", + me->name); + return -EINVAL; + } + uleb128_set_exists = true; + uleb128_set_loc = location; + uleb128_set_sym_val = + ((Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[i].r_info)) + ->st_value + + rel[i].r_addend; + } else if (type == R_RISCV_SUB_ULEB128) { + if (uleb128_set_exists && uleb128_set_loc == location) { + /* Calculate set and subtraction */ + v = uleb128_set_sym_val - v; + } else { + pr_err("%s: R_RISCV_SUB_ULEB128 must always be paired with the first R_RISCV_SET_ULEB128 that comes before it. PC = %p\n", + me->name, location); + return -EINVAL; + } } res = handler(me, location, v); From patchwork Wed Oct 18 05:34:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13426359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24DA5CDB47E for ; Wed, 18 Oct 2023 05:34:26 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id AEDE68D0136; Wed, 18 Oct 2023 01:34:24 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id A74C98D0016; Wed, 18 Oct 2023 01:34:24 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 802DE8D0136; Wed, 18 Oct 2023 01:34:24 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 642B68D0016 for ; Wed, 18 Oct 2023 01:34:24 -0400 (EDT) Received: from smtpin19.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id 31B0D1CBD92 for ; Wed, 18 Oct 2023 05:34:24 +0000 (UTC) X-FDA: 81357466848.19.E842824 Received: from mail-oi1-f174.google.com (mail-oi1-f174.google.com [209.85.167.174]) by imf26.hostedemail.com (Postfix) with ESMTP id 5F222140014 for ; Wed, 18 Oct 2023 05:34:22 +0000 (UTC) Authentication-Results: imf26.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=mlLGzVPK; dmarc=none; spf=pass (imf26.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.167.174 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1697607262; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=a7aDnvhFdfn1ml5kisVWbMxqXUHugy1VPt3yFyaG7Vc=; b=WE5nQpg5Fzw8PkJqowvUduxspYYQKqPE76dlF/M84y9PhJL9+709zhx5Qg5ymDPMilpgjO 3F9g5uF4IS0ZiJcG3jK+3+7WGJopyPaKZps9c19lTpsoOZQRrP515pKdLUDqFL+2ulqcF9 ttBmkn/UwosA9Dg58/IyB5ewn16cOEI= ARC-Authentication-Results: i=1; imf26.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=mlLGzVPK; dmarc=none; spf=pass (imf26.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.167.174 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1697607262; a=rsa-sha256; cv=none; b=oO6m/Yuqhz9ittwepaUA8gNFqLbIzaH/elj2rXWOrDp67A5TO8nqSXcxW7okX1Mqy620hn QYz5+lchbKZvLNxM2RexT0zvtejBDnRZYtYEnZ7Glf3kuwYFHuOHUIZzYHWorMVjiFNkZF gU6k42iurOrr1jRAHVEKyJBGrUQKhKo= Received: by mail-oi1-f174.google.com with SMTP id 5614622812f47-3b2b1af964dso3592049b6e.1 for ; Tue, 17 Oct 2023 22:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697607261; x=1698212061; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=a7aDnvhFdfn1ml5kisVWbMxqXUHugy1VPt3yFyaG7Vc=; b=mlLGzVPK3Gf3WWjQlRyKMmiuTtILDVrzZoZvJf2oA91eQLuB55blCWk69oR7fwkN+H kEZyLumALgtBkZs6IpDgI0uV/GWnWnS4BFOMh3vtKGnBcpzuhos9f6g6Q9W7XxItQNma DXmbPFE7bpoZbPVQchHNkZIyEk+OjoRxW37m6aZG6pf8s3x/e5YQu+z8vY3IGVtwzFem +HUlaUFhokBeIaXp7I4+14eA26MsxA1AzbgjyEsehsDYWMVzo/SCk7nP6njHgDxa1oQ6 LqLSlki6FGHeO9z84XGicy+TT5JwVKzfV7vgj0LuxoVSCskVRLMuAN5kxEXzR/xomPuM V3Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697607261; x=1698212061; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a7aDnvhFdfn1ml5kisVWbMxqXUHugy1VPt3yFyaG7Vc=; b=Xj2fYoIcnURMX1BQfuak1xzM3G04TXdCRFenJFz9fzePt/krtLuSHHYssNj/isLZFf gcE2QOFZ91x9mK6KHeebulmmFNYi3ez15DA0vaeXPaKalO0zK91W9gjfmfg8ZlUY+pEz SaifAN7p9ChhKPv00becmOcwzvp91tm4IayTpgCsA76+lMh14FjJ31jMObIK59937Jc4 /q3QnTqvqZEe/uZ66MKSCX6yCzFX1MBH6tWCgKdGCgUXRwiBT4tpkdeSbbfK2FzwuVIM ZaDJAB1iqiov0qKhKDnknBI1v7ovcL2Q385puoBGEwEF+prNRzh6yooKWCi0LuLu/fo7 b3dA== X-Gm-Message-State: AOJu0Yzv5PLlR0MpPIC1fIdJo+C7yRyimbNJn6QQpbbZkAAI70kxCLN8 EEGGSXDjrKP1bDZCTCi/IX7REM69aM4HBjnYZbg= X-Google-Smtp-Source: AGHT+IExAcFisyDW3445+SgBpmFhUdvCYk9+wFN+s0RBJKGEy4MfVK6iXMNlw4+b0GlDGy9raTqDNA== X-Received: by 2002:a05:6808:1413:b0:3ae:170f:a3b3 with SMTP id w19-20020a056808141300b003ae170fa3b3mr5771703oiv.26.1697607261481; Tue, 17 Oct 2023 22:34:21 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id z26-20020a54459a000000b003af60f06629sm527977oib.6.2023.10.17.22.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 22:34:20 -0700 (PDT) From: Charlie Jenkins Date: Tue, 17 Oct 2023 22:34:17 -0700 Subject: [PATCH v4 2/2] riscv: Add tests for riscv module loading MIME-Version: 1.0 Message-Id: <20231017-module_relocations-v4-2-937f5ef316f0@rivosinc.com> References: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> In-Reply-To: <20231017-module_relocations-v4-0-937f5ef316f0@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 5F222140014 X-Rspam-User: X-Rspamd-Server: rspam05 X-Stat-Signature: bkbq3yiarozkkrypubzkd37oqdx77ipf X-HE-Tag: 1697607262-671517 X-HE-Meta: U2FsdGVkX1+PUB6WfOgzmrfrPjl4rwbYtIJc4NjQ/okDJEJi7VOyI48OkF6rI80+lzfMKULe3g9hefJMpBIIJ1dFa7ZAMRKvBbvoOPzmuEVuG/7DMfcUBipCtmpTvRXhF81wICZJYulMCjKvw0DpobMIxLBcPdoSsyG0Sit/p9y1eOlFCp2zDV7UsFTYD1R4y52X0SDOFX/TXX90mjGsIrML6xLhydpthglWYcbl5mym613vEkjR5Am4opG8jJZskTAFQmf4J4TRFsmD4wfyuBRLi04fhMmgzyIzeGo/cZwPx3Og30TEq5PXLqVKuWJhz8d56i8W3tJnIjwUBKmDrPrnjQMFKJilQFS7fLPb0b5Qo5srd9Yd3z1hYM4bKJiZHULsdg6cd32bulXo6q3bQvYa4WF9wI47g1iBLh7v9tEsUAavBA3nSz9yUeeDjoeaIl5zdwa5cQuTfoh2PyJADWnt9sTHjxsOl12ZbWEzUbCRZnqXQ/T7BdD98QjhpD7DRZWdNlIEgl4X/1caEa8ympx/NjRf3E1jaZ7xc2SLu11/TtSrPs2VADLqPHJSzSV9mODCZODrV68x+CeLZ1pGvQc+eu8J7FZOHc1HcHMFG5M/oq9N+hrEc3MUqAqebf0yo6niSgTGNPc09tUaBYW8NViq6oZv8oT7qZok9ajw12/XlHKdr8a/cJIvZdDb+CtfsTn1Jk/8bQVSLi0XNdOADLRRg0U2q+TTJFWw6U4DC/ZNikyyy8hUV5NYuWxwUo5YG8DS+i6Ta6OBe5H7wyU7T+hdBPXl9pQNx933TqTl1tQdlficidJbAhK97aIXmryAxfDEQX2OD3ihthQVWDOz9wPCrR+TYs58KkwnDNT//tcp6hmIN7FwlNWw090ADYColQaXo3kPw3j5mYydLDJmBMCIsfiZFubrpB7mwlu+PIvmMCuHsYJnBHK2AMcAoHBhDaUOFYkt9V+zd/1ETrw tOX8IrSY bWlxR8omWHY/xnsauB9L4zzOVB2mw2hWKcvti+D7vl03VqTN7VwpC2izgqht6EKuMXjnfxf/9Sc3qzEazhjLDN+MZus3XzzRdcqQOPMHAtwdCZNlqGv5nFD19FSwSZe67c+GN0ZXrQwRjAyN14WXnAjhR8c152jq7xbzQcLKlWEr23J1EJq/UrdTHNqaFZcZXSH/5wZtpL3qoXFYaOARBaRorwJoq+YT7trIuEIgvoRlTYwUC4pgbCWkXycsAZHXs4eRaxa5VxHFNNMoS777eX86dyQ48MPNsXb591LYC5PkGxCc5rNEIM/TG/mzgAwRFGK4vjgHRG21RpZpA+4wVFbXMeuSf9lTqzm8G4d8WlBMHDNK9oiHFWU5huTIrCfYmwAoDQZa9FJaAJa3Usrqjiu6K8lI7P+oVyzo+YJ0mUrB3EYosoSnuSUYBaxPOc1797y8JBLC7hWa8YJN0fAWqwj+SR0nNv5PhYWLNktckOj2IA9h6G9lvUW4Ev98naMEzzAoFQY7/LyEhpRw= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000553, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128 which is a bit different because SUB and SET are required to happen together. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 35 +++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 ++++ .../tests/module_test/test_module_linking_main.c | 85 ++++++++++++++++++++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 27 +++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 22 ++++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 20 +++++ 16 files changed, 362 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ +obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug new file mode 100644 index 000000000000..5dba64e8e977 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +config AS_HAS_ULEB128 + def_bool $(as-instr,.reloc label$(comma) R_RISCV_SET_ULEB128$(comma) 127\n.reloc label$(comma) R_RISCV_SUB_ULEB128$(comma) 127\nlabel:\n.word 0) + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug log + in TAP format (http://testanything.org/). Only useful for kernel devs + running the KUnit test harness, and not intended for inclusion into a + production build. + + For more information on KUnit and unit tests in general please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Makefile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kernel/tests/module_test/Makefile new file mode 100644 index 000000000000..d7a6fd8943de --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m += test_module_linking.o + +test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o + +test_set := test_set6.o test_set8.o test_set16.o test_set32.o + +test_module_linking-objs += $(test_sub) + +test_module_linking-objs += $(test_set) + +ifeq ($(CONFIG_AS_HAS_ULEB128),y) +test_module_linking-objs += test_uleb128.o +endif + +test_module_linking-objs += test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..49820352f1df --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Test module linking"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); + +#ifdef CONFIG_AS_HAS_ULEB128 +extern int test_uleb(void); +#endif + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test); +void run_test_sub(struct kunit *test); +void run_test_uleb(struct kunit *test); + +void run_test_set(struct kunit *test) +{ + int val32 = test_set32(); + int val16 = test_set16(); + int val8 = test_set8(); + int val6 = test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 = test_sub64(); + int val32 = test_sub32(); + int val16 = test_sub16(); + int val8 = test_sub8(); + int val6 = test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +#ifdef CONFIG_AS_HAS_ULEB128 +void run_test_uleb(struct kunit *test) +{ + int valuleb = test_uleb(); + + CHECK_EQ(valuleb, 0); +} +#endif + +static struct kunit_case __refdata riscv_module_linking_test_cases[] = { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), +#ifdef CONFIG_AS_HAS_ULEB128 + KUNIT_CASE(run_test_uleb), +#endif + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite = { + .name = "riscv_checksum", + .test_cases = riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/kernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/kernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..c561e155d1db --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..93232c70cae6 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/kernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..d9c9526ceb62 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..6d260e2a5d98 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/kernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..af7849115d4d --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .rept 8 + .word 0 + .endr +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..db9f301092d0 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb +test_uleb: + ld a0, second + addi a0, a0, -127 + ret +.data +first: + .rept 127 + .byte 0 + .endr +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0