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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:41 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 1/6] target/riscv: Propagate error from PMU setup Date: Wed, 18 Oct 2023 16:39:09 +0100 Message-ID: <20231018154434.17367-2-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Atish Patra --- target/riscv/pmu.c | 19 +++++++++---------- target/riscv/pmu.h | 3 ++- target/riscv/tcg/tcg-cpu.c | 8 +++++++- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 36f6307d28..13801ccb78 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -434,22 +434,21 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx) } -int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { - return -1; + uint8_t pmu_num = cpu->cfg.pmu_num; + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; } cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal); if (!cpu->pmu_event_ctr_map) { - /* PMU support can not be enabled */ - qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); - cpu->cfg.pmu_num = 0; - return -1; + error_setg(errp, "Unable to allocate PMU event hash table"); + return; } /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, num_counters); - - return 0; + cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 2bfb71ba87..88e0713296 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -17,13 +17,14 @@ */ #include "cpu.h" +#include "qapi/error.h" bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); void riscv_pmu_timer_cb(void *priv); -int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a28918ab30..ed3eb991c0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -614,7 +614,13 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) } if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { + riscv_pmu_init(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.ext_sscofpmf) { cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } From patchwork Wed Oct 18 15:39:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13427258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65B19CDB482 for ; Wed, 18 Oct 2023 15:46:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8j2-0001Yz-1M; Wed, 18 Oct 2023 11:44:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8j0-0001Xt-Cd for qemu-devel@nongnu.org; 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:42 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 2/6] target/riscv: Don't assume PMU counters are continuous Date: Wed, 18 Oct 2023 16:39:10 +0100 Message-ID: <20231018154434.17367-3-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Check the PMU available bitmask when checking if a counter is valid rather than comparing the index against the number of PMUs. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/csr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b4ab56c40..a6ea38e0ba 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -183,7 +183,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { - int pmu_num = riscv_cpu_cfg(env)->pmu_num; + RISCVCPU *cpu = env_archcpu(env); + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs; int ctr_index; int base_csrno = CSR_MHPMCOUNTER3; @@ -192,7 +193,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; - if (!pmu_num || ctr_index >= pmu_num) { + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) { /* The PMU is not enabled or counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } From patchwork Wed Oct 18 15:39:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13427256 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D20ECDB47E for ; Wed, 18 Oct 2023 15:45:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8j3-0001a6-CX; Wed, 18 Oct 2023 11:44:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8j1-0001Yl-LT for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:47 -0400 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qt8iz-0004wV-Js for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:47 -0400 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-507962561adso8367570e87.0 for ; Wed, 18 Oct 2023 08:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697643883; x=1698248683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AC8jq+P5CM/fRZxkStBxJxLjJuS0g72lNMKPJ6Ep+4k=; b=pGj7jbnpuqDIdu8FzGk8u1mT2AeU3JFU1OT8oVdwB75uKwEjZMNro77xwqts5DiNQI NR59I8ORUkPsujU18zo3RZ+tapE82P6W2l1oCQr57DhJgEs+EqPg2rKxVYPbZoHm0sSe GI2jgnCffZ6nFRoVkRgZ95uehVwYve/ZVkVdS7TBmKENfcFsu970aQpU1LuQAWk9+arM k8mLJ+0Vy+y7JMPnRwLsmQKOAyHBPx8HEUW2vkrwG3VlPHk5DlGzIWsIk69eiZcMx3Hu aEj6YksFGrDW6S3906e5QWpGlarQI06Ek5PJPj7RtSb8R4/A7fc3HraTak0K7gidpKV4 8VkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697643883; x=1698248683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AC8jq+P5CM/fRZxkStBxJxLjJuS0g72lNMKPJ6Ep+4k=; b=DeOrCrX9ybwAiYU6DQXeGjm6zbLmFgap98e5NzGE8gA6+VrNd9ZAG28ZWpE21pdQMS 9AQmsyJE+gdqaHHziUnuuYtBYx7vvIUnz70RHS7dlGue7pHgeplIDVF0K8KihjTwUPps steDL7h5569T14C3LJNVJbR0LxZbFjZL6TGLMJXQuIPdsXzv9qklpgFwVQURd9UKBkA8 W291Znz+yogQSR9KuyRaJa3eiCG7YtGWCfns8MJ2377KSUhkH+RpshuH4J3/3t4v+up/ 0j9o6+x7s5Z3ShhAR9/sYGZOFHttrxv36XSIcxYoNTG+PNj07eDMlqzdAsHgO8+d9uU+ KsEA== X-Gm-Message-State: AOJu0Yypz3uo99QB4sZT4KN1rGDdH+Tcr9ZJl6lABbx7kq6ku4yf8GKP XmBwqNC2VUuMXGgaqH2GBTp3QEEexkO8VVbHDH/x7g== X-Google-Smtp-Source: AGHT+IEPYsW1307G7J3z/hTPuqT3ph/TkCnsGor2XyGa661SN6qVswYx+mAyE5IvZqalQbf8QzplBw== X-Received: by 2002:ac2:528a:0:b0:507:9625:5fd3 with SMTP id q10-20020ac2528a000000b0050796255fd3mr4150861lfm.32.1697643883628; Wed, 18 Oct 2023 08:44:43 -0700 (PDT) Received: from rockhopper.ba.rivosinc.com (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:43 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation Date: Wed, 18 Oct 2023 16:39:11 +0100 Message-ID: <20231018154434.17367-4-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=rbradford@rivosinc.com; helo=mail-lf1-x12e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org During the FDT generation use the existing mask containing the enabled counters rather then generating a new one. Using the existing mask will support the use of discontinuous counters. Signed-off-by: Rob Bradford Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- hw/riscv/virt.c | 2 +- target/riscv/pmu.c | 6 +----- target/riscv/pmu.h | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9de578c756..241681f98d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -722,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) pmu_name = g_strdup_printf("/pmu"); qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); + riscv_pmu_generate_fdt_node(ms->fdt, hart.pmu_avail_ctrs, pmu_name); g_free(pmu_name); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 13801ccb78..7ddf4977b1 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -34,13 +34,9 @@ * to provide the correct value as well. Heterogeneous PMU per hart is not * supported yet. Thus, number of counters are same across all harts. */ -void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name) +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name) { uint32_t fdt_event_ctr_map[15] = {}; - uint32_t cmask; - - /* All the programmable counters can map to any event */ - cmask = MAKE_32BIT_MASK(3, num_ctrs); /* * The event encoding is specified in the SBI specification diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 88e0713296..505fc850d3 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -28,6 +28,6 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); -void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name); +void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name); int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); From patchwork Wed Oct 18 15:39:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13427259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41C92CDB47E for ; Wed, 18 Oct 2023 15:46:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8j4-0001b8-If; Wed, 18 Oct 2023 11:44:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8j2-0001ZM-CY for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:48 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qt8j0-0004wx-JO for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:48 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4081ccf69dcso11571935e9.0 for ; Wed, 18 Oct 2023 08:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697643885; x=1698248685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4CsNraule73OlT/OKW+2qowhTSvd6THabYDqC178ink=; b=w61FSHBfgXyEBIXX5icrmR4rKm+kvubfci/4rqkOBnn6PR5bZQqL7V/Ex6mhNHkMkA rG8Io7DpjM9k16KRFCiPUuPGtrG12Op/Ep/4HArxHwT/yreuoVepyLYcaBTH8MwGy/0V fis0YBSnrfFDYJPU/JdWrzYxBPxaf+ntY43FGQRlmp/hgcyvwu0nhwAX+WhIr+stcyMS 3qiSsBc3iE0HcTjde4/3T1tCd4kHhDB4Vm+0fue+ra0VBEW7gdVCWOlEAe1ayNSJ7DaH xOOnO8pnQ4n56TxnH9DWWvQ5sT6lhotfUfj/PIjIPWDUQim/mtop+nbDvFweCUa8qPUO TEjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697643885; x=1698248685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4CsNraule73OlT/OKW+2qowhTSvd6THabYDqC178ink=; b=o9M8HGxSlla1ONYLhFeDA+56TR74l4VabcZVq9+lCycoYzjf5nKi3rv9PiUiMYmZDV 1B65ZFtBFxCQOWoDtpTxObXjJgujtCPYFZuLcGAGozhUwIN9jgdUhuBrTU99Lkshj97d txLllEMnqT+omWOonpZqGtmRQizjaXsa+dQEj4Jj4pnsWGNmyGD5kPGpyQzHnAclTfSs 1L8rd7IM9uAovv66XQSsCFvtu/iTgigmJM4w9+fs5frsDuDuz6XP8cBeRGGWtwqkpVU0 8pmBZw4M0h2dXpK2t3rvgIOBflG1GQqzlakBpnJP7hBW8rBY9dOu5yNQILkrLRUeHtfH Oabg== X-Gm-Message-State: AOJu0Yw8ZIokFXJeK9a41nj+pTHgdKiNKcwUsitmDxIlYGoOWRiEOQ3p d741nLyfqEk7qhfKW8iGRE22ahDtEL+K0gfAbXMu4Q== X-Google-Smtp-Source: AGHT+IHnDDmBBAwuVOf247Cu1DjI5ENMfoL9J5y8xkXYsZOuglIl3+dKASGK/Cq0c23nPAkk25Vbcg== X-Received: by 2002:a05:600c:3b92:b0:403:aced:f7f4 with SMTP id n18-20020a05600c3b9200b00403acedf7f4mr5204685wms.12.1697643884973; Wed, 18 Oct 2023 08:44:44 -0700 (PDT) Received: from rockhopper.ba.rivosinc.com (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:44 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num" Date: Wed, 18 Oct 2023 16:39:12 +0100 Message-ID: <20231018154434.17367-5-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters. The "pmu-num" property now generates a warning when used by the user on the command line. In order to avoid warning for the default value when the property is not explicitly by the user the property default value cannot be used so the default value must be set during the CPU object initialisation. If the "pmu-num" value is changed from the default then the mask will be generated from that to support the transition to "pmu-mask". Signed-off-by: Rob Bradford --- target/riscv/cpu.c | 31 ++++++++++++++++++++++++++++++- target/riscv/cpu_cfg.h | 3 ++- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 20 ++++++++++++++++---- target/riscv/tcg/tcg-cpu.c | 2 +- 5 files changed, 50 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..1b734d1dde 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1169,6 +1169,11 @@ static void riscv_cpu_post_init(Object *obj) static void riscv_cpu_init(Object *obj) { + RISCVCPU *cpu = RISCV_CPU(obj); + + /* Using property default value would spam deprecation warning */ + cpu->cfg.pmu_num = 16; + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); @@ -1362,8 +1367,32 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { DEFINE_PROP_END_OF_LIST(), }; +static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + visit_type_uint8(v, name, &cpu->cfg.pmu_num, errp); + warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\""); +} + +static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + visit_type_uint8(v, name, &cpu->cfg.pmu_num, errp); +} + +const PropertyInfo prop_pmu_num = { + .name = "pmu-num", + .get = prop_pmu_num_get, + .set = prop_pmu_num_set, +}; + Property riscv_cpu_options[] = { - DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), + DEFINE_PROP("pmu-num", RISCVCPU, cfg.pmu_num, prop_pmu_num, uint8_t), /* Deprecated */ + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK(3, 16)), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..d273487040 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -123,7 +123,8 @@ struct RISCVCPUConfig { bool ext_xtheadsync; bool ext_XVentanaCondOps; - uint8_t pmu_num; + uint8_t pmu_num; /* Deprecated */ + uint32_t pmu_mask; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..9f6e3f7a6d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -313,7 +313,7 @@ static bool pmu_needed(void *opaque) { RISCVCPU *cpu = opaque; - return cpu->cfg.pmu_num; + return (cpu->cfg.pmu_mask > 0); } static const VMStateDescription vmstate_pmu_ctr_state = { diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 7ddf4977b1..5e89354bb9 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" @@ -184,7 +185,7 @@ int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx) CPURISCVState *env = &cpu->env; gpointer value; - if (!cpu->cfg.pmu_num) { + if (!cpu->cfg.pmu_mask) { return 0; } value = g_hash_table_lookup(cpu->pmu_event_ctr_map, @@ -434,7 +435,13 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { uint8_t pmu_num = cpu->cfg.pmu_num; - if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + if (cpu->cfg.pmu_mask & (COUNTEREN_CY | COUNTEREN_TM | COUNTEREN_IR)) { + error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); + return; + } + + if (ctpop32(cpu->cfg.pmu_mask) > (RV_MAX_MHPMCOUNTERS - 3) || + (pmu_num > RV_MAX_MHPMCOUNTERS - 3)) { error_setg(errp, "Number of counters exceeds maximum available"); return; } @@ -445,6 +452,11 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) return; } - /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs = MAKE_32BIT_MASK(3, pmu_num); + if (pmu_num == 0) { + cpu->cfg.pmu_mask = 0; + } else if (pmu_num != 16) { + cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num); + } + + cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask; } diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ed3eb991c0..53c52389b9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -613,7 +613,7 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) riscv_timer_init(cpu); } - if (cpu->cfg.pmu_num) { + if (cpu->cfg.pmu_mask) { riscv_pmu_init(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); From patchwork Wed Oct 18 15:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13427260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B99BCDB47E for ; Wed, 18 Oct 2023 15:46:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8j5-0001bA-AV; Wed, 18 Oct 2023 11:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8j3-0001aH-Dl for qemu-devel@nongnu.org; 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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:45 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , libvir-list@redhat.com (reviewer:Incompatible changes) Subject: [PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation Date: Wed, 18 Oct 2023 16:39:13 +0100 Message-ID: <20231018154434.17367-6-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=rbradford@rivosinc.com; helo=mail-lf1-x12e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This has been replaced by a "pmu-mask" property that provides much more flexibility. Signed-off-by: Rob Bradford Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- docs/about/deprecated.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 2febd2d12f..857b5d4fc4 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -405,6 +405,18 @@ Specifying the iSCSI password in plain text on the command line using the used instead, to refer to a ``--object secret...`` instance that provides a password via a file, or encrypted. +CPU device properties +''''''''''''''''''''' + +``pmu-num=n`` on RISC-V CPUs (since 8.2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In order to support more flexible counter configurations this has been replaced +by a ``pmu-mask`` property. If set of counters is continuous then the mask can +be calculated with ``((2 ^ n) - 1) << 3``. The least significant three bits +must be left clear. + + Backwards compatibility ----------------------- From patchwork Wed Oct 18 15:39:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Bradford X-Patchwork-Id: 13427261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87A65CDB47E for ; Wed, 18 Oct 2023 15:46:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qt8j5-0001bB-Ae; Wed, 18 Oct 2023 11:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qt8j4-0001az-44 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:50 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qt8j2-0004xo-Jk for qemu-devel@nongnu.org; Wed, 18 Oct 2023 11:44:49 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4083cd3917eso6464585e9.3 for ; Wed, 18 Oct 2023 08:44:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697643886; x=1698248686; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I1DBZDUvIATC8PHiuhBMUA0lfNpRPy/ZdfO4sG+Ox/Q=; b=LCg93uoElhKqlDczVfsR7Y9WA6ipaa4yluALTNH8U8Qo3e2K3VfupqBdkZZLD/KrmE Sh0z4e7GhE4upYuP87KzWSi+ejbuSIQmwb3pfYPTKZ7jB2ra2PcLZ+D6M6aTZVy94U8f LUfaxF8y9caOzKq5FKgbDnvj2Y+y2s0qgeYnDNDNgM4h/Tlts2GSW9brYLsTbr1V2bRP e2lIJa1VSALq92qSKqm+9dlARNcdlcejn4vF5Q798AJkr53B/uMOgQK8ezilv/A6EhL9 id8ahBNYB0ukVpGjExZ52Duz9xHEwkVmuN1lJc9soSJlPxs8pi5usZrbKFopG2fj0VlS Cbyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697643886; x=1698248686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I1DBZDUvIATC8PHiuhBMUA0lfNpRPy/ZdfO4sG+Ox/Q=; b=EiWX3oayI8Nr/vwuT/NNZ+j3+cAImVw+6o97nmdO6NAMZmtO2xgN3P4vtayaXXbbpy Osp5dkjtXNA/Ncep1jOjpchTJyJ3P0DEMOJJJUmISlV5R/853EoVoAPyuWoMrr3Af5tl 3iMuiCnMllza9Z8PRd2MjCKkJyGJIap8ZPEpykKu8JzYpsW6YH6T64yC7dKLWBzzlfQV nD8Cd1Qm5/KB6PKiiNnwv7sXOI4OyxA9T/aqr0/Ic7l/HxqAQHHFmVeGPpb7zcXQvajl zMXblkHnxfEgiJHk6mczufk3H2qdrj+Kuzt26FjapHgcQrocL2kFP+9JPF+bXPaZJ1jh vnbQ== X-Gm-Message-State: AOJu0YxASsdSFnhu7bW7LWlhbmcACHx6P/6PUVpq5ccq4OuDNE8dKHVI Ek1U9bPoNAq6sO+p/uRGRSLc7UiRizKXpjaG6xmbmw== X-Google-Smtp-Source: AGHT+IGZ3TyGkOX8y9PV4t89xyq22UXzh1kpPWDTC+4tElTFZMTeUtGjsTL6v5WXgXZ6kwSTstI6Lw== X-Received: by 2002:a05:600c:a686:b0:3fc:dd9:91fd with SMTP id ip6-20020a05600ca68600b003fc0dd991fdmr4230208wmb.40.1697643886661; Wed, 18 Oct 2023 08:44:46 -0700 (PDT) Received: from rockhopper.ba.rivosinc.com (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id b14-20020a05600c4e0e00b0040607da271asm1963580wmq.31.2023.10.18.08.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:44:46 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro Date: Wed, 18 Oct 2023 16:39:14 +0100 Message-ID: <20231018154434.17367-7-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018154434.17367-1-rbradford@rivosinc.com> References: <20231018154434.17367-1-rbradford@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org A 32-bit mask can be trivially created using the 64-bit macro so make use of that instead. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/pmu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 5e89354bb9..81b25ec11a 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -25,8 +25,6 @@ #include "sysemu/device_tree.h" #define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */ -#define MAKE_32BIT_MASK(shift, length) \ - (((uint32_t)(~0UL) >> (32 - (length))) << (shift)) /* * To keep it simple, any event can be mapped to any programmable counters in @@ -455,7 +453,7 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp) if (pmu_num == 0) { cpu->cfg.pmu_mask = 0; } else if (pmu_num != 16) { - cpu->cfg.pmu_mask = MAKE_32BIT_MASK(3, pmu_num); + cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, pmu_num); } cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;