From patchwork Wed Oct 18 22:34:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 13428059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D967CDB47E for ; Wed, 18 Oct 2023 22:34:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229695AbjJRWel (ORCPT ); Wed, 18 Oct 2023 18:34:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbjJRWel (ORCPT ); Wed, 18 Oct 2023 18:34:41 -0400 Received: from dellerweb.de (dellerweb.de [173.249.48.176]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E79AAB for ; Wed, 18 Oct 2023 15:34:33 -0700 (PDT) Received: from mx3210.localdomain (unknown [142.126.114.79]) by dellerweb.de (Postfix) with ESMTPSA id C641916002AE; Thu, 19 Oct 2023 00:34:28 +0200 (CEST) Received: by mx3210.localdomain (Postfix, from userid 1000) id B6DC622012C; Wed, 18 Oct 2023 22:34:14 +0000 (UTC) Date: Wed, 18 Oct 2023 22:34:14 +0000 From: John David Anglin To: linux-parisc@vger.kernel.org Cc: Helge Deller , James Bottomley Subject: [PATCH v2] parisc: Add nop instructions after TLB inserts Message-ID: MIME-Version: 1.0 Content-Disposition: inline Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org An excerpt from the PA8800 ERS states: o The PA8800 violates the seven instruction pipeline rule when performing TLB inserts or PxTLBE instructions with the PSW C bit on. The instruction will take effect by the 12th instruction after the insert or purge. I believe we have a problem with handling TLB misses. We don't fill the pipeline following TLB inserts. As a result, we likely fault again after returning from the interruption. The above statement indicates that we need at least seven instructions after the insert on pre PA8800 processors and we need 12 instructions on PA8800/PA8900 processors. Here we add macros and code to provide the required number instructions after a TLB insert. Tested on c8000. v2: Revise per Helge's suggestions. Applies to master 6.6.0-rc6. Signed-off-by: John David Anglin Suggested-by: Helge Deller diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index ae03b8679696..4a848a928238 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -36,6 +36,24 @@ .level 2.0 #endif +/* + * We need seven instructions after a TLB insert for it to take effect. + * The PA8800/PA8900 processors are an exception and need 12 instructions. + * The RFI changes both IAOQ_Back and IAOQ_Front, so it counts as one. + */ +#ifdef CONFIG_64BIT +#define NUM_INSNS 12 +#else +#define NUM_INSNS 7 +#endif + + /* Insert num nops */ + .macro insert_nops num + .rept \num + nop + .endr + .endm + /* Get aligned page_table_lock address for this mm from cr28/tr4 */ .macro get_ptl reg mfctl %cr28,\reg @@ -415,25 +433,38 @@ 3: .endm - /* Release page_table_lock without reloading lock address. - We use an ordered store to ensure all prior accesses are - performed prior to releasing the lock. */ - .macro ptl_unlock0 spc,tmp,tmp2 -#ifdef CONFIG_TLB_PTLOCK -98: ldi __ARCH_SPIN_LOCK_UNLOCKED_VAL, \tmp2 + /* Release page_table_lock if for user space. We use an ordered + store to ensure all prior accesses are performed prior to + releasing the lock. */ + .macro ptl_unlock spc,tmp,tmp2 + ldi __ARCH_SPIN_LOCK_UNLOCKED_VAL, \tmp2 or,COND(=) %r0,\spc,%r0 stw,ma \tmp2,0(\tmp) + .endm + + /* Release page_table_lock without reloading lock address. */ + .macro ptl_unlock0 spc,tmp,tmp2 +#ifdef CONFIG_TLB_PTLOCK +98: ptl_unlock \spc,\tmp,\tmp2 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) +#else + insert_nops 3 #endif + /* Insert nops so we don't return before TLB insert takes effect. */ + insert_nops NUM_INSNS - 4 .endm - /* Release page_table_lock. */ + /* Reload lock address and release page_table_lock. */ .macro ptl_unlock1 spc,tmp,tmp2 #ifdef CONFIG_TLB_PTLOCK 98: get_ptl \tmp - ptl_unlock0 \spc,\tmp,\tmp2 + ptl_unlock \spc,\tmp,\tmp2 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP) +#else + insert_nops 4 #endif + /* Insert nops so we don't return before TLB insert takes effect. */ + insert_nops NUM_INSNS - 5 .endm /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and @@ -1133,6 +1164,7 @@ dtlb_check_alias_20w: idtlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop @@ -1159,6 +1191,7 @@ nadtlb_check_alias_20w: idtlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop @@ -1194,6 +1227,7 @@ dtlb_check_alias_11: idtlba pte,(va) idtlbp prot,(va) + insert_nops NUM_INSNS - 1 rfir nop @@ -1227,6 +1261,7 @@ nadtlb_check_alias_11: idtlba pte,(va) idtlbp prot,(va) + insert_nops NUM_INSNS - 1 rfir nop @@ -1255,6 +1290,7 @@ dtlb_check_alias_20: idtlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop @@ -1283,6 +1319,7 @@ nadtlb_check_alias_20: idtlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop @@ -1352,6 +1389,7 @@ naitlb_check_alias_20w: iitlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop @@ -1411,6 +1449,7 @@ naitlb_check_alias_11: iitlba pte,(%sr0, va) iitlbp prot,(%sr0, va) + insert_nops NUM_INSNS - 1 rfir nop @@ -1460,6 +1499,7 @@ naitlb_check_alias_20: iitlbt pte,prot + insert_nops NUM_INSNS - 1 rfir nop