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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 01/11] mlxsw: reg: Drop SGCR.llb Date: Thu, 19 Oct 2023 12:27:10 +0200 Message-ID: <26e24aa08c174286ab96080fb783b066e19fc7d3.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|SN7PR12MB7812:EE_ X-MS-Office365-Filtering-Correlation-Id: 50498584-2d65-487f-7e90-08dbd08e0d51 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KHh6eAXppBTY9bvN6KexsNLwuvaw601XoCQgiYw92AOqtnwtn2bnHl5I9V7emC+tHygqmNl2Fhd8xQ13eAqrf84JZPER0blMRo9oYL6lczYUdwmUMAkT3TzPJDw2ZXM6aaIJplbLkJbJtVky8g+asT+9otDA/zKTalxEhMD4TsA2k7AOish7iI8sMoyIBgz9gbgHTtAUZp3P/70YrauaOPBDofruqfPUIqSQHZbWrmnPDSvbZBATh8FfzJGasc8z3M7gkeveGxeAVfYXxu9xpwE7DiwwVBtXFAziLAUS2dQiYUHUf77SwZ3IgVVtuXBeze0nuXbuAHbqDQ+xToDnhSNEFa9UQRRrG+MAB1dVNDKp9b/AH0teqXEpUaSNrxSK9GrWLUIlciWpvA+QpsBn371FKD7hIEU3aLFGtYRmT+phCBjfy6TvljgYUtNVZdb+BJzWRpuVKhjWLPEtMtJD1JCrqwTmagI99OFZsz95lI/sYvujakOQpbfS7BZ4AqyJ+bO32P7/PL+9KnrrmrYUPShzkuU/XIq5pHt8MtYb0uX8laKLnu9svdGt5JOZ8W4p8VAgVj57RRDnEvDuUkAtmip8fxE8+Ta3tsOPiPjC4yIew6IXlz4yUYCQkUEzKGhMtsNXXKkRxNPmEF5axuV2TeKy/cd8H+/OT3sQutk15LUT9yX2Ic9r9S4d5/B7QYHwUPO8H5sPMiyoh1s0K5+yImL3lf8hoxPj1DmPXUV9JXWzq2LX5CoutyBlttZaMWdD3S/CazaeEEsWAjUWFBg75A== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(39860400002)(376002)(396003)(230922051799003)(451199024)(82310400011)(186009)(1800799009)(64100799003)(36840700001)(46966006)(40470700004)(83380400001)(40480700001)(40460700003)(107886003)(2616005)(36756003)(86362001)(316002)(110136005)(2906002)(8936002)(54906003)(5660300002)(70206006)(41300700001)(70586007)(4326008)(8676002)(478600001)(7696005)(6666004)(426003)(336012)(7636003)(26005)(356005)(16526019)(82740400003)(47076005)(36860700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:27:52.9029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50498584-2d65-487f-7e90-08dbd08e0d51 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7812 X-Patchwork-Delegate: kuba@kernel.org SGCR, Switch General Configuration Register, has not been used since commit b0d80c013b04 ("mlxsw: Remove Mellanox SwitchX-2 ASIC support"). We will need the register again shortly, so instead of dropping it and reintroducing again, just drop the sole unused field. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index c314afd4a8ff..ba00c68211c4 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -38,18 +38,9 @@ static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); -/* reg_sgcr_llb - * Link Local Broadcast (Default=0) - * When set, all Link Local packets (224.0.0.X) will be treated as broadcast - * packets and ignore the IGMP snooping entries. - * Access: RW - */ -MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); - -static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) +static inline void mlxsw_reg_sgcr_pack(char *payload) { MLXSW_REG_ZERO(sgcr, payload); - mlxsw_reg_sgcr_llb_set(payload, !!llb); } /* SPAD - Switch Physical Address Register From patchwork Thu Oct 19 10:27:11 2023 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 02/11] mlxsw: reg: Add SGCR.lag_lookup_pgt_base Date: Thu, 19 Oct 2023 12:27:11 +0200 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB55:EE_|DS7PR12MB6263:EE_ X-MS-Office365-Filtering-Correlation-Id: 0522c61c-f55a-4497-bb5e-08dbd08e0ee4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AtGWRzIhdMqLN7QOpx4g3ScymBLsg5+fb0ISu8/z3f9CQABTwew1P7iKpyxVom68y8Xpm4icWX+8OjIwKdmpXdr0/olr2QxlRiFocEr7tjwOFWEVsOqNCaFGMhJbdKJW8kqg1ps+QK6r5BBV2gc9/Tc5cc0w9KDa/Xs2EovE6AvirdmOWGZ6bOIG8zddGUYcq7mrNNYQtPu1LyCr5G7ANuXY/osH2wFjqixPoL4Bfb/7jQHeFMx1s2MdFSjydkS0ZHe+46G9cfek3aW0CsZkzbXS/z8bj2GxUYFoc2w22NGIQVZ+uADYpWy/58PJ2VUIKnxYEbJ4VSUYYw4vdsfxLBZ6T0sYrTNNmiXyOvhKy5u0c8otMypvAXkuhE2KQk8XpdopDce5L4RlMDHhiM5qDATqJYHxFc51XVk7EtMpHmzCSTxTQ4T8gZlmEmJqxmBm8+MXxAcrrupDw8saI1lw6HXVNqVR4jID5quR39OYTbaiNaTyeeDmK+iBzwxywDL19k/jvNc5jHmi4VwKU5c28KdfoKvnx8pcxqUWC3/zWepRfjKkrfiMFTVWWRpGr0ftoguso6fqkTF5Kzdftatt4LWKj6CGJUrjtFC5kV75GxwuO4aSH+OK3zHd+wsEgLA3tMD6jgIDpoikGODk91m101NzyUhD4RPB6YyH70itI9N/uNUCSlmRNQzFKNC2NqQGd0Kajf3rmCXPEkG2BL89lE19DQpmTigaXdfdDZfRH84= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(39860400002)(396003)(346002)(230922051799003)(64100799003)(1800799009)(82310400011)(186009)(451199024)(40470700004)(46966006)(36840700001)(316002)(82740400003)(107886003)(2616005)(70206006)(70586007)(478600001)(110136005)(426003)(2906002)(54906003)(7696005)(16526019)(8676002)(5660300002)(4326008)(41300700001)(26005)(8936002)(86362001)(47076005)(36756003)(83380400001)(7636003)(36860700001)(6666004)(356005)(336012)(40460700003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:27:55.4674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0522c61c-f55a-4497-bb5e-08dbd08e0ee4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6263 X-Patchwork-Delegate: kuba@kernel.org Add SGCR.lag_lookup_pgt_base, which is used for configuring the base address of the LAG table within the PGT table for cases when the driver is responsible for the table placement. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/reg.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index ba00c68211c4..e26e9d06bd72 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -38,9 +38,18 @@ static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); -static inline void mlxsw_reg_sgcr_pack(char *payload) +/* reg_sgcr_lag_lookup_pgt_base + * Base address used for lookup in PGT table + * Supported when CONFIG_PROFILE.lag_mode = 1 + * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries. + * Access: RW + */ +MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16); + +static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base) { MLXSW_REG_ZERO(sgcr, payload); + mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 03/11] mlxsw: cmd: Fix omissions in CONFIG_PROFILE field names in comments Date: Thu, 19 Oct 2023 12:27:12 +0200 Message-ID: <6611b1d9c57087c80383f309c4c0e5f1ee663e6f.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|CH3PR12MB9121:EE_ X-MS-Office365-Filtering-Correlation-Id: 67ea87c3-baf6-422d-b9d1-08dbd08e1086 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bg7YCuZvcODm1QpWlo43Oo9Vrdp35vOxZ3AUOtbdwLfq5IF8wVhmIzuMblaEOJFlwHWLbqmApvMwfWbFK+yC7Fl/N1284y7SUHSuqvJ22w+mWxgYrs0JgyofJmJaq6jz4MXRHCTIxBgHJNoWl81Z/MxTiMZgUJeMOznW6ybi95mJzdweq+o6tU3bP1oYDX8Dyf176uzLUnmJpRn6+IhrRkKP6laS129ZzvFcPvbm6HD4Gh+d01rNbQhqoTraDbtXv+xxRza51ptWAa6JAcHMIVOJow29N4//VPfw+2qdq4CsZQA09k1aGk/qyPwrX4lHemYUbL8jwl+24F3qmbSOPkpeklMAzS5tjjTTKmYyX+dXkuVRxz5CJjYHLPaE44D7La3CDWpBv5A7UFRYFxsDnP3ipL9D/NiwqqbwIMqYIuSdbtthdgrotE88L+wsiiNY1nf2HJaQdI3WPgVDcgOC5I0w3IFdyveYBzzwuUv6PdBQUoT6fq3fkLhuhHfIedwWLMGG23xaO/1M7FsHoKbJQy19RsIAwHtTUzU8Jy/m7f4XtqFQF5wmah1SiJeoE2NG0PPvEFLQ0eHjv+0Olq8HbNbNPShADeJYy0PvZsb2nnaCVI6fdRys8zoC8dwQAYILA3gYHKs0RZW2jeZ9IivqbSruyTQSAzoTXl5YB02UUdVaXI3LuktNOLi+VX8nkU4oqUQlf+DU+1pQ12100aR7L+K/tC00NKMJpHCo0ARyMH3Bu4iiseR09l5Ui6uyneLi X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(376002)(396003)(230922051799003)(64100799003)(82310400011)(451199024)(1800799009)(186009)(36840700001)(46966006)(40470700004)(47076005)(70206006)(40460700003)(36860700001)(70586007)(6666004)(83380400001)(16526019)(478600001)(7696005)(26005)(356005)(41300700001)(316002)(7636003)(54906003)(110136005)(2616005)(4326008)(8676002)(8936002)(107886003)(5660300002)(40480700001)(86362001)(2906002)(82740400003)(336012)(36756003)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:27:58.2224 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67ea87c3-baf6-422d-b9d1-08dbd08e1086 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9121 X-Patchwork-Delegate: kuba@kernel.org A number of CONFIG_PROFILE fields' comments refer to a field named like cmd_mbox_config_* instead of cmd_mbox_config_profile_*. Correct these omissions. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/cmd.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h index 09bef04b11d1..a181ca4b764e 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h +++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h @@ -659,37 +659,37 @@ MLXSW_ITEM32(cmd_mbox, config_profile, */ MLXSW_ITEM32(cmd_mbox, config_profile, set_ar_sec, 0x0C, 15, 1); -/* cmd_mbox_config_set_ubridge +/* cmd_mbox_config_profile_set_ubridge * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ MLXSW_ITEM32(cmd_mbox, config_profile, set_ubridge, 0x0C, 22, 1); -/* cmd_mbox_config_set_kvd_linear_size +/* cmd_mbox_config_profile_set_kvd_linear_size * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_linear_size, 0x0C, 24, 1); -/* cmd_mbox_config_set_kvd_hash_single_size +/* cmd_mbox_config_profile_set_kvd_hash_single_size * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_single_size, 0x0C, 25, 1); -/* cmd_mbox_config_set_kvd_hash_double_size +/* cmd_mbox_config_profile_set_kvd_hash_double_size * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ MLXSW_ITEM32(cmd_mbox, config_profile, set_kvd_hash_double_size, 0x0C, 26, 1); -/* cmd_mbox_config_set_cqe_version +/* cmd_mbox_config_profile_set_cqe_version * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); -/* cmd_mbox_config_set_cqe_time_stamp_type +/* cmd_mbox_config_profile_set_cqe_time_stamp_type * Capability bit. Setting a bit to 1 configures the profile * according to the mailbox contents. */ @@ -847,7 +847,7 @@ MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1); */ MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); -/* cmd_mbox_config_kvd_hash_single_size +/* cmd_mbox_config_profile_kvd_hash_single_size * KVD Hash single-entries size * Valid for Spectrum only * Allowed values are 128*N where N=0 or higher @@ -856,7 +856,7 @@ MLXSW_ITEM32(cmd_mbox, config_profile, kvd_linear_size, 0x54, 0, 24); */ MLXSW_ITEM32(cmd_mbox, config_profile, kvd_hash_single_size, 0x58, 0, 24); -/* cmd_mbox_config_kvd_hash_double_size +/* cmd_mbox_config_profile_kvd_hash_double_size * KVD Hash double-entries size (units of single-size entries) * Valid for Spectrum only * Allowed values are 128*N where N=0 or higher From patchwork Thu Oct 19 10:27:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13428578 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3F6E18B1B for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 04/11] mlxsw: cmd: Add CONFIG_PROFILE.{set_, }lag_mode Date: Thu, 19 Oct 2023 12:27:13 +0200 Message-ID: <1f60d9697693fbf7ab886aeca2dea678178f6e6e.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|SJ2PR12MB9006:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e77521c-ac71-4531-517b-08dbd08e1355 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tmOxCQhSOdqspoP2/l9JPJfj4asWoa4G2vXw48Jc2uiMZO2ttSSPogdOqdL+8CzmVmDI7wr83EDFXIde2Ns7ITyeXndN/1dPv2RhcscoQr57g8pJ3FN0cEhYgbyDwV/NR5deurNXswu8f9ZR2i20p60+xN2QYdUt5u7gGD1SzGZ6lotxI1CFqu6D1bjVfOZ1OyiWkBwP/CMq5KRrVPl1GRcla2FarpIPDgNcRWkbR1U5NZq9jdTvpT17cLoCIUiHle6f8iZ23URUHeE5KxV5N9dVF1ZfwArnOYFZxhDwOX42WlXgtToP/10KNehqLgJLFu3T62OupEGTRmD8Hp1XlUgI9Y/im8R9FaCUXf8kMxOF9dzhFWFtNXcWq4bb422IwQZ12Hjng09oPj6+4bSTZBu27ThinD+0rj4exAD+tHgwrq5N2fssb2zC4cu8I3tFFGutHqo9TwDhP87pywAXph7NzMu3afKFsNOyTeMD8iDQIztC/9vQPvO/riF3EsIXQ0ejPlkae46qK7R7le4FfMjdofrHiwlQdvgWPFLBlvR2wWf0Szx4Ps/GjftO9nDH82I1DqFXlFZhVThwHo5Mgbg6exwJ7vd7jwE4NPbOc5rr+6KpHoy0cQ8lMuCmcxBPK3zn22N46nU224HLiDLWDTcJMCXEX/pudH0Is2+XTb3OdyLUrfXrbylo3D/G+f6fSqznLBqF5LGzDvrIqFVUlnFuu/bxqOztpRAVsL54bYtFQ505NzOXQ1/8oTRDlxUZ X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(376002)(136003)(230922051799003)(64100799003)(186009)(451199024)(1800799009)(82310400011)(46966006)(40470700004)(36840700001)(47076005)(26005)(110136005)(2616005)(16526019)(426003)(82740400003)(36860700001)(336012)(40480700001)(70206006)(54906003)(7696005)(36756003)(316002)(83380400001)(7636003)(107886003)(356005)(86362001)(70586007)(478600001)(40460700003)(6666004)(2906002)(5660300002)(8936002)(4326008)(41300700001)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:02.9942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e77521c-ac71-4531-517b-08dbd08e1355 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9006 X-Patchwork-Delegate: kuba@kernel.org Add CONFIG_PROFILE.lag_mode, which serves for moving responsibility for placement of the LAG table from FW to SW. Whether lag_mode should be configured is determined by CONFIG_PROFILE.set_lag_mode, which also add. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/cmd.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h index a181ca4b764e..cb6e2a9ef03f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h +++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h @@ -695,6 +695,12 @@ MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_version, 0x08, 0, 1); */ MLXSW_ITEM32(cmd_mbox, config_profile, set_cqe_time_stamp_type, 0x08, 2, 1); +/* cmd_mbox_config_profile_set_lag_mode + * Capability bit. Setting a bit to 1 configures the lag_mode + * according to the mailbox contents. + */ +MLXSW_ITEM32(cmd_mbox, config_profile, set_lag_mode, 0x08, 7, 1); + /* cmd_mbox_config_profile_max_vepa_channels * Maximum number of VEPA channels per port (0 through 16) * 0 - multi-channel VEPA is disabled @@ -840,6 +846,21 @@ MLXSW_ITEM32(cmd_mbox, config_profile, arn, 0x50, 31, 1); */ MLXSW_ITEM32(cmd_mbox, config_profile, ubridge, 0x50, 4, 1); +enum mlxsw_cmd_mbox_config_profile_lag_mode { + /* FW manages PGT LAG table */ + MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW, + /* SW manages PGT LAG table */ + MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW, +}; + +/* cmd_mbox_config_profile_lag_mode + * LAG mode + * Configured if set_lag_mode is set + * Supported from Spectrum-2 and above. + * Supported only when ubridge = 1 + */ +MLXSW_ITEM32(cmd_mbox, config_profile, lag_mode, 0x50, 3, 1); + /* cmd_mbox_config_kvd_linear_size * KVD Linear Size * Valid for Spectrum only From patchwork Thu Oct 19 10:27:14 2023 Content-Type: text/plain; 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Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/cmd.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h index cb6e2a9ef03f..e827c78be114 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h +++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h @@ -276,6 +276,12 @@ MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8); */ MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8); +/* cmd_mbox_query_fw_lag_mode_support + * 0: CONFIG_PROFILE.lag_mode is not supported by FW + * 1: CONFIG_PROFILE.lag_mode is supported by FW + */ +MLXSW_ITEM32(cmd_mbox, query_fw, lag_mode_support, 0x18, 1, 1); + /* cmd_mbox_query_fw_clr_int_base_offset * Clear Interrupt register's offset from clr_int_bar register * in PCI address space. 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The bus module determines whether LAG is supported, can configure it if it is, and knows what (if any) configuration has been applied. Therefore add a bus callback to determine the configured LAG mode. Also add to core an API to query it. The LAG mode is for now kept at the default value of 0 for FW-managed. The code to actually toggle it will be added later. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/core.c | 7 +++++++ drivers/net/ethernet/mellanox/mlxsw/core.h | 3 +++ drivers/net/ethernet/mellanox/mlxsw/pci.c | 14 ++++++++++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index 1ccf3b73ed72..67032b93fba9 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -204,6 +204,13 @@ int mlxsw_core_max_lag(struct mlxsw_core *mlxsw_core, u16 *p_max_lag) } EXPORT_SYMBOL(mlxsw_core_max_lag); +enum mlxsw_cmd_mbox_config_profile_lag_mode +mlxsw_core_lag_mode(struct mlxsw_core *mlxsw_core) +{ + return mlxsw_core->bus->lag_mode(mlxsw_core->bus_priv); +} +EXPORT_SYMBOL(mlxsw_core_lag_mode); + void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core) { return mlxsw_core->driver_priv; diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h index c6bc5819ce43..5692f34b2a63 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core.h @@ -36,6 +36,8 @@ struct mlxsw_fw_rev; unsigned int mlxsw_core_max_ports(const struct mlxsw_core *mlxsw_core); int mlxsw_core_max_lag(struct mlxsw_core *mlxsw_core, u16 *p_max_lag); +enum mlxsw_cmd_mbox_config_profile_lag_mode +mlxsw_core_lag_mode(struct mlxsw_core *mlxsw_core); void *mlxsw_core_driver_priv(struct mlxsw_core *mlxsw_core); @@ -485,6 +487,7 @@ struct mlxsw_bus { u32 (*read_frc_l)(void *bus_priv); u32 (*read_utc_sec)(void *bus_priv); u32 (*read_utc_nsec)(void *bus_priv); + enum mlxsw_cmd_mbox_config_profile_lag_mode (*lag_mode)(void *bus_priv); u8 features; }; diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 8de953902918..3e8347585e42 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -105,6 +105,8 @@ struct mlxsw_pci { u64 free_running_clock_offset; u64 utc_sec_offset; u64 utc_nsec_offset; + bool lag_mode_support; + enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode; struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT]; u32 doorbell_offset; struct mlxsw_core *core; @@ -1313,6 +1315,7 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, profile->cqe_time_stamp_type); } + mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW; return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); } @@ -1640,6 +1643,8 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, mlxsw_pci->utc_nsec_offset = mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox); + mlxsw_pci->lag_mode_support = + mlxsw_cmd_mbox_query_fw_lag_mode_support_get(mbox); num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox); err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages); if (err) @@ -1949,6 +1954,14 @@ static u32 mlxsw_pci_read_utc_nsec(void *bus_priv) return mlxsw_pci_read32_off(mlxsw_pci, mlxsw_pci->utc_nsec_offset); } +static enum mlxsw_cmd_mbox_config_profile_lag_mode +mlxsw_pci_lag_mode(void *bus_priv) +{ + struct mlxsw_pci *mlxsw_pci = bus_priv; + + return mlxsw_pci->lag_mode; +} + static const struct mlxsw_bus mlxsw_pci_bus = { .kind = "pci", .init = mlxsw_pci_init, @@ -1960,6 +1973,7 @@ static const struct mlxsw_bus mlxsw_pci_bus = { .read_frc_l = mlxsw_pci_read_frc_l, .read_utc_sec = mlxsw_pci_read_utc_sec, .read_utc_nsec = mlxsw_pci_read_utc_nsec, + .lag_mode = mlxsw_pci_lag_mode, .features = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET, }; From patchwork Thu Oct 19 10:27:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13428580 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2572199A8 for ; Thu, 19 Oct 2023 10:28:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="PIdCqBr+" Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2077.outbound.protection.outlook.com [40.107.223.77]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67665119 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 07/11] mlxsw: pci: Permit toggling LAG mode Date: Thu, 19 Oct 2023 12:27:16 +0200 Message-ID: <8ecead4979d95abbbfc69be4e80c0514fdbc024f.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|BY5PR12MB4051:EE_ X-MS-Office365-Filtering-Correlation-Id: 83caee40-b94e-4cb2-1447-08dbd08e1876 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: noSwqgYEqxN1YMEbaBD+ID/fNkPcaTx7Xm5mGUFzJ+w2fZ6oMNvWsGVlcY2oRXimA5VWQX0Pwciz8NIGU3PS7iQSceqorcSlSm5YyAYIq89cnX+yF3AgWG7Yj55L01o3lXfIE2lwrIgi5ZBt4KC/bl5GN7LzjrjJkjt0/YxSoVjggBR2wxPTp8xZfEEp82ssGBlrzQ/xsVFoKSP0zlE6MCSEIBMPjvMwykLcC+hrlKDSV8WHTteLFGA0wdPm8Aw91Bp2E0RIUOE76DJkouPOYHIRsKTXo7Uj78SFq2F56kOrBB6PS6cx5FaceODMWnHqiUNPSIKc7Pe5R6a5ChwV6+ACG5mXKgXey0fMgAxSJ/ETGFX7p1gCC3/JtDvmZwuhS3k5YYmDugjEvTBfjpr4wnudy0L/3C9B5p0+/UffhZRAsD4gY6NP+cZvsxZ7mDAwXtrKU+ClUTK709lMlYUTKr3BVn85rQFWke7VB7cPcVQFmjKiET0xt47/22lzCFo/A2CWh/+QdEjq31hdegQ8vwXfku2Y567reCc/VSKskgoGZZgTzLpvcNWsl/bEZA+cbj3nV5kQYdSGoTYyeXgfblFKoNq191XOqF9y0T4Jgehz2OVKEbtfPcmqUSyDKV/i3/h20JYtlI8MxdbeVIOz7MJWHq1nXMuOmKX/rKuCRRSkY0hisZ7N5+L+Q72OSm4KDSYI5T6gyJrcnTzogiOC6PETvaABap91FDYpyvCiPp0ZXR8npWKGgB+tkTYnt66E X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(136003)(39860400002)(376002)(346002)(230922051799003)(82310400011)(64100799003)(1800799009)(451199024)(186009)(40470700004)(46966006)(36840700001)(54906003)(6666004)(110136005)(107886003)(5660300002)(26005)(336012)(16526019)(426003)(8676002)(70586007)(2616005)(8936002)(316002)(7696005)(41300700001)(83380400001)(2906002)(356005)(36860700001)(4326008)(70206006)(7636003)(478600001)(47076005)(82740400003)(86362001)(40460700003)(36756003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:11.5350 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83caee40-b94e-4cb2-1447-08dbd08e1876 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4051 X-Patchwork-Delegate: kuba@kernel.org Add to struct mlxsw_config_profile a field lag_mode_prefer_sw for the driver to indicate that SW LAG mode should be configured if possible. Add to the PCI module code to set lag_mode as appropriate. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/core.h | 1 + drivers/net/ethernet/mellanox/mlxsw/pci.c | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.h b/drivers/net/ethernet/mellanox/mlxsw/core.h index 5692f34b2a63..764d14bd5bc0 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.h +++ b/drivers/net/ethernet/mellanox/mlxsw/core.h @@ -337,6 +337,7 @@ struct mlxsw_config_profile { u8 kvd_hash_single_parts; u8 kvd_hash_double_parts; u8 cqe_time_stamp_type; + bool lag_mode_prefer_sw; struct mlxsw_swid_config swid_config[MLXSW_CONFIG_PROFILE_SWID_COUNT]; }; diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 3e8347585e42..5b1f2483a3cc 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1315,7 +1315,16 @@ static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox, profile->cqe_time_stamp_type); } - mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW; + if (profile->lag_mode_prefer_sw && mlxsw_pci->lag_mode_support) { + enum mlxsw_cmd_mbox_config_profile_lag_mode lag_mode = + MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW; + + mlxsw_cmd_mbox_config_profile_set_lag_mode_set(mbox, 1); + mlxsw_cmd_mbox_config_profile_lag_mode_set(mbox, lag_mode); + mlxsw_pci->lag_mode = lag_mode; + } else { + mlxsw_pci->lag_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_FW; + } return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox); } @@ -1677,9 +1686,8 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, if (err) goto err_config_profile; - /* Some resources depend on unified bridge model, which is configured - * as part of config_profile. Query the resources again to get correct - * values. + /* Some resources depend on details of config_profile, such as unified + * bridge model. Query the resources again to get correct values. */ err = mlxsw_core_resources_query(mlxsw_core, mbox, res); if (err) From patchwork Thu Oct 19 10:27:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13428583 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8494718AFB for ; Thu, 19 Oct 2023 10:28:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="MTpqBD2i" Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2062.outbound.protection.outlook.com [40.107.92.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF13E12A for ; Thu, 19 Oct 2023 03:28:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=a96LGuMauHx1XGSFPJfEGiJy7Dk5QyENCU01+xl8XDtW4fbzLyvoVHwaHiSNVNGccuWVhIuKaG64a2x3S5MPU+OPqTsioCrYBigdyp1X/IRoVb0FPmaGHaEUL3/9rT7gGzSga+U9xflu6xbLpDyNGiBSMAuVtIxDtMTE3w5HLVFH3I9XdxyrfldUgegjHn2UUw9ywjWqBzkDCehyrNx5nJB65N0dECBsHxrIgb69aC7RLSGMlgDLuuKuRYJZUAqaexrpztPTGh7k9zZKsTDfs1iOs39Lq1B9ctSBVVZxQfDaejKHaQvQcbJOldwmfz/MNr9pOvdoAO9cA56Uu/rU5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=W3Te5DtNGR1ydOeaPMBsy8xdzAAOieRfJJ7hOTm6+LI=; b=dV2cMphuBrAcSNY+shT6Scg9/ISB+ACqBtJVs2DySc8rq4VlycAkxYIioNQssdebSSfCT9aRXI+P4lyxpS8CQf4xd/ORkMeREAeAWEzGTd7YaBn0Fph+38PsklY1WknmkHTnCSalDqngp3uI5NvBjSd+GHSTlped3XWmrJwv22Jhg+ONf3auyTvNZBX1YZLWNYch+0H/fO0VklWRE0NmAawoATijAy84wRcOx4JTanqXcSltkOylrFvYkDZF60oJsAkwT6iZ2OhQ/iY4d0sK6OJ3sBdrH1bPw+t0+21ZKnIbvGJzuVehCzq4mhUUN1mg9/5rovH0eHvLt30Q7zVQkA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=davemloft.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W3Te5DtNGR1ydOeaPMBsy8xdzAAOieRfJJ7hOTm6+LI=; b=MTpqBD2iL48aZ9wY1xiZbi5NtLDfd2NwF10ZAqJ1ymX90uHBAmGxWLTmx1Phu3h/qd7hG7EgnsWZq5Mxc/5GXcco/6j2K0Iy92Ne3CHYB2LuoXgVIMA4DgapCT0OQlUynKS/SQ7BWnAracALdDKNWYfx7kOL/e5XIlk69f1hzvIa1MwblfFpfBRVZNVRzhSl5uRa0G3KH5tqoSbY6nstvmTp++Y5ZVKlAl/4ZIgUtqBqs7kv2/W72J2hpWSOnFOskjw1vSlRa6EhRc2DCNnxBcsj4hRzjPOGE6tVnPhoxKSBCK6u3PoGBtwzmaB6ZoScrAUH7LplGnRBy5HM6yDIAg== Received: from MN2PR20CA0008.namprd20.prod.outlook.com (2603:10b6:208:e8::21) by IA1PR12MB6211.namprd12.prod.outlook.com (2603:10b6:208:3e5::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.23; Thu, 19 Oct 2023 10:28:14 +0000 Received: from BL6PEPF0001AB55.namprd02.prod.outlook.com (2603:10b6:208:e8:cafe::80) by MN2PR20CA0008.outlook.office365.com (2603:10b6:208:e8::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.23 via Frontend Transport; Thu, 19 Oct 2023 10:28:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB55.mail.protection.outlook.com (10.167.241.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Thu, 19 Oct 2023 10:28:14 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 19 Oct 2023 03:27:57 -0700 Received: from yaviefel.vdiclient.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 19 Oct 2023 03:27:55 -0700 From: Petr Machata To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 08/11] mlxsw: spectrum_fid: Allocate PGT for the whole FID family in one go Date: Thu, 19 Oct 2023 12:27:17 +0200 Message-ID: <3b8a3df3ec6a31bf3d7cf808defd4b50fe4fb824.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB55:EE_|IA1PR12MB6211:EE_ X-MS-Office365-Filtering-Correlation-Id: 8e4c0f2e-614a-4798-a640-08dbd08e1a3c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: E2+fC6ZITTSl7Upd4qkSAjhBB+/kTKcpJfnnFvj6IsKyyCm16yyLf5djh+LoR9SfD0d7vehhSd358R04gRw89N73OhLjJKpWidTuRi19S/Phl+D5rFZqI9aiAatsC/i+9AlByrpNJ60xh+OI/80phxBoooKwnOv6kl70r2NUNNQvWujLFnaK7drL51SfCMCXtjB/FH3+v8vJBvVonqbIcocOHc+XNZlPf+NIO+H5D8pj01+iaz/6mcg57kcrseP4O9NyWf0DD5HDGFEuohw82xCg/9IDg99ixFc2vahSgdTbDh766vQwC7+jiCBF9CtzoK9LGdpr2Cs/kVMuXwKzMm7RZpNPOld+GNfIsifr3EjYtFcy9+NBHswEBOeyamPRzsSEs2ZUjwwqSLH1l+PviNanjUyMzZg+c8m/CpGFVgrmZhV54E66MsNfXTjZST8j2G47VdvJSsb/NN7ERZ6tSm7Z28V0j+B0dSqq6i7H7yJRO8XFzQDca+9h0uU+vNF58BxVo7Ht38r0I2mDMvOeCrTSfjxWdfWfkl1RoowN4rDVwqxZHWQ7DeV0gXQ08Y1yseGPGpazM8e3bFxurN0DiOPJBvJN4Af1wf+KvIBDjw9VFjxi0SMfMVtadCauX1BFZepG+VPNrMSg1fgiiC2qwagJiWJKgbv/nvwRVA3MDz5WlD2QAewDV8P5vt8xkXh9wfy92OU8qYZcnxgDEAalmlQ/hs81o6sg8LxU4cW1vrpqK4GC5eNdSryLsr0SY5yN X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(396003)(376002)(230922051799003)(451199024)(82310400011)(64100799003)(186009)(1800799009)(40470700004)(46966006)(36840700001)(54906003)(316002)(70586007)(70206006)(41300700001)(40480700001)(8936002)(8676002)(4326008)(5660300002)(6666004)(7696005)(110136005)(40460700003)(478600001)(2906002)(36860700001)(47076005)(83380400001)(7636003)(336012)(86362001)(356005)(26005)(16526019)(2616005)(107886003)(426003)(36756003)(82740400003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:14.4985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e4c0f2e-614a-4798-a640-08dbd08e1a3c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB55.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6211 X-Patchwork-Delegate: kuba@kernel.org PGT blocks are allocated through the function mlxsw_sp_pgt_mid_alloc_range(). The interface assumes that the caller knows which piece of PGT exactly they want to get. That was fine while the FID code was the only client allocating blocks of PGT. However for SW-allocated LAG table, there will be an additional client: mlxsw_sp_lag_init(). The interface should therefore be changed to not require particular coordinates, but to take just the requested size, allocate the block wherever, and give back the PGT address. The current FID mode has one place where PGT address can be stored: the FID family's pgt_base. The allocation scheme should therefore be changed from allocating a block per FID flood table, to allocating a block per FID family. Do just that in this patch. The per-family allocation is going to be useful for another related feature as well: the CFF mode. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- .../ethernet/mellanox/mlxsw/spectrum_fid.c | 63 ++++++++++--------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c index 9df098474743..4d0b72fbfebe 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c @@ -320,6 +320,14 @@ mlxsw_sp_fid_family_num_fids(const struct mlxsw_sp_fid_family *fid_family) return fid_family->end_index - fid_family->start_index + 1; } +static u16 +mlxsw_sp_fid_family_pgt_size(const struct mlxsw_sp_fid_family *fid_family) +{ + u16 num_fids = mlxsw_sp_fid_family_num_fids(fid_family); + + return num_fids * fid_family->nr_flood_tables; +} + static u16 mlxsw_sp_fid_flood_table_mid(const struct mlxsw_sp_fid_family *fid_family, const struct mlxsw_sp_flood_table *flood_table, @@ -1654,14 +1662,10 @@ mlxsw_sp_fid_flood_table_init(struct mlxsw_sp_fid_family *fid_family, enum mlxsw_sp_flood_type packet_type = flood_table->packet_type; struct mlxsw_sp *mlxsw_sp = fid_family->mlxsw_sp; const int *sfgc_packet_types; - u16 num_fids, mid_base; + u16 mid_base; int err, i; mid_base = mlxsw_sp_fid_flood_table_mid(fid_family, flood_table, 0); - num_fids = mlxsw_sp_fid_family_num_fids(fid_family); - err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, mid_base, num_fids); - if (err) - return err; sfgc_packet_types = mlxsw_sp_packet_type_sfgc_types[packet_type]; for (i = 0; i < MLXSW_REG_SFGC_TYPE_MAX; i++) { @@ -1675,57 +1679,56 @@ mlxsw_sp_fid_flood_table_init(struct mlxsw_sp_fid_family *fid_family, err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfgc), sfgc_pl); if (err) - goto err_reg_write; + return err; } return 0; - -err_reg_write: - mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mid_base, num_fids); - return err; -} - -static void -mlxsw_sp_fid_flood_table_fini(struct mlxsw_sp_fid_family *fid_family, - const struct mlxsw_sp_flood_table *flood_table) -{ - struct mlxsw_sp *mlxsw_sp = fid_family->mlxsw_sp; - u16 num_fids, mid_base; - - mid_base = mlxsw_sp_fid_flood_table_mid(fid_family, flood_table, 0); - num_fids = mlxsw_sp_fid_family_num_fids(fid_family); - mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mid_base, num_fids); } static int mlxsw_sp_fid_flood_tables_init(struct mlxsw_sp_fid_family *fid_family) { + struct mlxsw_sp *mlxsw_sp = fid_family->mlxsw_sp; + u16 pgt_size; + int err; int i; + if (!fid_family->nr_flood_tables) + return 0; + + pgt_size = mlxsw_sp_fid_family_pgt_size(fid_family); + err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, fid_family->pgt_base, + pgt_size); + if (err) + return err; + for (i = 0; i < fid_family->nr_flood_tables; i++) { const struct mlxsw_sp_flood_table *flood_table; - int err; flood_table = &fid_family->flood_tables[i]; err = mlxsw_sp_fid_flood_table_init(fid_family, flood_table); if (err) - return err; + goto err_flood_table_init; } return 0; + +err_flood_table_init: + mlxsw_sp_pgt_mid_free_range(mlxsw_sp, fid_family->pgt_base, pgt_size); + return err; } static void mlxsw_sp_fid_flood_tables_fini(struct mlxsw_sp_fid_family *fid_family) { - int i; + struct mlxsw_sp *mlxsw_sp = fid_family->mlxsw_sp; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 09/11] mlxsw: spectrum_pgt: Generalize PGT allocation Date: Thu, 19 Oct 2023 12:27:18 +0200 Message-ID: <8d5298af7ccea1c2dc357eb288048f2cca63a3fa.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|PH7PR12MB7454:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f81c745-18de-41fa-0045-08dbd08e191b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zeoc9pWDHNPXsoCSiRFwVpxaLAdDtl6+i6UjRwmNS0i+jVnWdzDmiUZlweh4Lr9BBGQVOXfevuYVw/5aUDiDiQNL4Qr4mlFvwvQrrFFUU86Wgg06l5EzjriwC5SkNSCAEvhOVcDSNMZ+jJiZzm2bnBL2ZcWwL4vCgiaWa5JY6s1b1LY+OMksWB2nZmV3Ca4tomaYy7szelZ/2fo73Jl+tIGlv2/o0nx98TXl9cq0JRfGo11OA9EXSWpzRXknC1Tvnzu0TnVIk/O4p+f0/80957BNypqrl1u/mfTx3ziWmwcAsjrpHbB+WtkUPrzm+R3URkHVR0hMCkkW0rHuYRxKLwiIxkX+VZ/2PI5ZVN6tzm+NoYCQdadZCXAGmb9fM7JfTNOxh9BPoXjbE94IHXeZlNclwmeJQg+vKOy/vMjkw4vWq6ISFphdBWANZzYFZs77GNTg48QLnau4pVRAn8NDMq0lR2BIWdb23ZMmmWh7iDMzJa+0+5ClWzH+BoWc/25pVh0+3F48v0XjSiqf68VkRcCepcOs0OPnC1RUNDYRENSbgJg/BW4Rl5vhzUEEziCvQsl/YNWUpX30MmCrklTCQ6RwdWBUBlU7LTdgIbBKhAz/Y1cgQlhVaypb2cmHqnXtFSJjAuyCo6E9F/0aROwDIduNy2cCB+MKE+Lufph0pUWgX9AgAM+YvdsLy5IpzqfhmEBxUTmcpz/z6t6In4f1ABEpyJnaxmcBfyEXJ0ckUnL1iZxbDgI51sBE32gYzOLL X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(346002)(39860400002)(136003)(230922051799003)(451199024)(1800799009)(82310400011)(64100799003)(186009)(46966006)(40470700004)(36840700001)(40480700001)(40460700003)(41300700001)(36756003)(26005)(2906002)(336012)(2616005)(426003)(86362001)(4326008)(8676002)(8936002)(107886003)(16526019)(36860700001)(82740400003)(356005)(83380400001)(7636003)(47076005)(7696005)(6666004)(5660300002)(316002)(478600001)(110136005)(70586007)(70206006)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:12.6627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f81c745-18de-41fa-0045-08dbd08e191b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7454 X-Patchwork-Delegate: kuba@kernel.org PGT blocks are allocated through the function mlxsw_sp_pgt_mid_alloc_range(). The interface assumes that the caller knows which piece of PGT exactly they want to get. That was fine while the FID code was the only client allocating blocks of PGT. However for SW-allocated LAG table, there will be an additional client: mlxsw_sp_lag_init(). The interface should therefore be changed to not require particular coordinates, but to take just the requested size, allocate the block wherever, and give back the PGT address. In this patch, change the interface accordingly. Initialize FID family's pgt_base from the result of the PGT allocation (note that mlxsw makes a copy of the family structure, so what gets initialized is not actually the global structure). Drop the now-unnecessary pgt_base initializations and the corresponding defines. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- .../net/ethernet/mellanox/mlxsw/spectrum.h | 2 +- .../ethernet/mellanox/mlxsw/spectrum_fid.c | 8 +------- .../ethernet/mellanox/mlxsw/spectrum_pgt.c | 20 +++++-------------- 3 files changed, 7 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h index 02ca2871b6f9..ac9d03937f4b 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -1480,7 +1480,7 @@ int mlxsw_sp_policer_resources_register(struct mlxsw_core *mlxsw_core); /* spectrum_pgt.c */ int mlxsw_sp_pgt_mid_alloc(struct mlxsw_sp *mlxsw_sp, u16 *p_mid); void mlxsw_sp_pgt_mid_free(struct mlxsw_sp *mlxsw_sp, u16 mid_base); -int mlxsw_sp_pgt_mid_alloc_range(struct mlxsw_sp *mlxsw_sp, u16 mid_base, +int mlxsw_sp_pgt_mid_alloc_range(struct mlxsw_sp *mlxsw_sp, u16 *mid_base, u16 count); void mlxsw_sp_pgt_mid_free_range(struct mlxsw_sp *mlxsw_sp, u16 mid_base, u16 count); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c index 4d0b72fbfebe..e954b8cd2ee8 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_fid.c @@ -1076,8 +1076,6 @@ static const struct mlxsw_sp_fid_ops mlxsw_sp_fid_8021d_ops = { #define MLXSW_SP_FID_8021Q_MAX (VLAN_N_VID - 2) #define MLXSW_SP_FID_RFID_MAX (11 * 1024) -#define MLXSW_SP_FID_8021Q_PGT_BASE 0 -#define MLXSW_SP_FID_8021D_PGT_BASE (3 * MLXSW_SP_FID_8021Q_MAX) static const struct mlxsw_sp_flood_table mlxsw_sp_fid_8021d_flood_tables[] = { { @@ -1442,7 +1440,6 @@ static const struct mlxsw_sp_fid_family mlxsw_sp1_fid_8021q_family = { .ops = &mlxsw_sp_fid_8021q_ops, .flood_rsp = false, .bridge_type = MLXSW_REG_BRIDGE_TYPE_0, - .pgt_base = MLXSW_SP_FID_8021Q_PGT_BASE, .smpe_index_valid = false, }; @@ -1456,7 +1453,6 @@ static const struct mlxsw_sp_fid_family mlxsw_sp1_fid_8021d_family = { .rif_type = MLXSW_SP_RIF_TYPE_FID, .ops = &mlxsw_sp_fid_8021d_ops, .bridge_type = MLXSW_REG_BRIDGE_TYPE_1, - .pgt_base = MLXSW_SP_FID_8021D_PGT_BASE, .smpe_index_valid = false, }; @@ -1498,7 +1494,6 @@ static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021q_family = { .ops = &mlxsw_sp_fid_8021q_ops, .flood_rsp = false, .bridge_type = MLXSW_REG_BRIDGE_TYPE_0, - .pgt_base = MLXSW_SP_FID_8021Q_PGT_BASE, .smpe_index_valid = true, }; @@ -1512,7 +1507,6 @@ static const struct mlxsw_sp_fid_family mlxsw_sp2_fid_8021d_family = { .rif_type = MLXSW_SP_RIF_TYPE_FID, .ops = &mlxsw_sp_fid_8021d_ops, .bridge_type = MLXSW_REG_BRIDGE_TYPE_1, - .pgt_base = MLXSW_SP_FID_8021D_PGT_BASE, .smpe_index_valid = true, }; @@ -1697,7 +1691,7 @@ mlxsw_sp_fid_flood_tables_init(struct mlxsw_sp_fid_family *fid_family) return 0; pgt_size = mlxsw_sp_fid_family_pgt_size(fid_family); - err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, fid_family->pgt_base, + err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &fid_family->pgt_base, pgt_size); if (err) return err; diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c index 7dd3dba0fa83..4ef81bac17d6 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_pgt.c @@ -54,25 +54,15 @@ void mlxsw_sp_pgt_mid_free(struct mlxsw_sp *mlxsw_sp, u16 mid_base) mutex_unlock(&mlxsw_sp->pgt->lock); } -int -mlxsw_sp_pgt_mid_alloc_range(struct mlxsw_sp *mlxsw_sp, u16 mid_base, u16 count) +int mlxsw_sp_pgt_mid_alloc_range(struct mlxsw_sp *mlxsw_sp, u16 *p_mid_base, + u16 count) { - unsigned int idr_cursor; + unsigned int mid_base; int i, err; mutex_lock(&mlxsw_sp->pgt->lock); - /* This function is supposed to be called several times as part of - * driver init, in specific order. Verify that the mid_index is the - * first free index in the idr, to be able to free the indexes in case - * of error. - */ - idr_cursor = idr_get_cursor(&mlxsw_sp->pgt->pgt_idr); - if (WARN_ON(idr_cursor != mid_base)) { - err = -EINVAL; - goto err_idr_cursor; - } - + mid_base = idr_get_cursor(&mlxsw_sp->pgt->pgt_idr); for (i = 0; i < count; i++) { err = idr_alloc_cyclic(&mlxsw_sp->pgt->pgt_idr, NULL, mid_base, mid_base + count, GFP_KERNEL); @@ -81,12 +71,12 @@ mlxsw_sp_pgt_mid_alloc_range(struct mlxsw_sp *mlxsw_sp, u16 mid_base, u16 count) } mutex_unlock(&mlxsw_sp->pgt->lock); + *p_mid_base = mid_base; return 0; err_idr_alloc_cyclic: for (i--; i >= 0; i--) idr_remove(&mlxsw_sp->pgt->pgt_idr, mid_base + i); -err_idr_cursor: mutex_unlock(&mlxsw_sp->pgt->lock); return err; } From patchwork Thu Oct 19 10:27:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13428584 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DCF01DFDF for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 10/11] mlxsw: spectrum: Allocate LAG table when in SW LAG mode Date: Thu, 19 Oct 2023 12:27:19 +0200 Message-ID: <741107f4bc32b6b0c7567a05d5f7a27427bb03ca.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|MW6PR12MB8834:EE_ X-MS-Office365-Filtering-Correlation-Id: 3247313b-b7b4-45b6-5cb1-08dbd08e1ca9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: P2a7yfKhBbs8qJ6M89tpTVtiJA3hMCwm44zcdlVpXV25nRy9+xM86CG7GNNYpoBzCvuYYbOTkEDuP0RnYE+iMNrIyR1p1WqXFoWhxdq1AwXnV0jz/DaWDUj47jWdNjjpg9ZYqXYfuK5o+HWFkQ/1VEglDUNgLIIfY9a0R5hKqAXVHBwbNaux7YUcUYo3qEbr4QjwVutIztuuVBppOv889YNcoQ3IGP5bxXL1RVBEnE6kbaz7jN43twmw6lgAynlvFO2WKQVXvYO7E/WKetgdOz+W69EFqtuK9ALinOH3grSKaef6Nr8TtJfMECKpjW6qBdvQr7i6rvPV0ItPk3Ib4QNqfZSNe2ZlplHYaeGVZswLqaJDG5Lhb8rJI1nmavsZnUs8sY6StDxHHZVNC+SaxcLTN19I/dhFg6efCmxYtvaDkC1z1L6FDuOazxWgeF2DSSwYDzwGuT4xbZ2C743ubkpdJn/Phf+o8MmlwX2s5skmKSXO0z0CRI3QuFdRKemQwywgSYo0UROzA53SR//l10ZmeHNkRgW1XpQLqlpuLIjPylO3Wus6x9GFkCFUc25f+Vhqj0KYANhjY74/N+MMpeHMUW7JAaoUXuX7jbQBB6eDOaABhmVTeHcifczjKctx/9EfcFc1busWoiJ0MoT1LzsQdIhFNlYoupHVgZkkuZX4oO+b4T5rB3WnRGy+OsxEnHtLES5cfuPrqaHejDMD4VLiQD579h7Y+1eLoePtnNhgLDasvAoVz3gFCq4V2rF/ X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(230922051799003)(451199024)(82310400011)(64100799003)(186009)(1800799009)(40470700004)(46966006)(36840700001)(66899024)(86362001)(40460700003)(36756003)(40480700001)(41300700001)(4326008)(5660300002)(47076005)(8676002)(66574015)(2906002)(54906003)(316002)(83380400001)(110136005)(16526019)(70206006)(70586007)(36860700001)(478600001)(6666004)(7696005)(2616005)(26005)(426003)(82740400003)(336012)(8936002)(107886003)(7636003)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:18.5820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3247313b-b7b4-45b6-5cb1-08dbd08e1ca9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8834 X-Patchwork-Delegate: kuba@kernel.org In this patch, if the LAG mode is SW, allocate the LAG table and configure SGCR to indicate where it was allocated. We use the default "DDD" (for dynamic data duplication) layout of the LAG table. In the DDD mode, the membership information for each LAG is copied in 8 PGT entries. This is done for performance reasons. The LAG table then needs to be allocated on an address aligned to 8. Deal with this by moving the LAG init ahead so that the LAG table is allocated at address 0. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- .../net/ethernet/mellanox/mlxsw/spectrum.c | 93 ++++++++++++++++--- .../net/ethernet/mellanox/mlxsw/spectrum.h | 1 + 2 files changed, 83 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index 9dbd5edff0b0..d383d00dd860 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -2692,6 +2692,63 @@ static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) kfree(mlxsw_sp->trap); } +static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) +{ + char sgcr_pl[MLXSW_REG_SGCR_LEN]; + u16 max_lag; + int err; + + if (mlxsw_core_lag_mode(mlxsw_sp->core) != + MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) + return 0; + + err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); + if (err) + return err; + + /* In DDD mode, which we by default use, each LAG entry is 8 PGT + * entries. The LAG table address needs to be 8-aligned, but that ought + * to be the case, since the LAG table is allocated first. + */ + err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base, + max_lag * 8); + if (err) + return err; + if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) { + err = -EINVAL; + goto err_mid_alloc_range; + } + + mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base); + err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl); + if (err) + goto err_mid_alloc_range; + + return 0; + +err_mid_alloc_range: + mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, + max_lag * 8); + return err; +} + +static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp) +{ + u16 max_lag; + int err; + + if (mlxsw_core_lag_mode(mlxsw_sp->core) != + MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) + return; + + err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); + if (err) + return; + + mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, + max_lag * 8); +} + #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) @@ -2723,16 +2780,27 @@ static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS)) return -EIO; + err = mlxsw_sp_lag_pgt_init(mlxsw_sp); + if (err) + return err; + mlxsw_sp->lags = kcalloc(max_lag, sizeof(struct mlxsw_sp_upper), GFP_KERNEL); - if (!mlxsw_sp->lags) - return -ENOMEM; + if (!mlxsw_sp->lags) { + err = -ENOMEM; + goto err_kcalloc; + } return 0; + +err_kcalloc: + mlxsw_sp_lag_pgt_fini(mlxsw_sp); + return err; } static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp) { + mlxsw_sp_lag_pgt_fini(mlxsw_sp); kfree(mlxsw_sp->lags); } @@ -3113,6 +3181,15 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, goto err_pgt_init; } + /* Initialize before FIDs so that the LAG table is at the start of PGT + * and 8-aligned without overallocation. + */ + err = mlxsw_sp_lag_init(mlxsw_sp); + if (err) { + dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); + goto err_lag_init; + } + err = mlxsw_sp_fids_init(mlxsw_sp); if (err) { dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n"); @@ -3143,12 +3220,6 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, goto err_buffers_init; } - err = mlxsw_sp_lag_init(mlxsw_sp); - if (err) { - dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n"); - goto err_lag_init; - } - /* Initialize SPAN before router and switchdev, so that those components * can call mlxsw_sp_span_respin(). */ @@ -3300,8 +3371,6 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, err_switchdev_init: mlxsw_sp_span_fini(mlxsw_sp); err_span_init: - mlxsw_sp_lag_fini(mlxsw_sp); -err_lag_init: mlxsw_sp_buffers_fini(mlxsw_sp); err_buffers_init: mlxsw_sp_devlink_traps_fini(mlxsw_sp); @@ -3312,6 +3381,8 @@ static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core, err_policers_init: mlxsw_sp_fids_fini(mlxsw_sp); err_fids_init: + mlxsw_sp_lag_fini(mlxsw_sp); +err_lag_init: mlxsw_sp_pgt_fini(mlxsw_sp); err_pgt_init: mlxsw_sp_kvdl_fini(mlxsw_sp); @@ -3477,12 +3548,12 @@ static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core) mlxsw_sp_counter_pool_fini(mlxsw_sp); mlxsw_sp_switchdev_fini(mlxsw_sp); mlxsw_sp_span_fini(mlxsw_sp); - mlxsw_sp_lag_fini(mlxsw_sp); mlxsw_sp_buffers_fini(mlxsw_sp); mlxsw_sp_devlink_traps_fini(mlxsw_sp); mlxsw_sp_traps_fini(mlxsw_sp); mlxsw_sp_policers_fini(mlxsw_sp); mlxsw_sp_fids_fini(mlxsw_sp); + mlxsw_sp_lag_fini(mlxsw_sp); mlxsw_sp_pgt_fini(mlxsw_sp); mlxsw_sp_kvdl_fini(mlxsw_sp); mlxsw_sp_parsing_fini(mlxsw_sp); diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h index ac9d03937f4b..c70333b460ea 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -212,6 +212,7 @@ struct mlxsw_sp { struct mutex ipv6_addr_ht_lock; /* Protects ipv6_addr_ht */ struct mlxsw_sp_pgt *pgt; bool pgt_smpe_index_valid; + u16 lag_pgt_base; }; struct mlxsw_sp_ptp_ops { From patchwork Thu Oct 19 10:27:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13428585 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 288B518C1D for ; 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Thu, 19 Oct 2023 03:28:05 -0700 Received: from yaviefel.vdiclient.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 19 Oct 2023 03:28:03 -0700 From: Petr Machata To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , Subject: [PATCH net-next 11/11] mlxsw: spectrum: Set SW LAG mode on Spectrum>1 Date: Thu, 19 Oct 2023 12:27:20 +0200 Message-ID: <478c8b531ed8a733fc5c621a648ccccb25361de1.1697710282.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB54:EE_|LV2PR12MB5823:EE_ X-MS-Office365-Filtering-Correlation-Id: 692e00d0-2c70-4b39-bb88-08dbd08e1f7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5p7Bx4JtxNUuxsiVA7WUm/9lgp1ktglyJJVcb16GFjLnR57IMVpw6Zza0QVMJLRyi1fFHZfBbUVHfeu8yWGPHAVggLWR5SOf/JweX07VUTamCS4S9GNySiZBeAbTxhMftaECeLwxzU30oOq5UaGCkmUly5o68nFF5YaO8YaU1p3v2xhyCBlkYCwc9DTrx8tygkSi2TfSTpOiyTj4b8C0bNJXNd8yGxBmpDlkV4wTEzPOgTsqUBgoGKwrCMZ62limxT8p9Kz3iHDUIBs1kKdG9YOkdbp2T4VXEgE4+UG5g6IlgSqewWxNLdI4YDu2w8X2Fx9SqpgbMHkf5RTqm50ea5xKKhz5WiQpjAsqNPuX6W17Qfopnop9JCf3i4TShr6GJYsUwFIrfqVu1kg/aUGonJgTj3Ip2CLXNelr6P18/UjlOWegOdDOi56pbeVI5F+DectEmJNrUOzMHsuweevckrf+i42rObJ0OR6xeciP/rcYJZS9sUHRhQPUm6FWtt0lB+1EkCmK/ZMFeu+Q+azvn14nWZFmk/X1/mH2i2l8yapDjEApUbRwkVEoeKPt+ZmKdiWwdQAS2CZ+CZsBtwywdEkZeLaHaTEEXohHPGPZs+2g9tLyi9htg0bL8UGkG+Q0+7p3biFQb4v9OOlWjKbSYrr8P6tiVrlqb8mZkFFH2rWIPVsUZ/ZODbaCB8uRzeOBCRpepinMpROWWtYi9S4YrYDvo6aXCwNRrFPuHlRx2SleLj5Hz5Iq5pb4YkCzMQcb X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(186009)(1800799009)(451199024)(82310400011)(64100799003)(36840700001)(46966006)(40470700004)(2906002)(40460700003)(5660300002)(8676002)(4326008)(36756003)(8936002)(40480700001)(41300700001)(316002)(110136005)(54906003)(70586007)(70206006)(86362001)(478600001)(6666004)(107886003)(2616005)(7696005)(26005)(426003)(7636003)(356005)(82740400003)(336012)(36860700001)(16526019)(83380400001)(47076005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2023 10:28:23.3202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 692e00d0-2c70-4b39-bb88-08dbd08e1f7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB54.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5823 X-Patchwork-Delegate: kuba@kernel.org On Spectrum-2, Spectrum-3 and Spectrum-4 machines, request SW responsibility for placement of the LAG table. On Spectrum-1, some FW versions claim to support lag_mode field despite quietly ignoring any settings made to that field. Thus refrain from attempting to configure lag_mode on those systems at all. Signed-off-by: Petr Machata Reviewed-by: Ido Schimmel --- drivers/net/ethernet/mellanox/mlxsw/spectrum.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index d383d00dd860..cec72d99d9c9 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -3597,6 +3597,7 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { }, .used_cqe_time_stamp_type = 1, .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, + .lag_mode_prefer_sw = true, }; /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs @@ -3624,6 +3625,7 @@ static const struct mlxsw_config_profile mlxsw_sp4_config_profile = { }, .used_cqe_time_stamp_type = 1, .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, + .lag_mode_prefer_sw = true, }; static void