From patchwork Fri Oct 20 19:50:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13431080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74A94C0032E for ; Fri, 20 Oct 2023 19:52:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=q93sv8UTJW24Y+yGsJgCE2lY24wKx5JdVLynsSUkMYs=; b=yZpZzp3TS8rqnH 5C452xBUVJq7rJHxMvxVUaKk07ZuWn6E4VeMscHgZ14lgbc4Ow1qbcU3JacQa/+sB7Ci4rzTGDSg7 JXLm0j4UJ4v7GHn/sbUz7lHMzk7wU8MeBfk9Oz9QPl+xuhYPrVfEJDvo9dvayGy1ZVYceUBrGbqHp hfzTbD9HYg62Ewv7CDi/P03lTDGePr58FlYn/VVORKjvRLehx0YMQlpG15y5iLg+Ct5mgsVMXDQ6H BpNh7Tp9wZYh21voRutzIn1x8y2X7gqxZtj6QnI0GZbg40LXGXGdw1IL5Pbl6RE3FYCNFwJhydJHV giBg/SoaARqyfJm3jBow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtvXC-002wXe-1P; Fri, 20 Oct 2023 19:51:50 +0000 Received: from mail-oa1-f47.google.com ([209.85.160.47]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qtvXA-002wXF-1V for linux-arm-kernel@lists.infradead.org; Fri, 20 Oct 2023 19:51:49 +0000 Received: by mail-oa1-f47.google.com with SMTP id 586e51a60fabf-1e19cb7829bso874011fac.1 for ; Fri, 20 Oct 2023 12:51:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697831507; x=1698436307; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=K8/ZbVb/9IBC0WHwq8jl1yDqEWiHfKExUA5yi1WK5j4=; b=HOZIHOVsHmF6UWYuVBnvp61QbareNzloG9fyM2pgvlKXAHcYnElSYRgg/Kcn6miDtb PnKuwJSrKu9bJgNCieYYzoPax8I5BReG8+/pn9Bg4WzsJgH5PkEt7RW3+PC0Q39kmOcA ucqhHp3jcOb9bfIjqJzE+7PqxC0iHWx5iQsXLp61pXJADmXHxUCK2Ug9GwPxQZ1Q5CQ8 70W0JcPHqitmbK16Rg7F3yASD4MFduE3cqtxh+Pod3eKUUm00/kr237jorwZ9LnTYC1p ZrOtjlnCMnOmRsnueEtxDYSe21rCjPiIAnmp7bpPIwJYaQ1Km8tZPy8XlaRx0stDXA8v SE3g== X-Gm-Message-State: AOJu0YyEKIEM3qSB/RlYYjVNuaSZaybrIv58CTD9WUWPN9xJ1c4HVq8y CvfdiEXqfs+TOD7NntxjWw== X-Google-Smtp-Source: AGHT+IFDQtRnNsXely0BT6dTlD9vbK/uYWv6xNMrP4qF2nI/sgu7QAY8ttiA22cFlzAmEMbaUvSsYg== X-Received: by 2002:a05:6870:5cc9:b0:1e9:9989:33a5 with SMTP id et9-20020a0568705cc900b001e9998933a5mr3353395oab.5.1697831507323; Fri, 20 Oct 2023 12:51:47 -0700 (PDT) Received: from herring.priv (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id m7-20020a056870194700b001cc9bc7b569sm483158oak.27.2023.10.20.12.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 12:51:46 -0700 (PDT) Received: (nullmailer pid 4185737 invoked by uid 1000); Fri, 20 Oct 2023 19:51:45 -0000 From: Rob Herring To: soc@kernel.org, Krzysztof Kozlowski , Conor Dooley , Kunihiko Hayashi , Masami Hiramatsu Cc: Pierre Gondois , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND PATCH v2] arm64: dts: Update cache properties for socionext Date: Fri, 20 Oct 2023 14:50:22 -0500 Message-ID: <20231020195022.4183862-2-robh@kernel.org> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231020_125148_504621_6A6D463D X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pierre Gondois The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Reviewed-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski --- I noticed this one fell thru the cracks from the rest of the series. Arnd, Can you take this directly. arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 1 + arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b071475..54e58d945fd7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,7 @@ cpu1: cpu@1 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272..18390cba2eda 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,12 @@ cpu3: cpu@101 { a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea42..56e037900818 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,7 @@ cpu3: cpu@3 { l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; };