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Lin" , Singo Chang , "Nancy Lin" , Shawn Sung Subject: [PATCH v2 1/9] dt-bindings: gce: mt8195: Add CMDQ_SYNC_TOKEN_SECURE_THR_EOF event id Date: Mon, 23 Oct 2023 12:37:43 +0800 Message-ID: <20231023043751.17114-2-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--6.916700-8.000000 X-TMASE-MatchedRID: IajWZngc9jMepnz2STo7dG3NvezwBrVmWIY1mtkm5WDfUZT83lbkEKr+ XcmqaRdP2YJ36PQpkbxcQcZU6RHBSpH0YXYnbGozFEUknJ/kEl5jFT88f69nG/oLR4+zsDTtjoc zmuoPCq013lqSCSy62Ckfi332ba81z9MznZrI2ArgCJXl+Q/4b9q3pvrxn4wTQwymtxuJ6y0= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.916700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 226DC81E61C736BCE8D18E9F6809EBAEF63BA28418595AE619577313A3B831312000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213804_341083_014251CF X-CRM114-Status: UNSURE ( 8.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CMDQ_SYNC_TOKEN_SECURE_THR_EOF is used as secure irq to notify CMDQ driver in the normal world that GCE secure thread has completed a task in thee secure world. Signed-off-by: Jason-JH.Lin --- include/dt-bindings/gce/mt8195-gce.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/gce/mt8195-gce.h b/include/dt-bindings/gce/mt8195-gce.h index dcfb302b8a5b..9f99da3363b9 100644 --- a/include/dt-bindings/gce/mt8195-gce.h +++ b/include/dt-bindings/gce/mt8195-gce.h @@ -809,4 +809,10 @@ /* end of hw event */ #define CMDQ_MAX_HW_EVENT 1019 +/* + * Notify normal CMDQ there are some secure task done, + * this token sync with secure world. + */ +#define CMDQ_SYNC_TOKEN_SECURE_THR_EOF 980 + #endif From patchwork Mon Oct 23 04:37:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FBCCC25B41 for ; Mon, 23 Oct 2023 04:38:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tIl0XPftdVxQBRM5HQYLF+TbGbHNDqS0903XN/VVun8=; b=RPWLhVQ/kfQiFs iYvIFEKDHzkECRfG35s7jXGzmJY/DBse4pVNPnCHLczO35tNMfMthObVssRfSIHcEhsH+3eqSLmkF EA+d4fkEQq5k9AprEfwhtlRtcNeR5ILMy65FNRFNvnJXoWwNDXuotjnjYM0xhsD8xYXoq54Cn2VyP cRheyetW6ow8dexopRWcOVFM3Edak4P5eLxAQAotyDcjrch+Qj1cUXibvdlSAl68qKJ+0y9CN3ov5 aWFYTDoVGNxqZvJDaO2Usnwc+CNhdNUPZZnqweODMKxOjDMsUw6Fkye8+zbkZBX+eKx3uZbBn2bPI zfSCjjO1o0GeT8kYd/nA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qumhh-006Obb-1b; Mon, 23 Oct 2023 04:38:13 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qumhY-006OYm-2I; Mon, 23 Oct 2023 04:38:06 +0000 X-UUID: f0cdfdf2715d11ee86758d4a7c00f3a0-20231022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=5nBOwBADosCE0laOtnAK0L9ej3kKDQodffYRoyom3d4=; b=qbpDe39Kbe9erBOql0tHxvYRI8/DitqBpxCcjYtFchJe/1lm2SDX0PrvT3bv9U1KxHP916nFC6oarkCT0b4Kanv1bwbDuWMJhysgZXG0BuT+wKCv/6WAVJjceitT3hpfgpzFHBjleL8gYWhilRNbcvj2kzXKK1PjiPm+pREpGK4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:683688e9-08f3-46d7-bbed-7e812490ef5a,IP:0,U RL:0,TC:0,Content:41,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:41 X-CID-META: VersionHash:5f78ec9,CLOUDID:707731d7-04a0-4e50-8742-3543eab8cb8e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:3,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f0cdfdf2715d11ee86758d4a7c00f3a0-20231022 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 179249380; Sun, 22 Oct 2023 21:37:58 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 12:37:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 12:37:54 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , "Johnson Wang" , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Shawn Sung Subject: [PATCH v2 2/9] dt-bindings: mailbox: Add property for CMDQ secure driver Date: Mon, 23 Oct 2023 12:37:44 +0800 Message-ID: <20231023043751.17114-3-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.522000-8.000000 X-TMASE-MatchedRID: y/MOm6ldwRIXSulpnju2H6wxbZnudyr7uLwbhNl9B5ULsYGwWRkFSmlF 7OhYLlctSBg3ErWyNT+PwmjRI+95a5rTfAGXhNOwTVa+L3Zgqc59LQinZ4QefPcjNeVeWlqY+gt Hj7OwNO2i5u/VvsFaHTsYKoZqBjyBCz8kvCpjUFQQyeIABkT72SV6AZY42TeLs2goH+0UPJS5sz pSRKsJSjbRPLz0bRf2+uyaDsGpB7/U1sBtGzC0lHZrUbEZipAEiWT09mQz7szw9kH8zAy44aOuV Lnx3A74 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.522000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 90C735ACB7A7C027BB46F382C2C4F23A60860207BC61CDEDC5264774F324D8CA2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213804_749414_89CD61FF X-CRM114-Status: GOOD ( 10.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add mboxes to define a GCE loopping thread as a secure irq handler. Add mediatek,gce-events to define a GCE event siganl sent from CMDQ TA driver in secure world as a secure irq. These 2 properties are required for CMDQ secure driver. Signed-off-by: Jason-JH.Lin --- .../bindings/mailbox/mediatek,gce-mailbox.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index cef9d7601398..65fb93bb53b6 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -49,6 +49,16 @@ properties: items: - const: gce + mboxes: + maxItems: 1 + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + required: - compatible - "#mbox-cells" From patchwork Mon Oct 23 04:37:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 753DFC001E0 for ; Mon, 23 Oct 2023 04:39:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MOtppU49C9+WZcbYEDwdKPxJU3PjrLBAW1LU9bV1aeE=; b=mqFznYgzLHTdkl T6J1N9qt51ImmeSEFd1gzTCz5VYBnQ/9TGV2kGkaZ/l+6HZQm4Ou5fsK1GxeMOSoaA6f+q4M/WNjb WXjYzxUHInRucG3QdL9ShPn9SfT/VerjHtkmILYHdDTxAu64lDT9IAIXFXoS5IQiuBvxp1XEwkyEW 7q4xVIthUGvLBkUn+c6FUZZc5y/LPvidL2b3SFFfk5hZ1SYJMqBZNCx/WL8IkUn0U0g4MWhbIvHza 7dQpWwG6mOHru1ia0/tA/QjGbPLQlgmsKESUdcH5Oicsu62OpC/uNcmgRPRdkBpjhFTCxG+Guu0SU /Yygs4Mezhq+q+Ro7zeQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qumiX-006Ovf-0H; Mon, 23 Oct 2023 04:39:05 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qumiU-006Otd-07; Mon, 23 Oct 2023 04:39:03 +0000 X-UUID: 149582aa715e11ee9b7791016c24628a-20231022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GpJxBLoK2jsQ6y0Gx3euE9llEY/qK/uxJ7GJoeCPKd8=; b=u4DWFdTkarAfSph1Tg9WwAz0EqHhvOhkqsNSzglWeycu8yEr99h5opvPHwe9we444UUSFjVvEd63/G5M4WtSC4uN8VkycJ7JtqSHcNDu5WNze+ibVt3BRLdUhfWqBUdjB/8SOzP2WctzMaizQxqMaYzfvOCLf+wU5EYvTuAkkJY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:66d2c2a0-9b1e-4468-a812-76be40a099ac,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:517931d7-04a0-4e50-8742-3543eab8cb8e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 149582aa715e11ee9b7791016c24628a-20231022 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1720433290; Sun, 22 Oct 2023 21:38:58 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 12:37:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 12:37:54 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , "Johnson Wang" , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Shawn Sung Subject: [PATCH v2 3/9] soc: mailbox: Add cmdq_pkt_logic_command to support math operation Date: Mon, 23 Oct 2023 12:37:45 +0800 Message-ID: <20231023043751.17114-4-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.806100-8.000000 X-TMASE-MatchedRID: wDTc/wNgEcM7GQ7VM/DlUU0IfQOJvRLRQKuv8uQBDjr7efdnqtsaExFx R5JQAS6O09NQNrxIpFbaGEeUNUEoVATsy5Ctk/ajpLS2yK6GQKOXYX34rFl3xxUZTfM00s4+tTD LZLR3mBE84GeYDGFPpnegIXkiA/apHxPMjOKY7A8LbigRnpKlKZvjAepGmdoOc6NjhkWnv1nUBs gfEe2OE3w6V0ttw+Rg8NbAhlNr8DbhZn2aF+ag0zCpMruasADBcvCaIJyGqr7shOa79co2/wH7g OC6yvdrSZrfNhP3sgUBh9AgBSEFrJm+YJspVvj2xkvrHlT8euJ0YHKn7N1oOA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.806100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: C6658C9C4E69CC63DFC7D9117807C1BCAB519431F94C65945195F0910CC2CABB2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213902_078059_99EC5D2E X-CRM114-Status: GOOD ( 15.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cmdq_pkt_logic_command to support match operation. cmdq_pkt_logic_command can append logic command to the CMDQ packet, ask GCE to execute a arithematic calculate instruction, such as add, subtract, multiply, AND, OR and NOT, etc. Note that all instructions just accept unsigned calculate. If there are any overflows, GCE will sent the invalid IRQ to notify CMDQ driver. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 36 ++++++++++++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 41 ++++++++++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index b0cd071c4719..5194d66dfc0a 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -13,9 +13,18 @@ #define CMDQ_WRITE_ENABLE_MASK BIT(0) #define CMDQ_POLL_ENABLE_MASK BIT(0) #define CMDQ_EOC_IRQ_EN BIT(0) +#define CMDQ_IMMEDIATE_VALUE 0 #define CMDQ_REG_TYPE 1 #define CMDQ_JUMP_RELATIVE 1 +#define CMDQ_OPERAND_GET_IDX_VALUE(operand) \ + ({ \ + struct cmdq_operand *op = operand; \ + op->reg ? op->idx : op->value; \ + }) +#define CMDQ_OPERAND_TYPE(operand) \ + ((operand)->reg ? CMDQ_REG_TYPE : CMDQ_IMMEDIATE_VALUE) + struct cmdq_instruction { union { u32 value; @@ -380,6 +389,33 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, } EXPORT_SYMBOL(cmdq_pkt_poll_mask); +int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, enum CMDQ_LOGIC_ENUM s_op, + u16 result_reg_idx, + struct cmdq_operand *left_operand, + struct cmdq_operand *right_operand) +{ + struct cmdq_instruction inst = { {0} }; + u32 left_idx_value; + u32 right_idx_value; + + if (!left_operand || !right_operand) + return -EINVAL; + + left_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(left_operand); + right_idx_value = CMDQ_OPERAND_GET_IDX_VALUE(right_operand); + inst.op = CMDQ_CODE_LOGIC; + inst.dst_t = CMDQ_REG_TYPE; + inst.src_t = CMDQ_OPERAND_TYPE(left_operand); + inst.arg_c_t = CMDQ_OPERAND_TYPE(right_operand); + inst.sop = s_op; + inst.arg_c = right_idx_value; + inst.src_reg = left_idx_value; + inst.reg_dst = result_reg_idx; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_logic_command); + int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) { struct cmdq_instruction inst = {}; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index a253c001c861..ea4fadfb5443 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -26,6 +26,30 @@ struct cmdq_pkt; +enum CMDQ_LOGIC_ENUM { + CMDQ_LOGIC_ASSIGN = 0, + CMDQ_LOGIC_ADD = 1, + CMDQ_LOGIC_SUBTRACT = 2, + CMDQ_LOGIC_MULTIPLY = 3, + CMDQ_LOGIC_XOR = 8, + CMDQ_LOGIC_NOT = 9, + CMDQ_LOGIC_OR = 10, + CMDQ_LOGIC_AND = 11, + CMDQ_LOGIC_LEFT_SHIFT = 12, + CMDQ_LOGIC_RIGHT_SHIFT = 13, +}; + +struct cmdq_operand { + /* register type */ + bool reg; + union { + /* index */ + u16 idx; + /* value */ + u16 value; + }; +}; + struct cmdq_client_reg { u8 subsys; u16 offset; @@ -244,6 +268,23 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value, u32 mask); +/** + * cmdq_pkt_logic_command() - Append logic command to the CMDQ packet, ask GCE to + * execute an instruction that store the result of logic operation + * with left and right operand into result_reg_idx. + * @pkt: the CMDQ packet + * @s_op: the logic operator enum + * @result_reg_idx: SPR index that store operation result of left_operand and right_operand + * @left_operand: left operand + * @right_operand: right operand + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_logic_command(struct cmdq_pkt *pkt, enum CMDQ_LOGIC_ENUM s_op, + u16 result_reg_idx, + struct cmdq_operand *left_operand, + struct cmdq_operand *right_operand); + /** * cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask GCE * to execute an instruction that set a constant value into From patchwork Mon Oct 23 04:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BF3ABC25B42 for ; Mon, 23 Oct 2023 04:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 4/9] soc: mailbox: Add cmdq_pkt_write_s_reg_value to support write value to reg Date: Mon, 23 Oct 2023 12:37:46 +0800 Message-ID: <20231023043751.17114-5-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213835_555869_900FE1A1 X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cmdq_pkt_write_s_reg_value to support write a value to a register. It appends write_s command to the command buffer in a CMDQ packet, ask GCE to excute a write instruction to write a value to a register with low 16 bits physical address offset. Signed-off-by: Jason-JH.Lin --- drivers/soc/mediatek/mtk-cmdq-helper.c | 13 +++++++++++++ include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 5194d66dfc0a..4be2a18a4a02 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -287,6 +287,19 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, } EXPORT_SYMBOL(cmdq_pkt_write_s_value); +int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value) +{ + struct cmdq_instruction inst = {}; + + inst.op = CMDQ_CODE_WRITE_S; + inst.dst_t = CMDQ_REG_TYPE; + inst.reg_dst = high_addr_reg_idx; + inst.value = value; + + return cmdq_pkt_append_command(pkt, inst); +} +EXPORT_SYMBOL(cmdq_pkt_write_s_reg_value); + int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask) { diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index ea4fadfb5443..4262594a0d18 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -207,6 +207,17 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u16 addr_low, u32 value, u32 mask); +/** + * cmdq_pkt_write_s_reg_value() - append write_s command to the CMDQ packet which + * write value to a register with low address pa + * @pkt: the CMDQ packet + * @reg_idx: internal register ID which contains high address of pa + * @value: the specified target value + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_write_s_reg_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, u32 value); + /** * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet * @pkt: the CMDQ packet From patchwork Mon Oct 23 04:37:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DFA76C001E0 for ; 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Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 5/9] soc: mailbox: Add cmdq_pkt_finalize_loop to support looping cmd with irq Date: Mon, 23 Oct 2023 12:37:47 +0800 Message-ID: <20231023043751.17114-6-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213834_170917_B0571212 X-CRM114-Status: GOOD ( 16.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add cmdq_pkt_finalize_loop to CMDQ driver. cmdq_pkt_finalize_loop appends end of command(EOC) instruction and jump to start of command buffer instruction to make the command buffer loopable. GCE irq occurs when GCE executes to the EOC instruction. CMDQ client can use a loop flag to mark the CMDQ packet as looping packet. If the CMDQ packet is a loopping packet, GCE irq handler won't delete the CMDQ task and disable the GCE thread. Signed-off-by: Jason-JH.Lin --- drivers/mailbox/mtk-cmdq-mailbox.c | 11 +++++++++++ drivers/soc/mediatek/mtk-cmdq-helper.c | 23 +++++++++++++++++++++++ include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + include/linux/soc/mediatek/mtk-cmdq.h | 8 ++++++++ 4 files changed, 43 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 4d62b07c1411..56fe01cd9731 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -264,6 +264,17 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq, curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->pdata->shift; + task = list_first_entry_or_null(&thread->task_busy_list, + struct cmdq_task, list_entry); + if (task && task->pkt->loop) { + struct cmdq_cb_data data; + + data.sta = err; + data.pkt = task->pkt; + mbox_chan_received_data(task->thread->chan, &data); + return; + } + list_for_each_entry_safe(task, tmp, &thread->task_busy_list, list_entry) { task_end_pa = task->pa_base + task->pkt->cmd_buf_size; diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 4be2a18a4a02..bbb127620bb3 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -475,6 +475,29 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt) } EXPORT_SYMBOL(cmdq_pkt_finalize); +int cmdq_pkt_finalize_loop(struct cmdq_pkt *pkt) +{ + struct cmdq_instruction inst = { {0} }; + int err; + + /* insert EOC and generate IRQ for each command iteration */ + inst.op = CMDQ_CODE_EOC; + inst.value = CMDQ_EOC_IRQ_EN; + err = cmdq_pkt_append_command(pkt, inst); + if (err < 0) + return err; + + /* JUMP to start of pkt */ + err = cmdq_pkt_jump(pkt, pkt->pa_base); + if (err < 0) + return err; + + pkt->loop = true; + + return err; +} +EXPORT_SYMBOL(cmdq_pkt_finalize_loop); + int cmdq_pkt_flush_async(struct cmdq_pkt *pkt) { int err; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index a8f0070c7aa9..f78a08e7c6ed 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -76,6 +76,7 @@ struct cmdq_pkt { size_t cmd_buf_size; /* command occupied size */ size_t buf_size; /* real buffer size */ void *cl; + bool loop; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan); diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 4262594a0d18..deb2e1920a0e 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -328,6 +328,14 @@ int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr); */ int cmdq_pkt_finalize(struct cmdq_pkt *pkt); +/** + * cmdq_pkt_finalize_loop() - Append EOC and jump to start command. + * @pkt: the CMDQ packet + * + * Return: 0 for success; else the error code is returned + */ +int cmdq_pkt_finalize_loop(struct cmdq_pkt *pkt); + /** * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ * packet and call back at the end of done packet From patchwork Mon Oct 23 04:37:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6A1FC001E0 for ; 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Lin" , Singo Chang , "Nancy Lin" , Shawn Sung Subject: [PATCH v2 6/9] mailbox: mediatek: Add CMDQ driver support for mt8188 Date: Mon, 23 Oct 2023 12:37:48 +0800 Message-ID: <20231023043751.17114-7-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.774700-8.000000 X-TMASE-MatchedRID: cAwOsowI+VI9S3IiQd+eNaMVgdN9w+TCTJDl9FKHbrkKogmGusPLb2Tv 8eaKHrag93LsYxp0JcCAMuqetGVetnyef22ep6XYOwBXM346/+wXxfm3DGa52ziDgySw1N/WFKA zntrocjJUmbEGssD1oyi8qpjQ9hxh X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.774700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: F5A44B3488AD73E6EF408530E3DB8994676D03692E77F9D01A964B8CDBD02E392000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_215806_019153_AB20AFAF X-CRM114-Status: UNSURE ( 9.41 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CMDQ driver support for mt8188 by adding its compatible and driver data in CMDQ driver. Signed-off-by: Jason-JH.Lin --- drivers/mailbox/mtk-cmdq-mailbox.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 56fe01cd9731..3bdfb9a60614 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -704,12 +704,20 @@ static const struct gce_plat gce_plat_v7 = { .gce_num = 1 }; +static const struct gce_plat gce_plat_v8 = { + .thread_nr = 32, + .shift = 3, + .control_by_sw = true, + .gce_num = 2 +}; + static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_v7}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, + {.compatible = "mediatek,mt8188-gce", .data = (void *)&gce_plat_v8}, {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6}, {} }; From patchwork Mon Oct 23 04:37:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432338 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A662CCDB474 for ; Mon, 23 Oct 2023 04:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Dk05JpQHPDzlb6Q44sa1fdH3qrd9RMowZ13ZJKS1o0Q=; b=j3fhHCPE+ECZB4 aoiYZFdVcYimklbDgAd7ObWo5crbLYbvi5XGctXnPN5RQvEC7NKi5AHuO8YTKhz5yLtdju0cyG3t5 q6wBOnhmA8WnfGnxEDrJhrAcHoeL6I5g0Fz3PBouCEHVkdXwxDBzIb+oqk8dgb5N0jSaNaiaaFRTQ 6upXKbCx7FM8gEGNYxNoJ4khtWFo99s+JX7OIuK8gVFhLtZLi0QP0MfW6Yf/xsxZ4uR2CAFLmrmtF ig7Mg1Tdj4DIY2IHI4+ikb+0eDpFmxNYzWa3lx9JAtyKGZ+9rA4n5qJOVTn2G4B6ctzrVYW5N6VKh Cx3LhtYpPI6uBVW+nW7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qumif-006P05-10; Mon, 23 Oct 2023 04:39:13 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qumiU-006Ou4-3D; Mon, 23 Oct 2023 04:39:04 +0000 X-UUID: 151fe7d8715e11ee9b7791016c24628a-20231022 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QCE1xwplhv7g43FWzmxofcp5fWVm6amYBKyf89k0HWI=; b=N4nxgJKz6b0nOW4GauYagDw+YIt93txnWgW5URpUWg7qu9GmShoPwW8B+phbDbJY+7sETROtFi5kRuxIStebVGXkQTun1bPUEaLfh3lzDKs2wDSRl+mUiXJy/ipf2eh8FbBU+AMl7+0lOsFRIT4t8HicGaEZJZyEAevcFyDGh88=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:73cfffeb-b53f-4790-ac6d-0fc0ebb64b34,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:59018294-10ce-4e4b-85c2-c9b5229ff92b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 151fe7d8715e11ee9b7791016c24628a-20231022 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 490841723; Sun, 22 Oct 2023 21:38:59 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 23 Oct 2023 12:37:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 12:37:54 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , "Johnson Wang" , "Jason-JH . Lin" , Singo Chang , "Nancy Lin" , Shawn Sung Subject: [PATCH v2 7/9] mailbox: mediatek: Add secure CMDQ driver support for CMDQ driver Date: Mon, 23 Oct 2023 12:37:49 +0800 Message-ID: <20231023043751.17114-8-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.531600-8.000000 X-TMASE-MatchedRID: R4jZHsvSUGclen1U/pCyekKcYi5Qw/RVCt59Uh3p/NVZps+y1VXzqUY/ auwRJnMLb1ikhugskqOOaaDenG8Fpc3AmdtMjGJVA9lly13c/gGuiRuR9mCaugqiCYa6w8tv235 yFjo/J+UK+kRk9ukAW+gSLotCiZMMHbClfpWB0AaeAiCmPx4NwBnUJ0Ek6yhjxEHRux+uk8jHUU +U0ACZwDM3/yauti3zE7n0nNNLhws2fCNH4eoPw5Wqh7x/wwDnnqg/VrSZEiM= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.531600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 0A72A5C88A1BA3E630A7B31C2BAC12F0A299FB84059DF24239935E87E14291BE2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213903_040020_74C7D2F7 X-CRM114-Status: GOOD ( 19.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CMDQ driver will probe a secure CMDQ driver when has_sec flag in platform data is true and its device node in dts has defined a event id of CMDQ_SYNC_TOKEN_SEC_EOF. Secure CMDQ driver support on mt8188 and mt8195 currently. So add a has_sec flag to their driver data to probe it. Signed-off-by: Jason-JH.Lin --- drivers/mailbox/mtk-cmdq-mailbox.c | 42 ++++++++++++++++++++++-- include/linux/mailbox/mtk-cmdq-mailbox.h | 11 +++++++ 2 files changed, 51 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index 3bdfb9a60614..4db5eb76f353 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -87,6 +87,7 @@ struct gce_plat { u8 shift; bool control_by_sw; bool sw_ddr_en; + bool has_sec; u32 gce_num; }; @@ -560,14 +561,23 @@ static int cmdq_probe(struct platform_device *pdev) int alias_id = 0; static const char * const clk_name = "gce"; static const char * const clk_names[] = { "gce0", "gce1" }; + struct resource *res; + struct platform_device *mtk_cmdq_sec; + u32 hwid = 0; cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); if (!cmdq) return -ENOMEM; - cmdq->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(cmdq->base)) + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + cmdq->base = devm_ioremap_resource(dev, res); + if (IS_ERR(cmdq->base)) { + dev_err(dev, "failed to ioremap cmdq\n"); return PTR_ERR(cmdq->base); + } cmdq->irq = platform_get_irq(pdev, 0); if (cmdq->irq < 0) @@ -585,6 +595,8 @@ static int cmdq_probe(struct platform_device *pdev) dev, cmdq->base, cmdq->irq); if (cmdq->pdata->gce_num > 1) { + hwid = of_alias_get_id(dev->of_node, clk_name); + for_each_child_of_node(phandle->parent, node) { alias_id = of_alias_get_id(node, clk_name); if (alias_id >= 0 && alias_id < cmdq->pdata->gce_num) { @@ -653,6 +665,30 @@ static int cmdq_probe(struct platform_device *pdev) return err; } + if (cmdq->pdata->has_sec) { + struct cmdq_sec_plat gce_sec_plat; + + if (of_property_read_u32_index(dev->of_node, "mediatek,gce-events", 0, + &gce_sec_plat.cmdq_event) == 0) { + gce_sec_plat.gce_dev = dev; + gce_sec_plat.base = cmdq->base; + gce_sec_plat.base_pa = res->start; + gce_sec_plat.hwid = hwid; + gce_sec_plat.gce_num = cmdq->pdata->gce_num; + gce_sec_plat.clocks = cmdq->clocks; + gce_sec_plat.thread_nr = cmdq->pdata->thread_nr; + + mtk_cmdq_sec = platform_device_register_data(dev, "mtk_cmdq_sec", + PLATFORM_DEVID_AUTO, + &gce_sec_plat, + sizeof(gce_sec_plat)); + if (IS_ERR(mtk_cmdq_sec)) { + dev_err(dev, "failed to register platform_device mtk_cmdq_sec\n"); + return PTR_ERR(mtk_cmdq_sec); + } + } + } + return 0; } @@ -693,6 +729,7 @@ static const struct gce_plat gce_plat_v6 = { .thread_nr = 24, .shift = 3, .control_by_sw = true, + .has_sec = true, .gce_num = 2 }; @@ -708,6 +745,7 @@ static const struct gce_plat gce_plat_v8 = { .thread_nr = 32, .shift = 3, .control_by_sw = true, + .has_sec = true, .gce_num = 2 }; diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index f78a08e7c6ed..fdda995a69ce 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -79,6 +79,17 @@ struct cmdq_pkt { bool loop; }; +struct cmdq_sec_plat { + struct device *gce_dev; + void __iomem *base; + dma_addr_t base_pa; + u32 hwid; + u32 gce_num; + struct clk_bulk_data *clocks; + u32 thread_nr; + u32 cmdq_event; +}; + u8 cmdq_get_shift_pa(struct mbox_chan *chan); #endif /* __MTK_CMDQ_MAILBOX_H__ */ From patchwork Mon Oct 23 04:37:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432336 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D4A87CDB474 for ; Mon, 23 Oct 2023 04:39:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Mon, 23 Oct 2023 12:37:55 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 23 Oct 2023 12:37:55 +0800 From: Jason-JH.Lin To: Jassi Brar , Chun-Kuang Hu , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski CC: Conor Dooley , Matthias Brugger , , , , , Jeffrey Kardatzke , Jason-ch Chen , Johnson Wang , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 8/9] mailbox: mediatek: Add CMDQ secure mailbox driver Date: Mon, 23 Oct 2023 12:37:50 +0800 Message-ID: <20231023043751.17114-9-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213835_682025_0837BC14 X-CRM114-Status: GOOD ( 24.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support secure video path feature, GCE have to read/write registgers in the secure world. GCE will enable the secure access permission to the HW who wants to access the secure content buffer. Add CMDQ secure mailbox driver to make CMDQ client user is able to sending their HW settings to the secure world. So that GCE can execute all instructions to configure HW in the secure world. Signed-off-by: Jason-JH.Lin --- drivers/mailbox/Makefile | 2 +- drivers/mailbox/mtk-cmdq-sec-mailbox.c | 1102 +++++++++++++++++ drivers/mailbox/mtk-cmdq-sec-tee.c | 202 +++ include/linux/mailbox/mtk-cmdq-mailbox.h | 2 + .../linux/mailbox/mtk-cmdq-sec-iwc-common.h | 293 +++++ include/linux/mailbox/mtk-cmdq-sec-mailbox.h | 83 ++ include/linux/mailbox/mtk-cmdq-sec-tee.h | 31 + 7 files changed, 1714 insertions(+), 1 deletion(-) create mode 100644 drivers/mailbox/mtk-cmdq-sec-mailbox.c create mode 100644 drivers/mailbox/mtk-cmdq-sec-tee.c create mode 100644 include/linux/mailbox/mtk-cmdq-sec-iwc-common.h create mode 100644 include/linux/mailbox/mtk-cmdq-sec-mailbox.h create mode 100644 include/linux/mailbox/mtk-cmdq-sec-tee.h diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index fc9376117111..82da2f4ee81a 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -51,7 +51,7 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o -obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o +obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o mtk-cmdq-sec-mailbox.o mtk-cmdq-sec-tee.o obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o diff --git a/drivers/mailbox/mtk-cmdq-sec-mailbox.c b/drivers/mailbox/mtk-cmdq-sec-mailbox.c new file mode 100644 index 000000000000..dac867386cf1 --- /dev/null +++ b/drivers/mailbox/mtk-cmdq-sec-mailbox.c @@ -0,0 +1,1102 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2019 MediaTek Inc. + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CMDQ_THR_BASE (0x100) +#define CMDQ_THR_SIZE (0x80) +#define CMDQ_THR_EXEC_CNT_PA (0x28) + +#define CMDQ_BUF_ALLOC_SIZE (PAGE_SIZE) +#define CMDQ_TIMEOUT_DEFAULT (1000) +#define CMDQ_NO_TIMEOUT (0xffffffff) +#define ADDR_METADATA_MAX_COUNT_ORIGIN (8) + +/* + * CMDQ secure context struct + * note it is not global data, each process has its own CMDQ sec context + */ +struct cmdq_sec_context { + struct list_head listEntry; + + /* basic info */ + u32 tgid; /* tgid of process context */ + u32 referCount; /* reference count for open cmdq device node */ + + /* iwc state */ + enum cmdq_iwc_state_enum state; + + /* iwc information */ + void *iwc_msg; /* message buffer */ + + struct cmdq_sec_tee_context tee; /* trustzone parameters */ +}; + +struct cmdq_sec_task { + struct list_head list_entry; + dma_addr_t pa_base; + struct cmdq_sec_thread *thread; + struct cmdq_pkt *pkt; + u64 exec_time; + struct work_struct exec_work; + + bool resetExecCnt; + u32 waitCookie; + + u64 engineFlag; + s32 scenario; + u64 trigger; +}; + +struct cmdq_sec_thread { + struct mbox_chan *chan; + void __iomem *base; + struct list_head task_list; + struct timer_list timeout; + u32 timeout_ms; + struct work_struct timeout_work; + u32 priority; + u32 idx; + bool occupied; + + /* following part only secure ctrl */ + u32 wait_cookie; + u32 next_cookie; + u32 task_cnt; + struct workqueue_struct *task_exec_wq; +}; + +/** + * shared memory between normal and secure world + */ +struct cmdq_sec_shared_mem { + void *va; + dma_addr_t pa; + u32 size; +}; + +struct cmdq_sec { + struct mbox_controller mbox; + void __iomem *base; + phys_addr_t base_pa; + u32 hwid; + u32 gce_num; + struct clk_bulk_data *clocks; + u32 thread_nr; + struct cmdq_sec_thread *thread; + struct cmdq_client *clt; + struct cmdq_pkt *clt_pkt; + + atomic_t path_res; + struct cmdq_sec_shared_mem *shared_mem; + struct cmdq_sec_context *context; + struct iwcCmdqCancelTask_t cancel; + + struct workqueue_struct *timeout_wq; + u64 sec_invoke; + u64 sec_done; + + bool notify_run; + struct work_struct irq_notify_work; + struct workqueue_struct *notify_wq; + u32 cmdq_event; + /* mutex for cmdq_sec_thread excuting cmdq_sec_task */ + struct mutex exec_lock; +}; + +static atomic_t cmdq_path_res = ATOMIC_INIT(0); + +static int cmdq_sec_task_submit(struct cmdq_sec *cmdq, struct cmdq_sec_task *task, + const u32 iwc_cmd, const u32 thrd_idx, void *data); + +static inline void cmdq_sec_setup_tee_context_base(struct cmdq_sec_context *context) +{ + cmdq_sec_setup_tee_context(&context->tee); +} + +static inline int cmdq_sec_init_context_base(struct cmdq_sec_context *context) +{ + int status; + + status = cmdq_sec_init_context(&context->tee); + if (status < 0) + return status; + + return status; +} + +int cmdq_sec_insert_backup_cookie(struct cmdq_pkt *pkt) +{ + struct cmdq_client *cl = (struct cmdq_client *)pkt->cl; + struct cmdq_sec_thread *thread = ((struct mbox_chan *)(cl->chan))->con_priv; + struct cmdq_sec *cmdq = container_of(thread->chan->mbox, struct cmdq_sec, mbox); + struct cmdq_operand left, right; + dma_addr_t addr; + + if (!thread->occupied || !cmdq->shared_mem) + return -EFAULT; + + pr_debug("%s %d: pkt:%p thread:%u gce:%#lx", + __func__, __LINE__, pkt, thread->idx, (unsigned long)cmdq->base_pa); + + addr = (u32)(cmdq->base_pa + CMDQ_THR_BASE + + CMDQ_THR_SIZE * thread->idx + CMDQ_THR_EXEC_CNT_PA); + + cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX1, CMDQ_ADDR_HIGH(addr)); + cmdq_pkt_read_s(pkt, CMDQ_THR_SPR_IDX1, CMDQ_ADDR_LOW(addr), CMDQ_THR_SPR_IDX1); + + left.reg = true; + left.idx = CMDQ_THR_SPR_IDX1; + right.reg = false; + right.value = 1; + cmdq_pkt_logic_command(pkt, CMDQ_LOGIC_ADD, CMDQ_THR_SPR_IDX1, &left, &right); + + addr = cmdq->shared_mem->pa + CMDQ_SEC_SHARED_THR_CNT_OFFSET + + thread->idx * sizeof(u32); + + cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX2, CMDQ_ADDR_HIGH(addr)); + cmdq_pkt_write_s(pkt, CMDQ_THR_SPR_IDX2, CMDQ_ADDR_LOW(addr), CMDQ_THR_SPR_IDX1); + cmdq_pkt_set_event(pkt, cmdq->cmdq_event); + + return 0; +} +EXPORT_SYMBOL(cmdq_sec_insert_backup_cookie); + +static int cmdq_sec_realloc_addr_list(struct cmdq_pkt *pkt, const u32 count) +{ + struct cmdq_sec_data *sec_data = (struct cmdq_sec_data *)pkt->sec_data; + void *prev = (void *)(unsigned long)sec_data->addrMetadatas, *curr; + + if (count <= sec_data->addrMetadataMaxCount) + return 0; + + curr = kcalloc(count, sizeof(*sec_data), GFP_KERNEL); + if (!curr) + return -ENOMEM; + + if (count && sec_data->addrMetadatas) + memcpy(curr, prev, sizeof(*sec_data) * sec_data->addrMetadataMaxCount); + + kfree(prev); + + sec_data->addrMetadatas = (uintptr_t)curr; + sec_data->addrMetadataMaxCount = count; + return 0; +} + +static int cmdq_sec_check_sec(struct cmdq_pkt *pkt) +{ + struct cmdq_sec_data *sec_data; + + if (pkt->sec_data) + return 0; + + sec_data = kzalloc(sizeof(*sec_data), GFP_KERNEL); + if (!sec_data) + return -ENOMEM; + + pkt->sec_data = (void *)sec_data; + + return 0; +} + +static int cmdq_sec_append_metadata(struct cmdq_pkt *pkt, + const enum cmdq_iwc_addr_metadata_type type, + const u64 base, const u32 offset, const u32 size, + const u32 port) +{ + struct cmdq_sec_data *sec_data; + struct iwcCmdqAddrMetadata_t *meta; + int idx, max, ret; + + pr_debug("[%s %d] pkt:%p type:%u base:%#llx offset:%#x size:%#x port:%#x", + __func__, __LINE__, pkt, type, base, offset, size, port); + + ret = cmdq_sec_check_sec(pkt); + if (ret < 0) + return ret; + + sec_data = (struct cmdq_sec_data *)pkt->sec_data; + idx = sec_data->addrMetadataCount; + if (idx >= CMDQ_IWC_MAX_ADDR_LIST_LENGTH) { + pr_err("idx:%u reach over:%u", idx, CMDQ_IWC_MAX_ADDR_LIST_LENGTH); + return -EFAULT; + } + + if (!sec_data->addrMetadataMaxCount) + max = ADDR_METADATA_MAX_COUNT_ORIGIN; + else if (idx >= sec_data->addrMetadataMaxCount) + max = sec_data->addrMetadataMaxCount * 2; + else + max = sec_data->addrMetadataMaxCount; + + ret = cmdq_sec_realloc_addr_list(pkt, max); + if (ret) + return ret; + + if (!sec_data->addrMetadatas) { + pr_info("addrMetadatas is missing"); + + meta = kzalloc(sizeof(*meta), GFP_KERNEL); + if (!meta) + return -ENOMEM; + + sec_data->addrMetadatas = (uintptr_t)(void *)meta; + } + meta = (struct iwcCmdqAddrMetadata_t *)(uintptr_t)sec_data->addrMetadatas; + + meta[idx].instrIndex = pkt->cmd_buf_size / CMDQ_INST_SIZE - 1; + meta[idx].type = type; + meta[idx].baseHandle = base; + meta[idx].offset = offset; + meta[idx].size = size; + meta[idx].port = port; + sec_data->addrMetadataCount += 1; + return 0; +} + +int cmdq_sec_pkt_set_data(struct cmdq_pkt *pkt, const u64 dapc_engine, + const u64 port_sec_engine, const enum cmdq_sec_scenario scenario) +{ + struct cmdq_sec_data *sec_data; + int ret; + + if (!pkt) { + pr_err("invalid pkt:%p", pkt); + return -EINVAL; + } + + ret = cmdq_sec_check_sec(pkt); + if (ret < 0) + return ret; + + pr_debug("[%s %d] pkt:%p sec_data:%p dapc:%llu port_sec:%llu scen:%u", + __func__, __LINE__, pkt, pkt->sec_data, dapc_engine, port_sec_engine, scenario); + + sec_data = (struct cmdq_sec_data *)pkt->sec_data; + sec_data->enginesNeedDAPC |= dapc_engine; + sec_data->enginesNeedPortSecurity |= port_sec_engine; + sec_data->scenario = scenario; + + return 0; +} +EXPORT_SYMBOL(cmdq_sec_pkt_set_data); + +int cmdq_sec_pkt_write(struct cmdq_pkt *pkt, u32 addr, u64 base, + const enum cmdq_iwc_addr_metadata_type type, + const u32 offset, const u32 size, const u32 port) +{ + int ret; + + ret = cmdq_pkt_assign(pkt, CMDQ_THR_SPR_IDX0, addr); + if (ret) + return ret; + + ret = cmdq_pkt_write_s_reg_value(pkt, CMDQ_THR_SPR_IDX0, (u32)base); + if (ret) + return ret; + + return cmdq_sec_append_metadata(pkt, type, base, offset, size, port); +} +EXPORT_SYMBOL(cmdq_sec_pkt_write); + +static u32 cmdq_sec_get_cookie(struct cmdq_sec *cmdq, u32 idx) +{ + return *(u32 *)(cmdq->shared_mem->va + + CMDQ_SEC_SHARED_THR_CNT_OFFSET + idx * sizeof(u32)); +} + +static void cmdq_sec_task_done(struct cmdq_sec_task *task, int sta) +{ + struct cmdq_cb_data data; + + data.sta = sta; + data.pkt = task->pkt; + + pr_debug("%s task:%p pkt:%p err:%d", + __func__, task, task->pkt, sta); + + mbox_chan_received_data(task->thread->chan, &data); + + list_del_init(&task->list_entry); + kfree(task); +} + +static bool cmdq_sec_irq_handler(struct cmdq_sec_thread *thread, const u32 cookie, const int err) +{ + struct cmdq_sec_task *task, *temp, *cur_task = NULL; + struct cmdq_sec *cmdq = container_of(thread->chan->mbox, struct cmdq_sec, mbox); + unsigned long flags; + int done; + + spin_lock_irqsave(&thread->chan->lock, flags); + if (thread->wait_cookie <= cookie) + done = cookie - thread->wait_cookie + 1; + else if (thread->wait_cookie == (cookie + 1) % CMDQ_MAX_COOKIE_VALUE) + done = 0; + else + done = CMDQ_MAX_COOKIE_VALUE - thread->wait_cookie + 1 + + cookie + 1; + + list_for_each_entry_safe(task, temp, &thread->task_list, list_entry) { + if (!done) + break; + + cmdq_sec_task_done(task, err); + + if (thread->task_cnt) + thread->task_cnt -= 1; + + done--; + } + + cur_task = list_first_entry_or_null(&thread->task_list, + struct cmdq_sec_task, list_entry); + + if (err && cur_task) { + spin_unlock_irqrestore(&thread->chan->lock, flags); + + /* for error task, cancel, callback and done */ + memset(&cmdq->cancel, 0, sizeof(cmdq->cancel)); + cmdq_sec_task_submit(cmdq, cur_task, CMD_CMDQ_IWC_CANCEL_TASK, + thread->idx, &cmdq->cancel); + + cmdq_sec_task_done(task, err); + + spin_lock_irqsave(&thread->chan->lock, flags); + + task = list_first_entry_or_null(&thread->task_list, + struct cmdq_sec_task, list_entry); + if (cur_task == task) + cmdq_sec_task_done(cur_task, err); + else + pr_err("task list changed"); + + /* + * error case stop all task for secure, + * since secure tdrv always remove all when cancel + */ + while (!list_empty(&thread->task_list)) { + cur_task = list_first_entry(&thread->task_list, + struct cmdq_sec_task, list_entry); + + cmdq_sec_task_done(cur_task, -ECONNABORTED); + } + } else if (err) { + pr_debug("error but all task done, check notify callback"); + } + + if (list_empty(&thread->task_list)) { + thread->wait_cookie = 0; + thread->next_cookie = 0; + thread->task_cnt = 0; + __raw_writel(0, (void __iomem *)cmdq->shared_mem->va + + CMDQ_SEC_SHARED_THR_CNT_OFFSET + + thread->idx * sizeof(u32)); + spin_unlock_irqrestore(&thread->chan->lock, flags); + del_timer(&thread->timeout); + return true; + } + + thread->wait_cookie = cookie % CMDQ_MAX_COOKIE_VALUE + 1; + + mod_timer(&thread->timeout, jiffies + msecs_to_jiffies(thread->timeout_ms)); + spin_unlock_irqrestore(&thread->chan->lock, flags); + + return false; +} + +static void cmdq_sec_irq_notify_work(struct work_struct *work_item) +{ + struct cmdq_sec *cmdq = container_of(work_item, struct cmdq_sec, irq_notify_work); + int i; + + mutex_lock(&cmdq->exec_lock); + + for (i = 0; i < CMDQ_MAX_SECURE_THREAD_COUNT; i++) { + struct cmdq_sec_thread *thread = &cmdq->thread[CMDQ_MIN_SECURE_THREAD_ID + i]; + u32 cookie = cmdq_sec_get_cookie(cmdq, thread->idx); + + if (cookie < thread->wait_cookie || !thread->task_cnt) + continue; + + cmdq_sec_irq_handler(thread, cookie, 0); + } + + mutex_unlock(&cmdq->exec_lock); +} + +static void cmdq_sec_irq_notify_callback(struct mbox_client *cl, void *mssg) +{ + struct cmdq_cb_data *data = (struct cmdq_cb_data *)mssg; + struct cmdq_sec *cmdq = container_of(((struct cmdq_client *)data->pkt->cl)->chan->mbox, + struct cmdq_sec, mbox); + + if (!work_pending(&cmdq->irq_notify_work)) + queue_work(cmdq->notify_wq, &cmdq->irq_notify_work); + else + pr_debug("%s last notify callback working", __func__); +} + +static int cmdq_sec_irq_notify_start(struct cmdq_sec *cmdq) +{ + int err; + + if (cmdq->notify_run) + return 0; + + if (!cmdq->clt_pkt) { + cmdq->clt = cmdq_mbox_create(cmdq->mbox.dev, 0); + if (!cmdq->clt || IS_ERR(cmdq->clt)) { + pr_err("clt mbox_create failed clt:%p index:%d", + cmdq->clt, CMDQ_SEC_IRQ_THREAD); + return -EINVAL; + } + cmdq->clt->client.rx_callback = cmdq_sec_irq_notify_callback; + + cmdq->clt_pkt = cmdq_pkt_create(cmdq->clt, CMDQ_BUF_ALLOC_SIZE); + if (!cmdq->clt_pkt || IS_ERR(cmdq->clt_pkt)) { + pr_err("clt_pkt cmdq_pkt_create failed pkt:%p index:%d", + cmdq->clt_pkt, CMDQ_SEC_IRQ_THREAD); + return -EINVAL; + } + + INIT_WORK(&cmdq->irq_notify_work, cmdq_sec_irq_notify_work); + } + + cmdq_pkt_wfe(cmdq->clt_pkt, cmdq->cmdq_event, true); + cmdq_pkt_finalize_loop(cmdq->clt_pkt); + dma_sync_single_for_device(cmdq->mbox.dev, + cmdq->clt_pkt->pa_base, + cmdq->clt_pkt->cmd_buf_size, + DMA_TO_DEVICE); + err = mbox_send_message(cmdq->clt->chan, cmdq->clt_pkt); + mbox_client_txdone(cmdq->clt->chan, 0); + if (err < 0) { + pr_err("%s failed:%d", __func__, err); + cmdq_pkt_destroy(cmdq->clt_pkt); + cmdq_mbox_destroy(cmdq->clt); + } else { + cmdq->notify_run = true; + pr_debug("%s success!", __func__); + } + + return err; +} + +static int cmdq_sec_session_init(struct cmdq_sec_context *context) +{ + int err = 0; + + if (context->state >= IWC_SES_OPENED) { + pr_debug("session opened:%u", context->state); + return err; + } + + switch (context->state) { + case IWC_INIT: + err = cmdq_sec_init_context_base(context); + if (err) + break; + context->state = IWC_CONTEXT_INITED; + fallthrough; + case IWC_CONTEXT_INITED: + if (context->iwc_msg) { + pr_err("iwcMessage not NULL:%p", context->iwc_msg); + err = -EINVAL; + break; + } + + err = cmdq_sec_allocate_wsm(&context->tee, &context->iwc_msg, + sizeof(struct iwcCmdqMessage_t)); + if (err) + break; + + context->state = IWC_WSM_ALLOCATED; + fallthrough; + case IWC_WSM_ALLOCATED: + err = cmdq_sec_open_session(&context->tee, context->iwc_msg); + if (err) + break; + + context->state = IWC_SES_OPENED; + fallthrough; + default: + break; + } + return err; +} + +static int cmdq_sec_fill_iwc_msg(struct cmdq_sec_context *context, + struct cmdq_sec_task *task, u32 thrd_idx) +{ + struct iwcCmdqMessage_t *iwc_msg = NULL; + struct cmdq_sec_data *data = (struct cmdq_sec_data *)task->pkt->sec_data; + u32 size = 0, offset = 0, *instr; + + iwc_msg = (struct iwcCmdqMessage_t *)context->iwc_msg; + + if (task->pkt->cmd_buf_size + 4 * CMDQ_INST_SIZE > CMDQ_TZ_CMD_BLOCK_SIZE) { + pr_err("task:%p size:%zu > %u", + task, task->pkt->cmd_buf_size, CMDQ_TZ_CMD_BLOCK_SIZE); + return -EFAULT; + } + + if (thrd_idx == CMDQ_INVALID_THREAD) { + iwc_msg->command.commandSize = 0; + iwc_msg->command.metadata.addrListLength = 0; + return 0; + } + + iwc_msg->command.thread = thrd_idx; + iwc_msg->command.scenario = task->scenario; + iwc_msg->command.engineFlag = task->engineFlag; + size = task->pkt->cmd_buf_size; + memcpy(iwc_msg->command.pVABase + offset, task->pkt->va_base, size); + iwc_msg->command.commandSize += size; + offset += size / 4; + + if (iwc_msg->command.commandSize == 0) { + pr_err("%s %d: commandSize is 0\n", __func__, __LINE__); + return 0; + } + + instr = &iwc_msg->command.pVABase[iwc_msg->command.commandSize / 4 - 4]; + if (instr[0] == 0x1 && instr[1] == 0x40000000) + instr[0] = 0; + else + pr_err("%s %d: find EOC failed: %#x %#x", + __func__, __LINE__, instr[1], instr[0]); + + iwc_msg->command.waitCookie = task->waitCookie; + iwc_msg->command.resetExecCnt = task->resetExecCnt; + + if (data->addrMetadataCount) { + iwc_msg->command.metadata.addrListLength = data->addrMetadataCount; + memcpy(iwc_msg->command.metadata.addrList, + (u32 *)(unsigned long)data->addrMetadatas, + data->addrMetadataCount * sizeof(struct iwcCmdqAddrMetadata_t)); + } + + iwc_msg->command.metadata.enginesNeedDAPC = data->enginesNeedDAPC; + iwc_msg->command.metadata.enginesNeedPortSecurity = + data->enginesNeedPortSecurity; + iwc_msg->command.hNormalTask = (unsigned long)task->pkt; + + return 0; +} + +static int cmdq_sec_session_send(struct cmdq_sec_context *context, + struct cmdq_sec_task *task, const u32 iwc_cmd, + const u32 thrd_idx, struct cmdq_sec *cmdq) +{ + int err = 0; + u64 cost; + struct iwcCmdqMessage_t *iwc_msg = NULL; + + iwc_msg = (struct iwcCmdqMessage_t *)context->iwc_msg; + + memset(iwc_msg, 0, sizeof(*iwc_msg)); + iwc_msg->cmd = iwc_cmd; + iwc_msg->cmdq_id = cmdq->hwid; + iwc_msg->command.thread = thrd_idx; + + switch (iwc_cmd) { + case CMD_CMDQ_IWC_SUBMIT_TASK: + err = cmdq_sec_fill_iwc_msg(context, task, thrd_idx); + if (err) + return err; + break; + case CMD_CMDQ_IWC_CANCEL_TASK: + iwc_msg->cancelTask.waitCookie = task->waitCookie; + iwc_msg->cancelTask.thread = thrd_idx; + break; + case CMD_CMDQ_IWC_PATH_RES_ALLOCATE: + if (!cmdq->shared_mem || !cmdq->shared_mem->va) { + pr_err("%s %d: shared_mem is NULL", __func__, __LINE__); + return -EFAULT; + } + iwc_msg->pathResource.size = cmdq->shared_mem->size; + iwc_msg->pathResource.shareMemoyPA = cmdq->shared_mem->pa; + iwc_msg->pathResource.useNormalIRQ = 1; + break; + default: + break; + } + + cmdq->sec_invoke = sched_clock(); + pr_debug("%s execute cmdq:%p task:%lx command:%u thread:%u cookie:%d", + __func__, cmdq, (unsigned long)task, iwc_cmd, thrd_idx, + task ? task->waitCookie : -1); + + /* send message */ + err = cmdq_sec_execute_session(&context->tee, iwc_cmd, CMDQ_TIMEOUT_DEFAULT); + + cmdq->sec_done = sched_clock(); + cost = div_u64(cmdq->sec_done - cmdq->sec_invoke, 1000000); + if (cost >= CMDQ_TIMEOUT_DEFAULT) + pr_err("%s execute timeout cmdq:%p task:%lx cost:%lluus", + __func__, cmdq, (unsigned long)task, cost); + else + pr_debug("%s execute done cmdq:%p task:%lx cost:%lluus", + __func__, cmdq, (unsigned long)task, cost); + + if (err == 0) + context->state = IWC_SES_ON_TRANSACTED; + + return err; +} + +static int cmdq_sec_session_reply(const u32 iwc_cmd, struct iwcCmdqMessage_t *iwc_msg, + void *data, struct cmdq_sec_task *task) +{ + struct iwcCmdqCancelTask_t *cancel = data; + struct cmdq_sec_data *sec_data = task->pkt->sec_data; + + if (iwc_cmd == CMD_CMDQ_IWC_SUBMIT_TASK) { + if (iwc_msg->rsp < 0) { + /* submit fail case copy status */ + memcpy(&sec_data->sec_status, &iwc_msg->secStatus, + sizeof(sec_data->sec_status)); + sec_data->response = iwc_msg->rsp; + } + } else if (iwc_cmd == CMD_CMDQ_IWC_CANCEL_TASK && cancel) { + /* cancel case only copy cancel result */ + memcpy(cancel, &iwc_msg->cancelTask, sizeof(*cancel)); + } + + return iwc_msg->rsp; +} + +static int cmdq_sec_task_submit(struct cmdq_sec *cmdq, struct cmdq_sec_task *task, + const u32 iwc_cmd, const u32 thrd_idx, void *data) +{ + struct cmdq_sec_context *context; + int err; + + do { + if (!cmdq->context) { + context = kzalloc(sizeof(*cmdq->context), GFP_ATOMIC); + if (!context) { + err = -ENOMEM; + break; + } + cmdq->context = context; + cmdq->context->state = IWC_INIT; + cmdq->context->tgid = current->tgid; + } + + if (cmdq->context->state == IWC_INIT) + cmdq_sec_setup_tee_context_base(cmdq->context); + + err = cmdq_sec_session_init(cmdq->context); + if (err) { + pr_err("%s %d: cmdq_sec_session_init fail", __func__, __LINE__); + break; + } + + err = cmdq_sec_irq_notify_start(cmdq); + if (err < 0) { + pr_err("%s %d: cmdq_sec_irq_notify_start fail", __func__, __LINE__); + break; + } + + err = cmdq_sec_session_send(cmdq->context, task, iwc_cmd, thrd_idx, cmdq); + if (err) + pr_err("%s %d: cmdq_sec_session_send fail: %d\n", __func__, __LINE__, err); + else + err = cmdq_sec_session_reply(iwc_cmd, cmdq->context->iwc_msg, data, task); + } while (0); + + if (err) + pr_err("%s %d: sec invoke err:%d task:%p thread:%u gce:%#lx", + __func__, __LINE__, err, task, thrd_idx, (unsigned long)cmdq->base_pa); + + return err; +} + +static int cmdq_sec_suspend(struct device *dev) +{ + struct cmdq_sec *cmdq = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(cmdq->gce_num, cmdq->clocks); + return 0; +} + +static int cmdq_sec_resume(struct device *dev) +{ + struct cmdq_sec *cmdq = dev_get_drvdata(dev); + + WARN_ON(clk_bulk_prepare_enable(cmdq->gce_num, cmdq->clocks)); + return 0; +} + +static const struct dev_pm_ops cmdq_sec_pm_ops = { + .suspend = cmdq_sec_suspend, + .resume = cmdq_sec_resume, +}; + +static void cmdq_sec_task_exec_work(struct work_struct *work_item) +{ + struct cmdq_sec_task *task = container_of(work_item, struct cmdq_sec_task, exec_work); + struct cmdq_sec *cmdq = container_of(task->thread->chan->mbox, struct cmdq_sec, mbox); + struct cmdq_sec_data *data; + unsigned long flags; + int err; + + pr_debug("%s gce:%#lx task:%p pkt:%p thread:%u", + __func__, (unsigned long)cmdq->base_pa, task, task->pkt, task->thread->idx); + + if (!task->pkt->sec_data) { + pr_err("pkt:%p without sec_data", task->pkt); + return; + } + data = (struct cmdq_sec_data *)task->pkt->sec_data; + + mutex_lock(&cmdq->exec_lock); + + spin_lock_irqsave(&task->thread->chan->lock, flags); + if (!task->thread->task_cnt) { + mod_timer(&task->thread->timeout, jiffies + + msecs_to_jiffies(task->thread->timeout_ms)); + task->thread->wait_cookie = 1; + task->thread->next_cookie = 1; + task->thread->task_cnt = 0; + __raw_writel(0, (void __iomem *)cmdq->shared_mem->va + + CMDQ_SEC_SHARED_THR_CNT_OFFSET + + task->thread->idx * sizeof(u32)); + } + + task->resetExecCnt = task->thread->task_cnt ? false : true; + task->waitCookie = task->thread->next_cookie; + task->thread->next_cookie = (task->thread->next_cookie + 1) % CMDQ_MAX_COOKIE_VALUE; + list_add_tail(&task->list_entry, &task->thread->task_list); + task->thread->task_cnt += 1; + spin_unlock_irqrestore(&task->thread->chan->lock, flags); + task->trigger = sched_clock(); + + if (!atomic_cmpxchg(&cmdq_path_res, 0, 1)) { + err = cmdq_sec_task_submit(cmdq, NULL, CMD_CMDQ_IWC_PATH_RES_ALLOCATE, + CMDQ_INVALID_THREAD, NULL); + if (err) { + atomic_set(&cmdq_path_res, 0); + goto task_err_callback; + } + } + + if (task->thread->task_cnt > CMDQ_MAX_TASK_IN_SECURE_THREAD) { + pr_err("task_cnt:%u cannot more than %u task:%p thrd-idx:%u", + task->thread->task_cnt, CMDQ_MAX_TASK_IN_SECURE_THREAD, + task, task->thread->idx); + err = -EMSGSIZE; + goto task_err_callback; + } + + err = cmdq_sec_task_submit(cmdq, task, CMD_CMDQ_IWC_SUBMIT_TASK, task->thread->idx, NULL); + if (err) + pr_err("task submit CMD_CMDQ_IWC_SUBMIT_TASK failed:%d gce:%#lx task:%p thread:%u", + err, (unsigned long)cmdq->base_pa, task, task->thread->idx); + +task_err_callback: + if (err) { + struct cmdq_cb_data cb_data; + + cb_data.sta = err; + cb_data.pkt = task->pkt; + mbox_chan_received_data(task->thread->chan, &cb_data); + + spin_lock_irqsave(&task->thread->chan->lock, flags); + if (!task->thread->task_cnt) + pr_err("thread:%u task_cnt:%u cannot below zero", + task->thread->idx, task->thread->task_cnt); + else + task->thread->task_cnt -= 1; + + task->thread->next_cookie = (task->thread->next_cookie - 1 + + CMDQ_MAX_COOKIE_VALUE) % CMDQ_MAX_COOKIE_VALUE; + list_del(&task->list_entry); + pr_debug("gce:%#lx err:%d task:%p pkt:%p thread:%u task_cnt:%u wait_cookie:%u next_cookie:%u", + (unsigned long)cmdq->base_pa, err, task, task->pkt, + task->thread->idx, task->thread->task_cnt, + task->thread->wait_cookie, task->thread->next_cookie); + spin_unlock_irqrestore(&task->thread->chan->lock, flags); + kfree(task); + } + mutex_unlock(&cmdq->exec_lock); +} + +static int cmdq_sec_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; + struct cmdq_sec_data *sec_data = (struct cmdq_sec_data *)pkt->sec_data; + struct cmdq_sec_thread *thread = (struct cmdq_sec_thread *)chan->con_priv; + struct cmdq_sec_task *task; + + if (!sec_data) + return -EINVAL; + + task = kzalloc(sizeof(*task), GFP_ATOMIC); + if (!task) + return -ENOMEM; + + task->pkt = pkt; + task->thread = thread; + task->scenario = sec_data->scenario; + task->engineFlag = sec_data->enginesNeedDAPC | sec_data->enginesNeedPortSecurity; + + INIT_WORK(&task->exec_work, cmdq_sec_task_exec_work); + queue_work(thread->task_exec_wq, &task->exec_work); + return 0; +} + +static void cmdq_sec_thread_timeout(struct timer_list *t) +{ + struct cmdq_sec_thread *thread = from_timer(thread, t, timeout); + struct cmdq_sec *cmdq = container_of(thread->chan->mbox, struct cmdq_sec, mbox); + + if (!work_pending(&thread->timeout_work)) + queue_work(cmdq->timeout_wq, &thread->timeout_work); +} + +static void cmdq_sec_task_timeout_work(struct work_struct *work_item) +{ + struct cmdq_sec_thread *thread = container_of(work_item, struct cmdq_sec_thread, + timeout_work); + struct cmdq_sec *cmdq = container_of(thread->chan->mbox, struct cmdq_sec, mbox); + struct cmdq_sec_task *task; + unsigned long flags; + u64 duration; + u32 cookie; + + mutex_lock(&cmdq->exec_lock); + + spin_lock_irqsave(&thread->chan->lock, flags); + if (list_empty(&thread->task_list)) { + pr_err("thread:%u task_list is empty", thread->idx); + spin_unlock_irqrestore(&thread->chan->lock, flags); + goto done; + } + + task = list_first_entry(&thread->task_list, struct cmdq_sec_task, list_entry); + duration = div_u64(sched_clock() - task->trigger, 1000000); + if (duration < thread->timeout_ms) { + mod_timer(&thread->timeout, jiffies + + msecs_to_jiffies(thread->timeout_ms - duration)); + spin_unlock_irqrestore(&thread->chan->lock, flags); + goto done; + } + + cookie = cmdq_sec_get_cookie(cmdq, thread->idx); + spin_unlock_irqrestore(&thread->chan->lock, flags); + + pr_err("%s duration:%llu cookie:%u thread:%u", + __func__, duration, cookie, thread->idx); + cmdq_sec_irq_handler(thread, cookie, -ETIMEDOUT); + +done: + mutex_unlock(&cmdq->exec_lock); +} + +static int cmdq_sec_mbox_startup(struct mbox_chan *chan) +{ + struct cmdq_sec_thread *thread = (struct cmdq_sec_thread *)chan->con_priv; + char name[20]; + + timer_setup(&thread->timeout, cmdq_sec_thread_timeout, 0); + + INIT_WORK(&thread->timeout_work, cmdq_sec_task_timeout_work); + snprintf(name, sizeof(name), "task_exec_wq_%u", thread->idx); + thread->task_exec_wq = create_singlethread_workqueue(name); + thread->occupied = true; + return 0; +} + +static void cmdq_sec_mbox_shutdown(struct mbox_chan *chan) +{ + struct cmdq_sec_thread *thread = (struct cmdq_sec_thread *)chan->con_priv; + + thread->occupied = false; +} + +static int cmdq_sec_mbox_flush(struct mbox_chan *chan, unsigned long timeout) +{ + struct cmdq_sec_thread *thread = (struct cmdq_sec_thread *)chan->con_priv; + struct cmdq_sec *cmdq = container_of(thread->chan->mbox, struct cmdq_sec, mbox); + int i; + + mutex_lock(&cmdq->exec_lock); + + if (list_empty(&thread->task_list)) + goto out; + + for (i = 0; i < CMDQ_MAX_SECURE_THREAD_COUNT; i++) { + struct cmdq_sec_thread *thread = &cmdq->thread[CMDQ_MIN_SECURE_THREAD_ID + i]; + u32 cookie = cmdq_sec_get_cookie(cmdq, thread->idx); + + if (cookie < thread->wait_cookie || !thread->task_cnt) + continue; + + cmdq_sec_irq_handler(thread, cookie, -ECONNABORTED); + } + +out: + mutex_unlock(&cmdq->exec_lock); + return 0; +} + +static bool cmdq_sec_mbox_last_tx_done(struct mbox_chan *chan) +{ + return true; +} + +static const struct mbox_chan_ops cmdq_sec_mbox_chan_ops = { + .send_data = cmdq_sec_mbox_send_data, + .startup = cmdq_sec_mbox_startup, + .shutdown = cmdq_sec_mbox_shutdown, + .flush = cmdq_sec_mbox_flush, + .last_tx_done = cmdq_sec_mbox_last_tx_done, +}; + +static struct mbox_chan *cmdq_sec_mbox_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + struct cmdq_sec_thread *thread; + int idx = sp->args[0]; + + if (mbox->num_chans <= idx) { + pr_err("invalid thrd-idx:%u", idx); + return ERR_PTR(-EINVAL); + } + + thread = (struct cmdq_sec_thread *)mbox->chans[idx].con_priv; + thread->chan = &mbox->chans[idx]; + thread->timeout_ms = CMDQ_NO_TIMEOUT; + thread->priority = sp->args[1]; + + return &mbox->chans[idx]; +} + +static int cmdq_sec_probe(struct platform_device *pdev) +{ + int i, err; + struct cmdq_sec *cmdq; + struct cmdq_sec_plat *plat_data; + struct device *dev = &pdev->dev; + + plat_data = (struct cmdq_sec_plat *)pdev->dev.platform_data; + if (!plat_data) { + dev_err(dev, "no valid platform data!\n"); + return -EINVAL; + } + + cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL); + if (!cmdq) + return -ENOMEM; + + cmdq->base_pa = plat_data->base_pa; + cmdq->base = plat_data->base; + cmdq->thread_nr = plat_data->thread_nr; + cmdq->gce_num = plat_data->gce_num; + cmdq->clocks = devm_kcalloc(dev, cmdq->gce_num, + sizeof(struct clk_bulk_data), GFP_KERNEL); + if (!cmdq->clocks) + return -ENOMEM; + + for (i = 0 ; i < cmdq->gce_num; i++) + cmdq->clocks[i] = plat_data->clocks[i]; + + cmdq->hwid = plat_data->hwid; + cmdq->cmdq_event = plat_data->cmdq_event; + + cmdq->mbox.dev = plat_data->gce_dev; + cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr, + sizeof(*cmdq->mbox.chans), GFP_KERNEL); + if (!cmdq->mbox.chans) + return -ENOMEM; + + cmdq->mbox.ops = &cmdq_sec_mbox_chan_ops; + cmdq->mbox.num_chans = cmdq->thread_nr; + cmdq->mbox.of_xlate = cmdq_sec_mbox_of_xlate; + + /* make use of TXDONE_BY_ACK */ + cmdq->mbox.txdone_irq = false; + cmdq->mbox.txdone_poll = false; + + cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr, + sizeof(*cmdq->thread), GFP_KERNEL); + if (!cmdq->thread) + return -ENOMEM; + + mutex_init(&cmdq->exec_lock); + for (i = 0; i < cmdq->thread_nr; i++) { + cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE + CMDQ_THR_SIZE * i; + INIT_LIST_HEAD(&cmdq->thread[i].task_list); + cmdq->thread[i].idx = i; + cmdq->thread[i].occupied = false; + cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i]; + } + + cmdq->notify_wq = create_singlethread_workqueue("mtk_cmdq_sec_notify_wq"); + cmdq->timeout_wq = create_singlethread_workqueue("mtk_cmdq_sec_timeout_wq"); + err = devm_mbox_controller_register(dev, &cmdq->mbox); + if (err) + return err; + + cmdq->shared_mem = devm_kzalloc(dev, sizeof(*cmdq->shared_mem), GFP_KERNEL); + if (!cmdq->shared_mem) + return -ENOMEM; + + cmdq->shared_mem->va = dma_alloc_coherent(dev, PAGE_SIZE, + &cmdq->shared_mem->pa, GFP_KERNEL); + cmdq->shared_mem->size = PAGE_SIZE; + + platform_set_drvdata(pdev, cmdq); + WARN_ON(clk_bulk_prepare_enable(cmdq->gce_num, cmdq->clocks)); + + return 0; +} + +static int cmdq_sec_remove(struct platform_device *pdev) +{ + struct cmdq_sec *cmdq = platform_get_drvdata(pdev); + + if (cmdq->context) + cmdq_sec_free_wsm(&cmdq->context->tee, &cmdq->context->iwc_msg); + + mbox_controller_unregister(&cmdq->mbox); + + clk_bulk_disable_unprepare(cmdq->gce_num, cmdq->clocks); + return 0; +} + +static struct platform_driver cmdq_sec_drv = { + .probe = cmdq_sec_probe, + .remove = cmdq_sec_remove, + .driver = { + .name = "mtk_cmdq_sec", + .pm = &cmdq_sec_pm_ops, + }, +}; + +static int __init cmdq_sec_init(void) +{ + int err; + + err = platform_driver_register(&cmdq_sec_drv); + if (err) + pr_err("platform_driver_register failed:%d", err); + return err; +} + +arch_initcall(cmdq_sec_init); + +MODULE_LICENSE("GPL"); diff --git a/drivers/mailbox/mtk-cmdq-sec-tee.c b/drivers/mailbox/mtk-cmdq-sec-tee.c new file mode 100644 index 000000000000..e42e9dba343c --- /dev/null +++ b/drivers/mailbox/mtk-cmdq-sec-tee.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2019 MediaTek Inc. + +#include +#include + +#include +#include + +/* lock to protect atomic secure task execution */ +static DEFINE_MUTEX(cmdq_sec_exec_lock); + +static void cmdq_sec_lock_secure_path(void) +{ + mutex_lock(&cmdq_sec_exec_lock); + smp_mb(); /*memory barrier*/ +} + +static void cmdq_sec_unlock_secure_path(void) +{ + mutex_unlock(&cmdq_sec_exec_lock); +} + +void cmdq_sec_setup_tee_context(struct cmdq_sec_tee_context *tee) +{ + /* 09010000 0000 0000 0000000000000000 */ + memset(tee->uuid, 0, sizeof(tee->uuid)); + tee->uuid[0] = 0x9; + tee->uuid[1] = 0x1; +} +EXPORT_SYMBOL(cmdq_sec_setup_tee_context); + +#if IS_ENABLED(CONFIG_TEE) +static int tee_dev_match(struct tee_ioctl_version_data *t, const void *v) +{ +#if IS_ENABLED(CONFIG_OPTEE) + if (t->impl_id == TEE_IMPL_ID_OPTEE) + return 1; +#endif + return 0; +} +#endif + +int cmdq_sec_init_context(struct cmdq_sec_tee_context *tee) +{ + int status; + +#if IS_ENABLED(CONFIG_TEE) + tee->tee_context = tee_client_open_context(NULL, tee_dev_match, NULL, NULL); +#endif + if (tee->tee_context) + status = 0; + else + status = -EINVAL; + + pr_info("[%s][%d]status=%d\n", __func__, __LINE__, status); + + return status; +} +EXPORT_SYMBOL(cmdq_sec_init_context); + +int cmdq_sec_deinit_context(struct cmdq_sec_tee_context *tee) +{ +#if IS_ENABLED(CONFIG_TEE) + if (tee) + tee_client_close_context(tee->tee_context); +#endif + return 0; +} +EXPORT_SYMBOL(cmdq_sec_deinit_context); + +int cmdq_sec_allocate_wsm(struct cmdq_sec_tee_context *tee, void **wsm_buffer, u32 size) +{ + void *buffer; + + if (!wsm_buffer) + return -EINVAL; + + if (!size) + size = 8; + + buffer = kmalloc(size, GFP_KERNEL); + if (!buffer) + return -EINVAL; + +#if IS_ENABLED(CONFIG_TEE) + tee->shared_mem = tee_shm_register_kernel_buf(tee->tee_context, + buffer, + size); +#endif + if (!tee->shared_mem) { + kfree(buffer); + return -EINVAL; + } + + *wsm_buffer = buffer; + + return 0; +} +EXPORT_SYMBOL(cmdq_sec_allocate_wsm); + +int cmdq_sec_free_wsm(struct cmdq_sec_tee_context *tee, void **wsm_buffer) +{ + if (!wsm_buffer) + return -EINVAL; + +#if IS_ENABLED(CONFIG_TEE) + tee_shm_put(tee->shared_mem); +#endif + tee->shared_mem = NULL; + kfree(*wsm_buffer); + *wsm_buffer = NULL; + + return 0; +} +EXPORT_SYMBOL(cmdq_sec_free_wsm); + +int cmdq_sec_open_session(struct cmdq_sec_tee_context *tee, void *wsm_buffer) +{ + struct tee_ioctl_open_session_arg osarg; + struct tee_param params; + int rc = 0; + + if (!wsm_buffer) + return -EINVAL; + + memset(¶ms, 0, sizeof(struct tee_param)); + + memset(&osarg, 0, sizeof(osarg)); + osarg.num_params = 1; + memcpy(osarg.uuid, tee->uuid, sizeof(osarg.uuid)); + osarg.clnt_login = 0; +#if IS_ENABLED(CONFIG_TEE) + rc = tee_client_open_session(tee->tee_context, &osarg, ¶ms); +#endif + if (rc) + return -EINVAL; + + if (!osarg.ret) + tee->session = osarg.session; + + return 0; +} +EXPORT_SYMBOL(cmdq_sec_open_session); + +int cmdq_sec_close_session(struct cmdq_sec_tee_context *tee) +{ +#if IS_ENABLED(CONFIG_TEE) + tee_client_close_session(tee->tee_context, tee->session); +#endif + return 0; +} +EXPORT_SYMBOL(cmdq_sec_close_session); + +int cmdq_sec_execute_session(struct cmdq_sec_tee_context *tee, u32 cmd, s32 timeout_ms) +{ + int status; + struct tee_ioctl_invoke_arg ivarg; + struct tee_param params; + u64 ts = sched_clock(); + int rc = 0; + + cmdq_sec_lock_secure_path(); + + memset(¶ms, 0, sizeof(struct tee_param)); + params.attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT; + params.u.memref.shm = tee->shared_mem; + params.u.memref.shm_offs = 0; + params.u.memref.size = tee->shared_mem->size; + + memset(&ivarg, 0, sizeof(ivarg)); + ivarg.num_params = 1; + ivarg.session = tee->session; + ivarg.func = cmd; + +#if IS_ENABLED(CONFIG_TEE) + rc = tee_client_invoke_func(tee->tee_context, &ivarg, ¶ms); +#endif + if (rc) { + pr_err("tee_client_invoke_func failed, ret=%d\n", rc); + return -EINVAL; + } + + status = ivarg.ret; + + cmdq_sec_unlock_secure_path(); + + ts = div_u64(sched_clock() - ts, 1000000); + + if (status != 0) + pr_err("[SEC]execute: TEEC_InvokeCommand:%u err:%d cost:%lluus", cmd, status, ts); + else if (ts > timeout_ms) + pr_err("[SEC]execute: TEEC_InvokeCommand:%u ret:%d cost:%lluus", cmd, status, ts); + else + pr_debug("[SEC]execute: TEEC_InvokeCommand:%u ret:%d cost:%lluus", cmd, status, ts); + + return status; +} +EXPORT_SYMBOL(cmdq_sec_execute_session); + +MODULE_LICENSE("GPL"); diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h index fdda995a69ce..997a75c529fb 100644 --- a/include/linux/mailbox/mtk-cmdq-mailbox.h +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h @@ -7,6 +7,7 @@ #ifndef __MTK_CMDQ_MAILBOX_H__ #define __MTK_CMDQ_MAILBOX_H__ +#include #include #include #include @@ -77,6 +78,7 @@ struct cmdq_pkt { size_t buf_size; /* real buffer size */ void *cl; bool loop; + void *sec_data; }; struct cmdq_sec_plat { diff --git a/include/linux/mailbox/mtk-cmdq-sec-iwc-common.h b/include/linux/mailbox/mtk-cmdq-sec-iwc-common.h new file mode 100644 index 000000000000..addc515df279 --- /dev/null +++ b/include/linux/mailbox/mtk-cmdq-sec-iwc-common.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef __CMDQ_SEC_IWC_COMMON_H__ +#define __CMDQ_SEC_IWC_COMMON_H__ + +/* + * shared DRAM + * bit x = 1 means thread x raise IRQ + */ +#define CMDQ_SEC_SHARED_IRQ_RAISED_OFFSET 0 +#define CMDQ_SEC_SHARED_THR_CNT_OFFSET 0x100 +#define CMDQ_SEC_SHARED_TASK_VA_OFFSET 0x200 +#define CMDQ_SEC_SHARED_OP_OFFSET 0x300 +#define CMDQ_SEC_SHARED_SUSPEND_CNT 0x304 +#define CMDQ_SEC_SHARED_RESET_CNT 0x308 + +/* commanad buffer & metadata */ +#define CMDQ_TZ_CMD_BLOCK_SIZE (20 << 12) /* MDP readback may request 20 pages */ +#define CMDQ_IWC_MAX_CMD_LENGTH (CMDQ_TZ_CMD_BLOCK_SIZE / 4) + +#define CMDQ_IWC_MAX_ADDR_LIST_LENGTH (30) + +#define CMDQ_IWC_CLIENT_NAME (16) + +#define CMDQ_SEC_MESSAGE_INST_LEN (8) +#define CMDQ_SEC_DISPATCH_LEN (8) +#define CMDQ_MAX_READBACK_ENG (8) + +/* + * Command IDs for normal world(TLC or linux kernel) to secure world + */ +/* submit current task */ +#define CMD_CMDQ_IWC_SUBMIT_TASK (1) +/* (not used)release resource in secure path per session */ +#define CMD_CMDQ_IWC_RES_RELEASE (2) +/* cancel current task */ +#define CMD_CMDQ_IWC_CANCEL_TASK (3) +/* create global resource for secure path */ +#define CMD_CMDQ_IWC_PATH_RES_ALLOCATE (4) +/* destroy globacl resource for secure path */ +#define CMD_CMDQ_IWC_PATH_RES_RELEASE (5) + +/* + * ERROR code number (ERRNO) + * note the error result returns negative value, i.e, -(ERRNO) + */ +#define CMDQ_ERR_NOMEM (12) /* out of memory */ +#define CMDQ_ERR_FAULT (14) /* bad address */ + +#define CMDQ_ERR_ADDR_CONVERT_HANDLE_2_PA (1000) +#define CMDQ_ERR_ADDR_CONVERT_ALLOC_MVA (1100) +#define CMDQ_ERR_ADDR_CONVERT_ALLOC_MVA_N2S (1101) +#define CMDQ_ERR_ADDR_CONVERT_FREE_MVA (1200) +#define CMDQ_ERR_PORT_CONFIG (1300) + +/* param check */ +#define CMDQ_ERR_UNKNOWN_ADDR_METADATA_TYPE (1400) +#define CMDQ_ERR_TOO_MANY_SEC_HANDLE (1401) +/* security check */ +#define CMDQ_ERR_SECURITY_INVALID_INSTR (1500) +#define CMDQ_ERR_SECURITY_INVALID_SEC_HANDLE (1501) +#define CMDQ_ERR_SECURITY_INVALID_DAPC_FALG (1502) +#define CMDQ_ERR_INSERT_DAPC_INSTR_FAILED (1503) +#define CMDQ_ERR_INSERT_PORT_SECURITY_INSTR_FAILED (1504) +#define CMDQ_ERR_INVALID_SECURITY_THREAD (1505) +#define CMDQ_ERR_PATH_RESOURCE_NOT_READY (1506) +#define CMDQ_ERR_NULL_TASK (1507) +#define CMDQ_ERR_SECURITY_INVALID_SOP (1508) +#define CMDQ_ERR_SECURITY_INVALID_SEC_PORT_FALG (1511) + +enum cmdq_iwc_addr_metadata_type { + CMDQ_IWC_H_2_PA = 0, /* sec handle to sec PA */ + CMDQ_IWC_H_2_MVA = 1, /* sec handle to sec MVA */ + CMDQ_IWC_NMVA_2_MVA = 2, /* map normal MVA to secure world */ + CMDQ_IWC_PH_2_MVA = 3, /* protected handle to sec MVA */ +}; + +enum cmdq_sec_engine_enum { + /* MDP */ + CMDQ_SEC_MDP_RDMA0 = 0, + CMDQ_SEC_MDP_RDMA1 = 1, + CMDQ_SEC_MDP_WDMA = 2, + CMDQ_SEC_MDP_RDMA2 = 3, + CMDQ_SEC_MDP_RDMA3 = 4, + CMDQ_SEC_MDP_WROT0 = 5, + CMDQ_SEC_MDP_WROT1 = 6, + CMDQ_SEC_MDP_WROT2 = 7, + CMDQ_SEC_MDP_WROT3 = 8, + CMDQ_SEC_MDP_HDR0 = 9, + CMDQ_SEC_MDP_HDR1 = 10, + CMDQ_SEC_MDP_HDR2 = 11, + CMDQ_SEC_MDP_HDR3 = 12, + CMDQ_SEC_MDP_AAL0 = 13, + CMDQ_SEC_MDP_AAL1 = 14, + CMDQ_SEC_MDP_AAL2 = 15, + CMDQ_SEC_MDP_AAL3 = 16, + + /* DISP (VDOSYS0) */ + CMDQ_SEC_DISP_RDMA0 = 17, + CMDQ_SEC_DISP_RDMA1 = 18, + CMDQ_SEC_DISP_WDMA0 = 19, + CMDQ_SEC_DISP_WDMA1 = 20, + CMDQ_SEC_DISP_OVL0 = 21, + CMDQ_SEC_DISP_OVL1 = 22, + CMDQ_SEC_DISP_OVL2 = 23, + CMDQ_SEC_DISP_2L_OVL0 = 24, + CMDQ_SEC_DISP_2L_OVL1 = 25, + CMDQ_SEC_DISP_2L_OVL2 = 26, + + /* DSIP (VDOSYS1) */ + CMDQ_SEC_VDO1_DISP_RDMA_L0 = 27, + CMDQ_SEC_VDO1_DISP_RDMA_L1 = 28, + CMDQ_SEC_VDO1_DISP_RDMA_L2 = 29, + CMDQ_SEC_VDO1_DISP_RDMA_L3 = 30, + + /* VENC */ + CMDQ_SEC_VENC_BSDMA = 31, + CMDQ_SEC_VENC_CUR_LUMA = 32, + CMDQ_SEC_VENC_CUR_CHROMA = 33, + CMDQ_SEC_VENC_REF_LUMA = 34, + CMDQ_SEC_VENC_REF_CHROMA = 35, + CMDQ_SEC_VENC_REC = 36, + CMDQ_SEC_VENC_SUB_R_LUMA = 37, + CMDQ_SEC_VENC_SUB_W_LUMA = 38, + CMDQ_SEC_VENC_SV_COMV = 39, + CMDQ_SEC_VENC_RD_COMV = 40, + CMDQ_SEC_VENC_NBM_RDMA = 41, + CMDQ_SEC_VENC_NBM_WDMA = 42, + CMDQ_SEC_VENC_NBM_RDMA_LITE = 43, + CMDQ_SEC_VENC_NBM_WDMA_LITE = 44, + CMDQ_SEC_VENC_FCS_NBM_RDMA = 45, + CMDQ_SEC_VENC_FCS_NBM_WDMA = 46, + + CMDQ_SEC_MAX_ENG_COUNT /* keep in the end */ +}; + +/* + * IWC message + */ +struct iwcCmdqAddrMetadata_t { + /* + * [IN] index of instruction + * Update its arg_b value to real PA/MVA in secure world + */ + u32 instrIndex; + + /* + * Note: Buffer and offset + * + * ------------- + * | | | + * ------------- + * ^ ^ ^ ^ + * A B C D + * + * A: baseHandle + * B: baseHandle + blockOffset + * C: baseHandle + blockOffset + offset + * A~B or B~D: size + */ + + u32 type; /* [IN] addr handle type */ + u64 baseHandle; /* [IN] secure address handle */ + u32 blockOffset; /* [IN] block offset from handle(PA) to current block(plane) */ + u32 offset; /* [IN]_b, buffser offset to secure handle */ + u32 size; /* [IN] buffer size */ + u32 port; /* [IN] HW port id (i.e. M4U port id)*/ +}; + +struct iwcCmdqDebugConfig_t { + s32 logLevel; + s32 enableProfile; +}; + +struct iwcCmdqSecStatus_t { + u32 step; + s32 status; + u32 args[4]; + u32 sec_inst[CMDQ_SEC_MESSAGE_INST_LEN]; + u32 inst_index; + char dispatch[CMDQ_SEC_DISPATCH_LEN]; +}; + +struct iwcCmdqMetadata_t { + u32 addrListLength; + struct iwcCmdqAddrMetadata_t addrList[CMDQ_IWC_MAX_ADDR_LIST_LENGTH]; + + u64 enginesNeedDAPC; + u64 enginesNeedPortSecurity; +}; + +struct iwcCmdqPathResource_t { + long long shareMemoyPA; /* use long long for 64 bit compatible support */ + u32 size; + bool useNormalIRQ; /* use normal IRQ in SWd */ +}; + +struct iwcCmdqCancelTask_t { + /* [IN] */ + s32 thread; + u32 waitCookie; + + /* [OUT] */ + bool throwAEE; + bool hasReset; + s32 irqStatus; /* global secure IRQ flag */ + s32 irqFlag; /* thread IRQ flag */ + u32 errInstr[2]; /* errInstr[0] = instB, errInstr[1] = instA */ + u32 regValue; + u32 pc; +}; + +struct iwcCmdqMetaBuf { + u64 va; + u64 size; +}; + +/* extension flag for secure driver, must sync with def */ +enum sec_extension_iwc { + IWC_MDP_AAL = 0, + IWC_MDP_TDSHP, +}; + +struct readback_engine { + u32 engine; + u32 start; + u32 count; + u32 param; +}; + +struct iwcCmdqCommand_t { + /* basic execution data */ + u32 thread; + u32 scenario; + u32 priority; + u32 commandSize; + u64 engineFlag; + u32 pVABase[CMDQ_IWC_MAX_CMD_LENGTH]; + + /* exec order data */ + u32 waitCookie; /* [IN] index in thread's task list, it should be (nextCookie - 1) */ + bool resetExecCnt; /* [IN] reset HW thread */ + + /* client info */ + s32 callerPid; + char callerName[CMDQ_IWC_CLIENT_NAME]; + + /* metadata */ + struct iwcCmdqMetadata_t metadata; + + /* client extension bits */ + u64 extension; + u64 readback_pa; + + /* debug */ + u64 hNormalTask; /* handle to reference task in normal world */ + + /* SVP HDR */ + u32 mdp_extension; + struct readback_engine readback_engs[CMDQ_MAX_READBACK_ENG]; + u32 readback_cnt; +}; + +/* + * Linex kernel and mobicore has their own MMU tables, + * the latter's is used to map world shared memory and physical address + * so mobicore dose not understand linux virtual address mapping. + * If we want to transact a large buffer in TCI/DCI, there are 2 method (both need 1 copy): + * 1. use mc_map, to map normal world buffer to WSM, and pass secure_virt_addr in TCI/DCI buffer + * note mc_map implies a memcopy to copy content from normal world to WSM. + * 2. declare a fixed length array in TCI/DCI struct, and its size must be < 1M. + */ +struct iwcCmdqMessage_t { + union { + u32 cmd; /* [IN] command id */ + s32 rsp; /* [OUT] 0 for success, < 0 for error */ + }; + + union { + struct iwcCmdqCommand_t command; + struct iwcCmdqCancelTask_t cancelTask; + struct iwcCmdqPathResource_t pathResource; + }; + + struct iwcCmdqDebugConfig_t debug; + struct iwcCmdqSecStatus_t secStatus; + + u8 cmdq_id; +}; +#endif /* __CMDQ_SEC_IWC_COMMON_H__ */ diff --git a/include/linux/mailbox/mtk-cmdq-sec-mailbox.h b/include/linux/mailbox/mtk-cmdq-sec-mailbox.h new file mode 100644 index 000000000000..17ee0ae646ab --- /dev/null +++ b/include/linux/mailbox/mtk-cmdq-sec-mailbox.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef __MTK_CMDQ_SEC_MAILBOX_H__ +#define __MTK_CMDQ_SEC_MAILBOX_H__ + +#include + +#include +#include +#include +#include + +#define CMDQ_INVALID_THREAD (-1) +#define CMDQ_MAX_TASK_IN_SECURE_THREAD (16) +#define CMDQ_SEC_IRQ_THREAD (15) + +/* This define should sync with cmdq_sec_def.h in secure world */ +#define CMDQ_MIN_SECURE_THREAD_ID (8) +#define CMDQ_MAX_SECURE_THREAD_ID (10) +#define CMDQ_MAX_SECURE_THREAD_COUNT (CMDQ_MAX_SECURE_THREAD_ID - CMDQ_MIN_SECURE_THREAD_ID) + +/* Max value of CMDQ_THR_EXEC_CMD_CNT (value starts from 0) */ +#define CMDQ_MAX_COOKIE_VALUE (0xffff) + +enum cmdq_sec_scenario { + CMDQ_SEC_PRIMARY_DISP = 1, + CMDQ_SEC_SUB_DISP = 4, + CMDQ_SEC_PRIMARY_DISP_DISABLE = 18, + CMDQ_SEC_SUB_DISP_DISABLE = 19, + + CMDQ_MAX_SEC_COUNT /* keep in the end */ +}; + +/* Inter-world communication state */ +enum cmdq_iwc_state_enum { + IWC_INIT, + IWC_CONTEXT_INITED, + IWC_WSM_ALLOCATED, + IWC_SES_OPENED, + IWC_SES_ON_TRANSACTED, + + IWC_STATE_END_OF_ENUM, +}; + +/* + * Address metadata, used to translate secure buffer PA + * related instruction in secure world. + */ +struct cmdq_sec_data { + u32 addrMetadataCount; /* [IN] count of element in addrList */ + u64 addrMetadatas; /* [IN] array of iwcCmdqAddrMetadata_t */ + u32 addrMetadataMaxCount; /* [Reserved] */ + + enum cmdq_sec_scenario scenario; + + u64 enginesNeedDAPC; + u64 enginesNeedPortSecurity; + + /* + * [Reserved] + * This is task index in thread's tasklist for CMDQ driver usage. + * Not for client. -1 means not in tasklist. + */ + s32 waitCookie; + /* [Reserved] reset HW thread in secure world */ + bool resetExecCnt; + + /* [OUT] response */ + s32 response; + struct iwcCmdqSecStatus_t sec_status; +}; + +int cmdq_sec_insert_backup_cookie(struct cmdq_pkt *pkt); +int cmdq_sec_pkt_set_data(struct cmdq_pkt *pkt, const u64 dapc_engine, + const u64 port_sec_engine, const enum cmdq_sec_scenario scenario); +int cmdq_sec_pkt_write(struct cmdq_pkt *pkt, u32 addr, u64 base, + const enum cmdq_iwc_addr_metadata_type type, + const u32 offset, const u32 size, const u32 port); + +#endif /* __MTK_CMDQ_SEC_MAILBOX_H__ */ diff --git a/include/linux/mailbox/mtk-cmdq-sec-tee.h b/include/linux/mailbox/mtk-cmdq-sec-tee.h new file mode 100644 index 000000000000..77090921cdf6 --- /dev/null +++ b/include/linux/mailbox/mtk-cmdq-sec-tee.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 MediaTek Inc. + */ + +#ifndef __MTK_CMDQ_SEC_TEE_H__ +#define __MTK_CMDQ_SEC_TEE_H__ + +#include +#include +#include + +/* context for tee vendor */ +struct cmdq_sec_tee_context { + /* Universally Unique Identifier of secure world */ + u8 uuid[TEE_IOCTL_UUID_LEN]; + struct tee_context *tee_context; /* basic context */ + u32 session; /* session handle */ + struct tee_shm *shared_mem; /* shared memory */ +}; + +void cmdq_sec_setup_tee_context(struct cmdq_sec_tee_context *tee); +int cmdq_sec_init_context(struct cmdq_sec_tee_context *tee); +int cmdq_sec_deinit_context(struct cmdq_sec_tee_context *tee); +int cmdq_sec_allocate_wsm(struct cmdq_sec_tee_context *tee, void **wsm_buffer, u32 size); +int cmdq_sec_free_wsm(struct cmdq_sec_tee_context *tee, void **wsm_buffer); +int cmdq_sec_open_session(struct cmdq_sec_tee_context *tee, void *wsm_buffer); +int cmdq_sec_close_session(struct cmdq_sec_tee_context *tee); +int cmdq_sec_execute_session(struct cmdq_sec_tee_context *tee, u32 cmd, s32 timeout_ms); + +#endif /* __MTK_CMDQ_SEC_TEE_H__ */ From patchwork Mon Oct 23 04:37:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jason-JH.Lin" X-Patchwork-Id: 13432333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2558C25B43 for ; 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Lin" , Singo Chang , Nancy Lin , Shawn Sung Subject: [PATCH v2 9/9] arm64: dts: mediatek: mt8195: Add CMDQ secure driver support for gce0 Date: Mon, 23 Oct 2023 12:37:51 +0800 Message-ID: <20231023043751.17114-10-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231023043751.17114-1-jason-jh.lin@mediatek.com> References: <20231023043751.17114-1-jason-jh.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231022_213805_808527_ED126F7C X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add CMDQ secure driver support for GCE0. CMDQ secure driver will requset a GCE HW thread in GCE0 core to support sending a CMDQ packet through secure mailbox. Then ask GCE HW thread to excute commands in the secure world. Signed-off-by: Jason-JH.Lin --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 54c674c45b49..42f9fdf696fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -911,6 +911,8 @@ interrupts = ; #mbox-cells = <2>; clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + mboxes = <&gce0 15 CMDQ_THR_PRIO_1>; + mediatek,gce-events = ; }; gce1: mailbox@10330000 {