From patchwork Mon Oct 23 14:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FF9BC004C0 for ; Mon, 23 Oct 2023 14:40:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B82F10E1F4; Mon, 23 Oct 2023 14:40:57 +0000 (UTC) Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3A75C10E090 for ; Mon, 23 Oct 2023 14:40:23 +0000 (UTC) Received: by mail-qk1-x72d.google.com with SMTP id af79cd13be357-778af1b5b1eso202292485a.2 for ; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Adaptive Ambient Light for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7fd42c8fdc32..840b48a878ca 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-disp-aal - mediatek,mt8192-disp-aal - mediatek,mt8195-disp-aal + - mediatek,mt8365-disp-aal - const: mediatek,mt8183-disp-aal reg: From patchwork Mon Oct 23 14:40:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1A398C25B41 for ; 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Mon, 23 Oct 2023 07:40:25 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:02 +0200 Subject: [PATCH 02/18] dt-bindings: display: mediatek: ccorr: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-2-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=994; i=amergnat@baylibre.com; h=from:subject:message-id; bh=JeNqW+WVxqqJtX+9p7tMLNbwoCk4n1DQyFj303zeDpE=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXOHe+hbAHJDiOZ+OVrpp+ogl+pb7Lr4y+qX804 OlABC7GJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzgAKCRArRkmdfjHURc2gEA DFJ7bqOoha+846mBbXiyiSz8SjEv8vWq1uEyYeVmfWi3sxNfPvY88KKVK7KzsjG1iTOx2+0Kxn7leo DOIAZgnV2ZNoPSq6euB3iS86wajZsW+Vqe7IUem0PaHmzDl5JptkYOnFzuuIS0ABQ/ngG0ps1lkYtS Ku0Coa2KbBAmY6K2/XZ1O6P2AT3AqD5te9dsIbX1F0UJButVt/QxtIy4Iu8OelRfrJJbJUJkt6CJPB Xw0YSXE3JTv0zxGTiV+7gKGRSXBmCst2FmRFQnxUanUhBfB0ouROeDsJ+FAOENbfhfiRVn7Xfbfkc4 HtR/EOX7cSm75MblTuT956tp2Kc6ikETj7dUmuQXOGCrg4NDtSMJZCTvZ29mCRjbtoZAZ4Te9H2m0t y7inJcqCfOcr2TO4IFx6TaEF/Ut5PZkYBuVspi005Cf8RyWovpNcA2LwTViTn14qQ09Z9X6MaRqbDc 7MU5GLr/L+fTsk6gNYWEp027LKetYZpar7qX4imTJJD8a3DDGtW/5DMJN3W1DxzhBAOP/Yzi+kuv0P xd2f31lSLvE5rKq4BcX//75+rMyXe1AOrB1iA0StQrLWHNcao0QUVTtFeVzHAPUGBAMOrj/4bfaBCJ SPVxVC9f9mMG4h9P0XbJD5KniE3CaSL9W8jimZ23Xjz5kgf1ynbthPIpuZ+g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Color Correction for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml index 8c2a737237f2..9f8366763831 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -24,6 +24,9 @@ properties: - enum: - mediatek,mt8183-disp-ccorr - mediatek,mt8192-disp-ccorr + - items: + - const: mediatek,mt8365-disp-ccorr + - const: mediatek,mt8183-disp-ccorr - items: - enum: - mediatek,mt8186-disp-ccorr From patchwork Mon Oct 23 14:40:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 476B9C00A8F for ; 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Mon, 23 Oct 2023 07:40:28 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:03 +0200 Subject: [PATCH 03/18] dt-bindings: display: mediatek: color: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-3-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=942; i=amergnat@baylibre.com; h=from:subject:message-id; bh=YU1e5sIok1+NbWY+6HobM33V2no6aYQT7i5d9DqejUU=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXOX/azDl+ertxlsp4unLNJxzKKT9zEjAR6PtwW hAs1qQmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzgAKCRArRkmdfjHURRc1EA CyDaIaIfkyDDyAVVQwiAwHwJfYWVP8v6IFzEHshzqijzeYNEzhU5kywjLlaKyoNWzwS5QwYGw4ydP0 rGGtLrS0sTHSrcZk5hPSOItdc3deukZxSxsBNw2L6QidCWnsCRMwK3R6wWpajt2AKap0WgUZXz8H2V XQ7YFHDkgZAEbK/ydrb0ywq4K/agzoHG190lbBvBUm4LHMTLWbA3zf0lermqAUExlOrVuT4c7k1ive SuJelX66K7WkPjqZj/WsxOUSrxhid8P6q2DoHoZC9cU4oaN8JqwnZzUtI0kVhggWylulFlyCiIyQ4S Uq13CkltChuXB7zrdWTYNZ3oKXWfUtf09TYzn+aD4KEszGS4CCBkx/Kx1PEurAZEWDOcECD8+ru40w rQG+Vh1XazpuQ/v4ItapdZssXcsXx9gGuFfps/Ag8tZhLHBtlKQS2YkmckrhVefSbXhkRwgbvMAJS1 6DNHYYjAKvEqeTTsV3ECPQCeYrO6w2b8WxCc3gVkkLNdavoY+d3Fq90pgpV+XxIyul6+1/aNJDhn9o nEpRrs9plK+W/0nyUwkrWlbVBppj2gon9XQm+rRZ9iiz47Srd4Io3ZVSnBOh1ebM3iqcBG8Xd+Lb3z GCialIyQYoWGFpw0U96qCACTy26PC2yItVewLkUg/dDXskEGrmlymiViqVng== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Color for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index f21e44092043..fbf15242af52 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt8188-disp-color - mediatek,mt8192-disp-color - mediatek,mt8195-disp-color + - mediatek,mt8365-disp-color - const: mediatek,mt8173-disp-color reg: maxItems: 1 From patchwork Mon Oct 23 14:40:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 232A2C004C0 for ; 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Mon, 23 Oct 2023 07:40:32 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:04 +0200 Subject: [PATCH 04/18] dt-bindings: display: mediatek: dither: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-4-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=938; i=amergnat@baylibre.com; h=from:subject:message-id; bh=tYxquOkpHCbnFi05aHcxCGsRKb8h7qDvHcF/fXuV370=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXOkwi2U4WCrequXuzYCvok2QkmF3+0zqAfxGGm J896eL6JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzgAKCRArRkmdfjHURViaD/ oCnO3B16x6z8742sQoq3Qz35HJC9XGKiHeYoOY2xIdc2g7wjcBOLaA02OVr7AbLQPFMJ4zskMA4uaz IjSpJd6ha3Gdh4fql86jC1THgW8paGXUOfdna0fEdRXWf/TpfPschReTyn1q6a1YHdByWrYAXbyhkV JOOZp7q5szn7Cr+4KUdiAUsdynt83BQMUiWxOf0fwa4+vO/EVy9Ufs9m6xtufJJFGgoEH+UjxHzyrf 58I40s5RZyWwQo7GAu3VWsqrcMUF/txYb5il27M5gdXSfPH6HbTubmMMBNXMAhm4i9TC172GOCUsXX XqCMkDF9xwCbjqPQJgdRR+4Ld+2PpWrTjNEEhf3YGGMV1i2kVJWY4Rk4j5EaNJ3nZvhFng8fnpzwZh YcU9lkXwpHD3nfO/9Ll7J7tvDexb3pD5v+M3EsS4ViFAmKogqOXS5Ev99oBj6D5lbzcgB/wryuRK6q XGoVJ75TlSy6Yg3XFIMggMWra+1FonABuOdIZx1Zm89vE5/w/MIJ3h4pYuQUSJ6KXdTc7V+nCgGo6N BSGnJVYub2dD0vJxKOSqnG2fESwz2kTkO9lcuCYpmW3LkfpxIdfwU0TxKYAmRtGuwsJ6deFOp0NsCM SujXn5rcipp1UgI6zjCqhbxOV3FyFENNZ6M3tN9RKHtk0ZN9xiIRoicfSzOA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Dither for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml index 1588b3f7cec7..6fceb1f95d2a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt8188-disp-dither - mediatek,mt8192-disp-dither - mediatek,mt8195-disp-dither + - mediatek,mt8365-disp-dither - const: mediatek,mt8183-disp-dither reg: From patchwork Mon Oct 23 14:40:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 205D2C25B41 for ; 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Mon, 23 Oct 2023 07:40:35 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:05 +0200 Subject: [PATCH 05/18] dt-bindings: display: mediatek: dsi: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-5-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=898; i=amergnat@baylibre.com; h=from:subject:message-id; bh=+OlEWEvMUxFbKjJVjIiLf0e0kaqCLKK8Af5H5ievjhM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPZJ/cY4ERZiiSBfVRRGRyTqsN8HRcTtNer+op /GLORxmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURV0oD/ 0VXz2ryPfkA3GQgZfBGaQjZnLlqT71UDJqxrP4rzcrY58feUXLCqvam9ncDhmdgUSBM+aphUEBydzM WJH8b2LKpzmJaj5S8Wqz5jyP/D0snP4yShSpzIKA0W84vr969DljY9A0mz82JprPusmwLUWBpr873x iUD+sj9hNpR9mIu1BN+rAFj3se1zGrhWPAk+djg4GQC9Tlg3UAUwS87Qk3jA2xTlaeCRgv18Jngq0S ar9r0GTuD5IwHO4szV96F6eF77D6EWrNEcTHm6jbcdSEfQP2ecIjNOuTt85fAwTjhXqzXIby6ng1U1 wdeBarMnV+qZIaOTiwl/3E3/+LnkQ2zZR1t1mJ6EyaQtWiyETT5bkYubyh5XsUAO1069iV+6uA3M8q ucsPRUSAqTSZ2fKX0yK/gwnSj432MKNFNMBnL4hPOGQcznyrlQpqZadpPUqvk6pCpGNDcvILphvWQ0 AKifv6jwJLQfWb3FTbAtPoa9uRffmwzNlaub6T8EwrebyoGUFyIj4769lqi4XlYSHr2rk9hYlyQBYo vAxhRBm3jOkj8U2LWqL3zaFMr+epUIWc5htDqbxnXwi3apKidDY68sPFZ98mk5xBmITeY+ueR/Rry5 n4zO4J4zgWT5Ss7YzL7jjwLr3MVXV8PDgniVA2BSyJ9UDXJM/TiRtPE3v0DQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Serial Interface for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml index 12441b937684..2479b9e4abd2 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -34,6 +34,8 @@ properties: - enum: - mediatek,mt6795-dsi - const: mediatek,mt8173-dsi + - mediatek,mt8365-dsi + - const: mediatek,mt8183-dsi reg: maxItems: 1 From patchwork Mon Oct 23 14:40:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 411E7C001E0 for ; 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Mon, 23 Oct 2023 07:40:39 -0700 (PDT) From: amergnat@baylibre.com Date: Mon, 23 Oct 2023 16:40:06 +0200 Subject: [PATCH 06/18] dt-bindings: display: mediatek: dpi: add power-domains property MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-6-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1609; i=amergnat@baylibre.com; h=from:subject:message-id; bh=P6NTpV6Hcl2nq4Xnripe5Czc4f+S/tebkAJSAKKZfY8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPLAFxugtO1wZ1wc6FF7eR6Teq9Ksq5ScGKNOo wQqT5GaJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURU8PD/ 9nARfanwZ43dC7K38128J+6s4DtRyTG8Hj37dZv3E61VaZVngol48cTkmXw090pPu59i5eED3Je7Zj j23oVIMjIX68q/zeBxDw4f2iBdqzrQpcfbYsEJM/wyt9jzk9K0d41kVLw2EOuf/8CcnISQFn9v0vr4 Ba3mxWWRTn3rke0AR8IAfs/3OVQrzxbT1/9ZYihMIic0eoBoE0rHOxX1qgAux2bzUPRkTjecZF1NZE 1t8Y+rNbCXFXtynEILOxuQeYMSudfUWkLJ3DmObNMbbcMvXdcBKq9TWTRn3nu26GnrnyKMyc8lt32s +eybrWvI8JX0OlCT3qtGZKq6DjCs/2YiegaxQnAWVQqwQlmbvSy7i182JHCPHmsdYy48fpz5pyAfQN tX5f2ghH3h90rmfwd80LH3T5u69lBpIUgNl3xs56SqCZcESvviuxGUEdKZRcWKHHAQlLr1Qx58vfnY 4swHECrNRS8mQvQk00mISHgkWFE+FGp21hFuG126GPOpCSQetVNlq9Y+vLWL3hTuYAJTtcsOPFdm2I pfljEC21uDHrwGEdXicc8Nsm6w40nIkw6t71siqyx0vgQ8PchwCecgKZWz/2yuqO2XlOaICRDtbhU4 4Cn75XRdTzR6Ax/7Q/RCVx15kQa1IubAdplkKWdvRb+g07dHmShLPZJgHFTA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent DPI is part of the display / multimedia block in MediaTek SoCs, and always have a power-domain (at least in the upstream device-trees). Add the power-domains property to the binding documentation. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 803c00f26206..e126486e8eac 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -64,6 +64,9 @@ properties: Output port node. This port should be connected to the input port of an attached HDMI, LVDS or DisplayPort encoder chip. + power-domains: + maxItems: 1 + required: - compatible - reg @@ -78,11 +81,13 @@ examples: - | #include #include + #include dpi0: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; From patchwork Mon Oct 23 14:40:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432938 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50BD3C00A8F for ; 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Mon, 23 Oct 2023 07:40:42 -0700 (PDT) From: amergnat@baylibre.com Date: Mon, 23 Oct 2023 16:40:07 +0200 Subject: [PATCH 07/18] dt-bindings: display: mediatek: dpi: add binding for MT8365 MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-7-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1806; i=amergnat@baylibre.com; h=from:subject:message-id; bh=jKTgLJ7tZRm38ANNnWtNI/u763F2Jj1UVc7V+THD25Q=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPxIX1QNuRobZW6u5aV9tmmhhr5yqPuC817lI4 62W3Xv6JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURQE3D/ 9gh0ybUwT+mSx5ZgcOKs8AfJtTZow7les4rs5WdR/ORkQzY6kXCEPQHJGwSm0pR6fHVeLntm2PWxpi 78A3aSvnwtOhVtVJoriEEqc3VPTXLDGdncGNzxQgHjIaJf/qf0g3vXhMbQvnMcTGQKq0P7ofP70yRS yp3iq2ADrr+onPPVI9x5OqNqqrgou/rGorFRI3j6YUcUVuRk0eTZw2mvQPpRvhPou7cvlatR+mcOQd berg1tg3/mYPJutWXRz5ap4f1oflMYsg3i9spOCvvx7hjuYxBpU1hHWorYsM9gg0IcXml/oWyQKiQM 17TD0yEEYJ/kIkt+1+FITaxqJIiV1yZC2y7/mWDR9lnavla8+8MVs7z/ISJu+CDzxrBIQyiBnSQ9Dd nEexfUsenm4xIu0EvfZMG1E3iAHqfb84Y4Pm8Ot7gLwQ0Ng2dN5kKXmT5Y0RgVOoRgtNmNyJmJiJ0Z SL6XNuTP80brDNxMxods4dmBecGPUVrhSMLc+2jle6uyNYeODCCeLeCW9AqK4oBI+BgchKhuIOoHCl +ER5rAlg0xyfWbsj1xq00CDmneG0+on57XQ++jBfGnGN6Ia/00PiXrCamZVX8HYu5PLJa1oS/DykiZ RsA4SIdFr0mQ+fJ9a1qydzvN8kxnhcf4lPkehbldTFcp7ns0U5UFtjtzHABQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent DPI for MT8365 is compatible with MT8192 but requires an additional clock. Modify the documentation to requires this clock only on MT8365 SoCs. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat --- .../bindings/display/mediatek/mediatek,dpi.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index e126486e8eac..c86527c33acf 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-dp-intf - mediatek,mt8192-dpi - mediatek,mt8195-dp-intf + - mediatek,mt8365-dpi - items: - enum: - mediatek,mt6795-dpi @@ -39,16 +40,20 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: Pixel Clock - description: Engine Clock - description: DPI PLL + - description: DPI Clock clock-names: + minItems: 3 items: - const: pixel - const: engine - const: pll + - const: dpi pinctrl-0: true pinctrl-1: true @@ -77,6 +82,20 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-dpi + + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + examples: - | #include From patchwork Mon Oct 23 14:40:08 2023 Content-Type: text/plain; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display GAMMA for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml index c6641acd75d6..f447f4320e8b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8188-disp-gamma - mediatek,mt8192-disp-gamma - mediatek,mt8195-disp-gamma + - mediatek,mt8365-disp-gamma - const: mediatek,mt8183-disp-gamma reg: From patchwork Mon Oct 23 14:40:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 067FCC004C0 for ; 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Mon, 23 Oct 2023 07:40:50 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id f1-20020a05620a408100b007789a3499casm2725020qko.115.2023.10.23.07.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 07:40:49 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:09 +0200 Subject: [PATCH 09/18] dt-bindings: display: mediatek: ovl: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-9-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Overlay for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8192 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 3e1069b00b56..2873bbdf3979 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -43,6 +43,7 @@ properties: - items: - enum: - mediatek,mt8186-disp-ovl + - mediatek,mt8365-disp-ovl - const: mediatek,mt8192-disp-ovl reg: From patchwork Mon Oct 23 14:40:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A779FC004C0 for ; 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Mon, 23 Oct 2023 07:40:53 -0700 (PDT) Received: from [127.0.1.1] ([93.5.22.158]) by smtp.googlemail.com with ESMTPSA id f1-20020a05620a408100b007789a3499casm2725020qko.115.2023.10.23.07.40.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 07:40:53 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:10 +0200 Subject: [PATCH 10/18] dt-bindings: display: mediatek: rdma: add binding for MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-10-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display Data Path Read DMA for MT8365 is compatible with another SoC. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index 39dbb5c8bcf8..4cadb245d028 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -45,6 +45,7 @@ properties: - enum: - mediatek,mt8186-disp-rdma - mediatek,mt8192-disp-rdma + - mediatek,mt8365-disp-rdma - const: mediatek,mt8183-disp-rdma reg: From patchwork Mon Oct 23 14:40:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C54EC25B47 for ; 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Mon, 23 Oct 2023 07:40:56 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:11 +0200 Subject: [PATCH 11/18] dt-bindings: pwm: add power-domains property MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-11-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1511; i=amergnat@baylibre.com; h=from:subject:message-id; bh=DODtQ3KKkKmSOKStztk0HQRraEPq6Af8qZra+9tlquw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPErWn29tQPCf4oVzASO7FUbuxbsUhXSJzI3GY C7jeCR+JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURXt/D/ 9MzVckTai5VFj0U2crACXdS3d85+cjns4FtKSUJrUj/WjckEkdp0JsdxKC1zFkNjWK0Ihsv/kw4yem CjzBSNb9MoorMzjySnhztrmePXHYs2TD7BKvHL3UzwQizLhHPUeK0tCLvMrfd3C+G3i//d5Im+GJ3v CPe74eH/Rt4ZHcSUt5BrjEeSfrCE+f5ge9YTMoV9VuuimUyfWf7CZnRzZdcDKZC8hkrn+f/17wtBMu R+oWl6HOInmMINApfqjKTEkiC6vMr1qcZPCT2DsKxjDoEFBacV1PVafe71gumjbFeRk215SA/PTx1/ TH/xHn4Jwlrj94CzH1hUxoYbU74wGylMDpyjEAxRGamB/CBJMGOiksErFg4F4qCV58Q6E+DLMgSRM9 qzBPT0RwgvjthxPYqCDZdm0LesHEhqcnu6q5IzWWAVF1x0uTl53lW58W0xjyGDQGfhgB50Q2wBQUAe ZyLLg1qCtnsSijsKnH7tmjpUGHyN3OTeaqztt5HgDvJBGOiuNyuA07yJIOB2gRt23IrtPo+wFZHtEX fLnYrGMi+HR8rtWvuWHDoUEPM3py0EML3ZNo5mOUBu28/m6ThGcgb87IVVXBJsybV0iJcia4VD1/Ox FjnvboSPmCb8+ILzMlww4Ln+u4fDTotP+vaGxPMNz4G5GF3MT+loseO0hexg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" According to the Mediatek datasheet, the display PWM block has a power domain. Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 153e146df7d4..efe0cacf55b7 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -53,6 +53,12 @@ properties: - const: main - const: mm + power-domains: + maxItems: 1 + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + required: - compatible - reg @@ -67,6 +73,7 @@ examples: #include #include #include + #include pwm0: pwm@1401e000 { compatible = "mediatek,mt8173-disp-pwm"; @@ -75,4 +82,5 @@ examples: clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; clock-names = "main", "mm"; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; }; From patchwork Mon Oct 23 14:40:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3F9D1C001E0 for ; Mon, 23 Oct 2023 14:41:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4325F10E205; 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Mon, 23 Oct 2023 07:41:00 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:12 +0200 Subject: [PATCH 12/18] dt-bindings: pwm: add binding for mt8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-12-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=860; i=amergnat@baylibre.com; h=from:subject:message-id; bh=ffAXKXJ9cZhbqlXUqaqX2HWdbChLJu80R5DE84NCORA=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPMQfrIcZqNQJQO0Ys25obPGYM1stc5OlxnvAk nFfDrjyJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURdavD/ 0ZHAZ0Cjk4mWoa9zs6Fp9jRc9KI2yB7gYjoYxe/765Z3sfJIriT6yE7EbmApJeAFwZXuxMtXTxp1ap LVnEtyhFnLZn9KfHA+ALiIERlyx6i1MPCmiGtdhBSH2kgn5rVrELtf/LrFTJ9LUEuy5MMzV6vnxU3R E+uKJAxMTzdrTUBbvpmehqvKKL05WgmgdrInZWPK+kJHrJ1AYdlXFrFnBPb/WOnmIKBe5agU5m46tc fwUSK/zMXFAjySNrRw+spBLwPUIo5T8iCdLo1VnjYRvJtzkMeyc1hzZGTDWkmKoHGmPx3p0Ee5RUFA 7OMDbifvVvc5t1VQ5KlsyuJcr2nNZWaVFtNotj2PjUSFaiqVubPTbRdk3hcZAKtGSnA9reIBsmViaJ z0e9t0zUGEHa6oTIHkBpFQStDh8lgpeoM+tKKh9RL/OtyNDRvIocFqYTOU8/JVcsUSWlJ0xi3w0EDA Uy1/BPSzCu3Xi4oAs2iNbnzwElhIXn7l4/2+s6fXHQL49j8l9+wkpBITfsWZM0++zwWxgIE89bW0q9 kTB2XBw2jQMfD6NtU9QnfS7D4PztrSV36Dqn0v20qW51tyHLvq4sxPAq2b6GBE9LKE8LKQYx77NnT2 3/+4xLlLo34+v7R651isf4We2qMe+NsPxHGpuHQMIF03yxjM02olxLhcaoaQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Display PWM for MT8365 is compatible with MT8183. Then, add MT8365 binding along with MT8183 SoC. Signed-off-by: Alexandre Mergnat Acked-by: Uwe Kleine-König Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index efe0cacf55b7..e4069bcbf8d5 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -32,6 +32,7 @@ properties: - mediatek,mt8188-disp-pwm - mediatek,mt8192-disp-pwm - mediatek,mt8195-disp-pwm + - mediatek,mt8365-disp-pwm - const: mediatek,mt8183-disp-pwm reg: From patchwork Mon Oct 23 14:40:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CF79C004C0 for ; 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Mon, 23 Oct 2023 07:41:03 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:13 +0200 Subject: [PATCH 13/18] drm/mediatek: dsi: Improves the DSI lane setup robustness MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-13-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1234; i=amergnat@baylibre.com; h=from:subject:message-id; bh=M0lgMNEWbaoZ4qkfmFQ2d2c6SqYe0EzRwVFM4lhot+4=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXP9F3RAu1ZKmUXEIyW8a/kP5CK+Jb3tGF7IdoH 1RqcA3mJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURTPOD/ 9t+6pSLsY0qJ4yNYIAy8Yj64n+qV7yRH4vlC9ppkx91ePv2Sf/rsw1+QRG5hlj0j3d5dWf0ZGe/qPt DjapblIQRzzn7BcMUQD/gavAeQ+YuLMd4IOyVk4uXEBjys9STpAuYQuKC03y3NcyjL6JWTj2fmFXTq FSDDYsV/wNBpk5ALR2J7sE92+GGZXhthAmqro6CeVxpKs8z4H+c8lJOUUGaohZDWJkzoPl3QJssrhq XljafCvUMlRJYbGBRWHusF+de6q6F9tY7mJoX2udGUIrH/cZR16ydBWCpSVaFEKmGEioAQXsFQ1JpS 3/FHHTBX2h2nfGJQ2eT5muUbMii7hB7u5QWiVCF3BFBfzU4ketZCF3bj5Dk9xLBskq1ddV951Z1VJq aWbuUgtjoALtwalhNzN12FffvNPsJIBz4z1TjRHf/cK4a6jaXgVBorbrdg3g+HRu0BH+uAGnC6c1j1 BZhh5BAQvMKdxFZnbk/zwmdsmAwXbfIPVcs2R2rk5mriJ4BOy13/lj/L2c/671sxkorHAFPtQUsi9I 4XIePB314S80C1hBbP4Le8sz3x/gPiLeaQOFxu1Y38FmqYPDFc9iZvDBov3qmHwo1awkx6YyeMuOrY kr/y4GCxn8tSG8oU6g3QQsh+p+1wUWzZ6V47BRTgBHkVb5pT5lxJo6zeFjNg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Currently, mtk_dsi_lane_ready (which setup the DSI lane) is triggered before mtk_dsi_poweron. lanes_ready flag toggle to true during mtk_dsi_lane_ready function, and the DSI module is set up during mtk_dsi_poweron. Later, during panel driver init, mtk_dsi_lane_ready is triggered but does nothing because lanes are considered ready. Unfortunately, when the panel driver try to communicate, the DSI returns a timeout. The solution found here is to put lanes_ready flag to false after the DSI module setup into mtk_dsi_poweron to init the DSI lanes after the power / setup of the DSI module. Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index d8bfc2cce54d..81cf0ddcc399 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -668,6 +668,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + dsi->lanes_ready = false; + return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk); From patchwork Mon Oct 23 14:40:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88BEEC25B41 for ; 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Mon, 23 Oct 2023 07:41:07 -0700 (PDT) From: amergnat@baylibre.com Date: Mon, 23 Oct 2023 16:40:14 +0200 Subject: [PATCH 14/18] drm/mediatek: dpi: add support for dpi clock MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-14-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5504; i=amergnat@baylibre.com; h=from:subject:message-id; bh=gNNMmG/tic5FCAz01Mxk94pBODEehb9j1DvbosxWwjM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPtvxxoh6jBrTsWy5g9sqziSKeYRBQSeK2X9qj pLF6+oGJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURTkGD/ 9aHtaIPalJ9hCBJVp5Cm+eMJS63WzvlzUNGpmZTUXItS7gLNhiSr5M9Ygkx2cEbtyjitdJsef3ebnI CbVf/pWb3thpVnIj2emA0T4Ft/AvZDt5A69fkPmF0PrrVI1d7IPf336AX5AIsJKIlB+cchIXGi4oOh VcSTryoyVCGkKCmID4fVfNyVHV1Fxw1dTipJbS12OvX9fwfCclZHjoikr/B8G6xSopAC66omgAJTbD GJ/nV8ATBffGjCldK8zWsdXhnhMdOVG4nJgjN18FH8IgkPRd8e4/U6SX0Qj/NdTphyWitHWxmt8a3J 2LyqB+lcQ49WBFaLOs7qxG1u1ZCZyElHol4PLbjye0nJdWyNlnMW7yTbODQgwaMpJ4s0/SHlV2+c6o 4Z0L64Ie/RWZdHX3gXB2q+MZJKcx7lpbST/D3q4GumpmPewlHH95Z8ewyluHzWINNM4FSfWCszIE/a I9xFyVeZB1Qo1hzvaVrEj+u9Wtko52r9LNrmvJi+Yds9DdVxwMkDwuPGCF3SdSeEv/sHVvPbrGkXTw Ni1R85QW/UwDwmlAqvlu6ntr0MwqOwZ6Qy6BTGrKnXRTfxP9iAlV3E1beT/pOqKF0gY69zplnECvOy j9CUjsKAn7VaC/s6pr6m0Yx1QK6UQhrO3tl4u84dpMgDExKgpTM/DcDiEkCQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent MT8365 requires an additional clock for DPI. Add support for that additional clock. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dpi.c | 50 +++++++++++++++++++++++++++++++++++++- 1 file changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2f931e4e2b60..ddd7c54febe6 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -70,6 +70,7 @@ struct mtk_dpi { struct device *mmsys_dev; struct clk *engine_clk; struct clk *pixel_clk; + struct clk *dpi_clk; struct clk *tvd_clk; int irq; struct drm_display_mode mode; @@ -137,6 +138,7 @@ struct mtk_dpi_yc_limit { * @csc_enable_bit: Enable bit of CSC. * @pixels_per_iter: Quantity of transferred pixels per iteration. * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS. + * @is_dpi_clk_req: Support the additionnal DPI clock. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -156,6 +158,7 @@ struct mtk_dpi_conf { u32 csc_enable_bit; u32 pixels_per_iter; bool edge_cfg_in_mmsys; + bool is_dpi_clk_req; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -472,6 +475,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_clk); } static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -481,10 +485,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0; + ret = clk_prepare_enable(dpi->dpi_clk); + if (ret) { + dev_err(dpi->dev, "failed to enable dpi clock: %d\n", ret); + goto err_refcount; + } + ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; } ret = clk_prepare_enable(dpi->pixel_clk); @@ -497,6 +507,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->dpi_clk); err_refcount: dpi->refcount--; return ret; @@ -902,6 +914,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, .csc_enable_bit = CSC_ENABLE, + .is_dpi_clk_req = false, }; static const struct mtk_dpi_conf mt2701_conf = { @@ -920,6 +933,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, .csc_enable_bit = CSC_ENABLE, + .is_dpi_clk_req = false, }; static const struct mtk_dpi_conf mt8183_conf = { @@ -937,6 +951,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, .csc_enable_bit = CSC_ENABLE, + .is_dpi_clk_req = false, }; static const struct mtk_dpi_conf mt8186_conf = { @@ -969,6 +984,7 @@ static const struct mtk_dpi_conf mt8188_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE, + .is_dpi_clk_req = false, }; static const struct mtk_dpi_conf mt8192_conf = { @@ -986,6 +1002,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, .csc_enable_bit = CSC_ENABLE, + .is_dpi_clk_req = false, }; static const struct mtk_dpi_conf mt8195_dpintf_conf = { @@ -1000,6 +1017,25 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE, + .is_dpi_clk_req = false, +}; + +static const struct mtk_dpi_conf mt8365_conf = { + .cal_factor = mt8183_calculate_factor, + .channel_swap_shift = CH_SWAP, + .csc_enable_bit = CSC_ENABLE, + .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, + .is_ck_de_pol = true, + .is_dpi_clk_req = true, + .max_clock_khz = 150000, + .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .output_fmts = mt8183_output_fmts, + .pixels_per_iter = 1, + .reg_h_fre_con = 0xe0, + .support_direct_pin = true, + .swap_input_support = true, + .yuv422_en_bit = YUV422_EN, }; static int mtk_dpi_probe(struct platform_device *pdev) @@ -1056,6 +1092,17 @@ static int mtk_dpi_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk), "Failed to get tvdpll clock\n"); + if (dpi->conf->is_dpi_clk_req) { + dpi->dpi_clk = devm_clk_get(dev, "dpi"); + if (IS_ERR(dpi->dpi_clk)) { + ret = PTR_ERR(dpi->dpi_clk); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi clock: %d\n", ret); + + return ret; + } + } + dpi->irq = platform_get_irq(pdev, 0); if (dpi->irq < 0) return dpi->irq; @@ -1097,6 +1144,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8188_dpintf_conf }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf }, { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf }, + { .compatible = "mediatek,mt8365-dpi", .data = &mt8365_conf }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); From patchwork Mon Oct 23 14:40:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AEC08C25B41 for ; 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Mon, 23 Oct 2023 07:41:10 -0700 (PDT) From: amergnat@baylibre.com Date: Mon, 23 Oct 2023 16:40:15 +0200 Subject: [PATCH 15/18] drm/mediatek: add MT8365 SoC support MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-15-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2718; i=amergnat@baylibre.com; h=from:subject:message-id; bh=ZnkaVO4f0o9RizPBgJV2PC+/Ox7JmjKaiFkOq/2YPew=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPvl7J+ly89uTeJkwL0erLnyNQp9pX/flwDfIL raGDyHeJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURRWTEA Cm6umD5gVmCR7xOl83GRyS+2etvws/qE9QDQtrdSXVazCbRh5I4OqeGTz5Wc/fqy9CeQ5923/lkKam Xw/JEizkC4ZVPJZOAe+6s82urCvz70SxQBFupbIl4RPXYIrx49T8ElS6+rr1pHMHn94YucqXY+a32f GMDycbKDPS3BcT1to+1F3fia0IpdzlYAS0QTnhxESja3h7ZPuMhNLE0pf8F+IZwrGeLCGifEroUqHE yz2eBBwDEsuhpRhwtrfZQONp//kfSqOG+SxxegQMja67q6Af6r+wCgaWtGXF8DD3rXfjHy310goD/Q 3kjqLOk2eDKyCdTJLwq9ha1vr2raaT+Saj6ji5h36b7pQyKGusNTU3U4K/m2ICV0PMqY4bz1vTAvtn BraK0gFCfeYHz1JplSTOiKjJJOybGT6rhaTHEorLi8lFFtxqntfVvvFHap2mbH5OqE1etzR/51+opn mbUeGPQ/WKlStmhdMfmW3BHGD4aHc25cz8gis2NPw/Gri3XVURa3m0PKzoxy5sG+uFs8QTEuyk3+5P 4lQvoNrLw/og2NCO2k5EZbGj4BL0KSNV3be5TNYyB+1MY1EwBtmRnqPFAZcy9tMJIyGnueWGJzR1bx /8uq/HHOr9EgLyx4kqNAfpC4e+UIsbhOPJiI/k8F23WM3cftiBOKY3nOBjcw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Fabien Parent , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Fabien Parent Add DRM support for MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 93552d76b6e7..682ab464186f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -227,6 +227,22 @@ static const unsigned int mt8195_mtk_ddp_ext[] = { DDP_COMPONENT_DP_INTF1, }; +static const unsigned int mt8365_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_DITHER0, + DDP_COMPONENT_DSI0, +}; + +static const unsigned int mt8365_mtk_ddp_ext[] = { + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -311,6 +327,14 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .mmsys_dev_num = 2, }; +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { + .main_path = mt8365_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8365_mtk_ddp_main), + .ext_path = mt8365_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8365_mtk_ddp_ext), + .mmsys_dev_num = 1, +}; + static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, @@ -336,6 +360,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8195_vdosys0_driver_data}, { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data}, + { .compatible = "mediatek,mt8365-mmsys", + .data = &mt8365_mmsys_driver_data}, { } }; MODULE_DEVICE_TABLE(of, mtk_drm_of_ids); @@ -703,6 +729,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8195-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8365-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, { .compatible = "mediatek,mt2701-disp-ovl", @@ -765,6 +793,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8186-dsi", .data = (void *)MTK_DSI }, + { .compatible = "mediatek,mt8365-dpi", + .data = (void *)MTK_DPI }, { } }; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Enable this feature for the i350-evk HDMI connector support. Signed-off-by: Alexandre Mergnat --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5315789f4868..0a60e7616abe 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -839,6 +839,7 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_LONTIUM_LT8912B=m CONFIG_DRM_LONTIUM_LT9611=m CONFIG_DRM_LONTIUM_LT9611UXC=m From patchwork Mon Oct 23 14:40:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B95ACC00A8F for ; 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Mon, 23 Oct 2023 07:41:17 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:17 +0200 Subject: [PATCH 17/18] arm64: dts: mediatek: add display blocks support for the MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-17-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7082; i=amergnat@baylibre.com; h=from:subject:message-id; bh=GrqIHwd0l9+44q9ggVwPid+Zd2sZPQpFOwpuTf1SwWY=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPPcsd/oUE0a9NY68W+0Ky2eNYAfmRaFOVUlwY Fr2tBLWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURVuAD/ 9o/qWcsErVbAO5/ec3rAt7R2x0P+I5D9RaBuukKd7b5m0IE8U2CBqbNivJTaA/t1LbRzwHzC/ah3SS qcyz6vE38fXyjCrpFRt42IuTSxMk4lIIuK4BsyGjPznAyL/HH+70O88uzw4B83x9VvvjFAVjB5YVMt SAwZL+wQ0bI0FnauDW3PCkEqasdIzWz3BRGIolJ7iKRM7iZwkqPdgE9FHCNYIyQvdn+fnFG6ZEDHUA fyJs0SK2JzrQugPsFxjQsQawuQRMPm+/WME13iCojHuImZbJCQIeLyhem98xq7c0ludW+1oMLfifTK y5h+azpqOFnG4PAV2bZN2ECUI/tRB4BQxsCIk3gPprDxOFnDGe7A1F9ubDPtJJijvDMF1P+kiLHFEU RMPk8O/Y3/c2bV7RzKBjy00byPbBTAuXzn1AQZBEf5OtXaRs7wBoe/RzeUUAU2zOzy3wimMs60FYmy DKhDKnjDBkS9199Ia+X3b4UeW1l6EhCWGSmovYgyBiR6sG3/H6l5TK93YAKRw0SQH9gsdZHHwJ9iE2 Dwza+H2EfJkCqNLCWo4QEyZ3kq9oK0VipWezsJM97k7wcb4wwC9QyPoN5P0uQdPvIJoaNvdibfJTjC CtBA02Hj+qRBmGlS6x6KvQfcGrgNZn3l/9H00K1MIdGTlw1bgYX4tfEJKang== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..6096358f7d07 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -607,6 +621,17 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", + "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -703,6 +728,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +766,13 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8365-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -755,6 +796,111 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = ; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi"; + reg = <0 0x14018000 0 0x1000>; + assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>; + assigned-clocks = <&topckgen CLK_TOP_DPI0_SEL>; + clock-names = "pixel", "engine", "pll", "dpi"; + clocks = <&topckgen CLK_TOP_DPI0_SEL>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>, + <&mmsys CLK_MM_DPI0_DPI0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; From patchwork Mon Oct 23 14:40:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 13432952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 647CFC004C0 for ; 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Mon, 23 Oct 2023 07:41:21 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:18 +0200 Subject: [PATCH 18/18] arm64: dts: mediatek: add display support for mt8365-evk MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-18-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6023; i=amergnat@baylibre.com; h=from:subject:message-id; bh=pcJBtWjpwilqxNWOakxNZQwRB91WeJf0Sg90BfqV228=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPkea0Zqy/PQcdnRsfgCu3AEXfk7wmG8tbv9W6 6/bMYLmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURSDAEA CQA7Cf4KSXMTBTFLJLDn3nVGt/R5YFfqc4INXDjm6cldZkidaTUTKIifrfDCxHp1r0Ja/JaBxMYzh0 pHhJvAuYtIecogTkNQHbTaEPok1TVVQBfaC39ZpgywxOcQ5R4V5wmk3JZo7ZSibtsAgR+NsmIDQXD1 gMcHUflijw+a1lUpZ3wIGoCtZbrP/M+Gas8r4P6vb7YOIEP4kFZinEF+hPfGadJ7SAzsKKeOS2Am2q tiiB2z92LubE4muqkhtO4YRYBrSLpNkF52xFJfMkp8uweHjtZr8PCrr8AsRMr3ktLamN03DP1LKDDj 2FzODsOY5xZ9SxTdcO5ktlVOW9oyereFUcwssEjDOSm3KneJeNTPngCGOdk+cxVYvKD05XG7WmxJLx Uk6KmO2qNJkS3JSRK6PRltlbvAk3zvHerOVqe1ytnDco6jzVC8hdmhQkOKGLl9l7wUGt93yBAFYYBA 3UUUwXMvgprT3kjgAmhG1P0utomkLEv00dx3r7MhZEFIkKAo++sOZspVHKQNkmAe6HtWJ7Qe24ZjPg lqqmS2yVrDfBExc1i7WvB4nAC0RpGxnkLTV4AjGMsXk0sTh76HJXEAGlACHyNPpd5V+zTZ6z6cXVdq MPQDooC/3O8BIsyi+aQiGQNxmm8cZQnAU/HDVEjWBR0A6OWhBeZxaSBmuYrQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, Alexandre Mergnat , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" MIPI DSI: - Add "vsys_lcm_reg" regulator support and setup the "mt6357_vsim1_reg", to power the pannel plugged to the DSI connector. - Setup the Display Parallel Interface. - Add the startek kd070fhfid015 pannel support. HDMI: - Add HDMI connector support. - Add the "ite,it66121" HDMI bridge support, driven by I2C1. - Setup the Display Parallel Interface. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 183 ++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 50cbaefa1a99..823d7623b8b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -26,6 +26,18 @@ chosen { stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -86,6 +98,57 @@ optee_reserved: optee@43200000 { reg = <0 0x43200000 0 0x00c00000>; }; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vsys_lcm"; + }; +}; + +&dpi0 { + pinctrl-0 = <&dpi_default_pins>; + pinctrl-1 = <&dpi_idle_pins>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&it66121_in>; + }; + }; +}; + + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid015"; + status = "okay"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + + port { + dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &cpu0 { @@ -138,6 +201,50 @@ &i2c0 { status = "okay"; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-div = <2>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + it66121hdmitx: it66121hdmitx@4c { + #sound-dai-cells = <0>; + compatible = "ite,it66121"; + interrupt-parent = <&pio>; + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&ite_pins>; + pinctrl-names = "default"; + reg = <0x4c>; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply = <&mt6357_vsim2_reg>; + vcn33-supply = <&mt6357_vibr_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + it66121_in: endpoint { + bus-width = <12>; + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi_connector_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -180,7 +287,55 @@ &mt6357_pmic { #interrupt-cells = <2>; }; +&mt6357_vsim1_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &pio { + dpi_default_pins: dpi-default-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = ; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux = ; @@ -222,6 +377,34 @@ pins { }; }; + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + + irq_ite_pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux = , + ; + output-high; + }; + + rst_ite_pins { + pinmux = ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux = ;