From patchwork Mon Oct 23 19:13:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13433421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C8CFC25B46 for ; Mon, 23 Oct 2023 19:14:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230432AbjJWTOK (ORCPT ); Mon, 23 Oct 2023 15:14:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229532AbjJWTOJ (ORCPT ); Mon, 23 Oct 2023 15:14:09 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB1D3101; Mon, 23 Oct 2023 12:14:07 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 31DA45C0003; Mon, 23 Oct 2023 15:14:07 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute1.internal (MEProxy); Mon, 23 Oct 2023 15:14:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698088447; x= 1698174847; bh=QkagzItTcmygJhd+IgCnn6qdrUYk56vVzdHfbFmNb0k=; b=T /E/5+zQuNigcfKSF7CMZ0lO9sjt4sK4g600xMPKbt2UIj9cqjGjyKzAvWavJszQ4 cNlF4IOTus0xeZg38meeoj4lN9GH9tsGQ02xwDO+kYXN8R8aFZugbL3iZz31ybDD CLrvfKOKTdcfE5wUgcVyoaQArKmzWAw7xylbskL5pyDMfkdX7hkOrF8CP/lwHOM4 yIBeFFb40qHnaqXXN89QiewLVq+ViQ/0N+6W2HKLWxmL20mWChVY2qtpNFox5pLc i4QwvaWiu1WanHvFVjA8c3I0v1k6CDGLIASuzq0KjJ0+Z9Z8kB49mujAvjwRR4Rl PZeLcixMv78DlUnS5W1Fw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698088447; x= 1698174847; bh=QkagzItTcmygJhd+IgCnn6qdrUYk56vVzdHfbFmNb0k=; b=a 3K19ixhUgYwupkRenvXWOt4P0RKvWT97F34PLsdEaXmBCrJmUsC1cbjF1YaDBjQb STsQMZLCKhwx4dhIJDy4vHCzKcrUl7WlrkVW/7mruUMj6IIm14Byw5hxH+Ni/Rjq SFZ3e+gWUVLlPxuEKNgKrZE4cbf/ZHuU3Ad1xDzjeyBAm33wTMPC1KpLSyVEqvcS Yp4oR/Orq+zKnTPwoA6nzmN9jj8Wbx2iM5PWLiULuIOGnrGs22Cq4kKJYs+XG2T2 luvvFIEh06VDLIo+H5gHKeckPSWIUkPwE/uhgZlNnP0qH12kINqG6/BvUvWs5/vn s6Fra68jeHfTkW+i196TQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrkeeigddufedvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 23 Oct 2023 15:14:05 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 1/5] MIPS: Export higher/highest relocation functions in uasm Date: Mon, 23 Oct 2023 20:13:56 +0100 Message-Id: <20231023191400.170052-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Export uasm_rel_{higher,highest} functions. Those functions can be helpful in dealing with 64bit immediates. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/uasm.h | 2 ++ arch/mips/mm/uasm.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 296bcf31abb5..12db6d2fca07 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr, #ifdef CONFIG_64BIT int uasm_in_compat_space_p(long addr); #endif +int uasm_rel_highest(long val); +int uasm_rel_higher(long val); int uasm_rel_hi(long val); int uasm_rel_lo(long val); void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62..6846bf2084c5 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr) } UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); -static int uasm_rel_highest(long val) +int uasm_rel_highest(long val) { #ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; @@ -433,8 +433,9 @@ static int uasm_rel_highest(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_highest); -static int uasm_rel_higher(long val) +int uasm_rel_higher(long val) { #ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; @@ -442,6 +443,7 @@ static int uasm_rel_higher(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_higher); int uasm_rel_hi(long val) { From patchwork Mon Oct 23 19:13:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13433422 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28848C25B48 for ; Mon, 23 Oct 2023 19:14:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231270AbjJWTOM (ORCPT ); Mon, 23 Oct 2023 15:14:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229499AbjJWTOL (ORCPT ); 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Mon, 23 Oct 2023 15:14:07 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 2/5] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Date: Mon, 23 Oct 2023 20:13:57 +0100 Message-Id: <20231023191400.170052-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use {highest, higher, hi, lo} immediate loading sequence to load 64 bit jump address for handler when kernel is loaded to XKPHYS. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/genex.S | 19 +++++++++++++++---- arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..fd765ad9ecac 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler -FEXPORT(except_vec_vi_lui) - lui v0, 0 /* Patched */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) +FEXPORT(except_vec_vi_hi) + lui v0, 0 /* Patched */ +#else +FEXPORT(except_vec_vi_highest) + lui v0, 0 /* Patched */ +FEXPORT(except_vec_vi_higher) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +FEXPORT(except_vec_vi_hi) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +#endif jr v1 -FEXPORT(except_vec_vi_ori) - ori v0, 0 /* Patched */ +FEXPORT(except_vec_vi_lo) + PTR_ADDIU v0, 0 /* Patched */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..60c513c51684 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_hi[]; + extern const u8 except_vec_vi_lo[], except_vec_vi_end[]; +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + extern const u8 except_vec_vi_highest[], except_vec_vi_higher[]; +#endif extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) - const int lui_offset = except_vec_vi_lui - vec_start + 2; - const int ori_offset = except_vec_vi_ori - vec_start + 2; + const int imm_offset = 2; #else - const int lui_offset = except_vec_vi_lui - vec_start; - const int ori_offset = except_vec_vi_ori - vec_start; + const int imm_offset = 0; +#endif +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + const int highest_offset = except_vec_vi_highest - vec_start + imm_offset; + const int higher_offset = except_vec_vi_higher - vec_start + imm_offset; #endif + const int hi_offset = except_vec_vi_hi - vec_start + imm_offset; + const int lo_offset = except_vec_vi_lo - vec_start + imm_offset; + const int handler_len = except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { @@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif - h = (u16 *)(b + lui_offset); - *h = (handler >> 16) & 0xffff; - h = (u16 *)(b + ori_offset); - *h = (handler & 0xffff); +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + h = (u16 *)(b + highest_offset); + *h = uasm_rel_highest(handler); + h = (u16 *)(b + higher_offset); + *h = uasm_rel_higher(handler); +#endif + h = (u16 *)(b + hi_offset); + *h = uasm_rel_hi(handler); + h = (u16 *)(b + lo_offset); + *h = uasm_rel_lo(handler); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } From patchwork Mon Oct 23 19:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13433423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E25D8C25B45 for ; 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Mon, 23 Oct 2023 15:14:08 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 3/5] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Mon, 23 Oct 2023 20:13:58 +0100 Message-Id: <20231023191400.170052-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org ebase may be in XKPHYS if memblock unable to allocate memory within KSEG0 physical range. To map ebase into uncached space we just convert it back to physical address and then use platform's TO_UNCAC helper to create mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 60c513c51684..230728d76d11 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = TO_UNCAC(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Mon Oct 23 19:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13433424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22658C25B46 for ; Mon, 23 Oct 2023 19:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbjJWTOT (ORCPT ); Mon, 23 Oct 2023 15:14:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231661AbjJWTOO (ORCPT ); Mon, 23 Oct 2023 15:14:14 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44B81100; Mon, 23 Oct 2023 12:14:12 -0700 (PDT) Received: from compute7.internal (compute7.nyi.internal [10.202.2.48]) by mailout.nyi.internal (Postfix) with ESMTP id 9546D5C0381; Mon, 23 Oct 2023 15:14:11 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute7.internal (MEProxy); Mon, 23 Oct 2023 15:14:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698088451; x= 1698174851; bh=axCOXJ1HMSIUr/oFZjhnVtqXrX+b0q0P4G/a7WUwdbo=; b=v sLaEWs92HWTR+7DJmUj2C5j4L3zPRmjgOhMu51FdXoiwbWRGb/Vr9Yum7Sy9z9Ax QDizshS8CFvxX9KSLEC6K8RgBc5toBasXpaErwFUWlgCxIF2GRJsNi6ONkVJKhYP +1P9b1HCvOtXeP39IFh7gy0gLxI/cOLsC0BUk0HDFr8G+2LaYifAKHeWvUuuvtOq iW+wFNLZTT4y2NOSOIaXS3n4DemEcLhMk557ohgWpofuvKHlS66jjwVGNTahJiuT OIXwVdQi2Qt588OSbXYm0JfkXu9DJEpvqBesAnAkhLqIy2Y1aI9Kks5N4YEeV8mz 9Z6kOFIKmhU77BoEz+jjA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698088451; x= 1698174851; bh=axCOXJ1HMSIUr/oFZjhnVtqXrX+b0q0P4G/a7WUwdbo=; b=H 1HXqrR9VDzPz5pGLgnhATMlkXnkYo86IZ9veC3/fX/6JB5Ld5oW3BBmazE5YeWBD oHTFg16AiKsjH/+voYWMYnv++Ul84E5BOdcG1AOniGBNobX9b3y1i86/Ebd1D+1J 4Z3VUh0hZpvJA7+/YTRHq9eHuqbG5Hbn8jfRupaMLkLHu4KUsgU+0FkJTpgTewta yH/I7lYLaaG/EGw/bcaCU5OG8h5vW7tNsQXkaeb4W4t7HxEdK3Smv0EnRExopxol DfdIe2JKMZTLJ/mo/Bs2wU/ts2Kf412st0cmoXRQRYN10IU5d+zAYProreRpejHy ej0t5GO+Z/Bhgvx/t0jCw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrkeeigddufeefucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 23 Oct 2023 15:14:10 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 4/5] MIPS: Handle mips_cps_core_entry within lower 4G Date: Mon, 23 Oct 2023 20:13:59 +0100 Message-Id: <20231023191400.170052-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Set CM_GCR_Cx_RESET_BASE_MODE and use XKPHYS base address for core_entry for 64bit CM when mips_cps_core_entry is beyond KSEG1. Also disable SMP and warn user if mips_cps_core_entry is unsuitable as reset vector. Signed-off-by: Jiaxun Yang --- Note: IMO it does not solve the problem of MobileEye, which have mips_cps_core_entry beyond lower 4G, it just enables me to test kernel in XKPHYS on boston. --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..15d8d69de455 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db..623dfd05585b 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -26,6 +26,7 @@ #include static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; struct core_boot_config *mips_cps_core_bootcfg; @@ -37,7 +38,6 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +94,20 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + /* + * Set up the core entry address + * If accessible in KSEG1 just use KSEG1 + */ + if (__pa_symbol(mips_cps_core_entry) < SZ_512M) + core_entry_reg = CKSEG1ADDR(__pa_symbol(mips_cps_core_entry)); + + /* If CM is 64bit and with-in low 4G just use XKPHYS */ + if (mips_cm_is64 && __pa_symbol(mips_cps_core_entry) < SZ_4G) + core_entry_reg = __pa_symbol(mips_cps_core_entry) | + CM_GCR_Cx_RESET_BASE_MODE; + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -114,6 +124,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -213,7 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); From patchwork Mon Oct 23 19:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13433425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF57BC25B47 for ; 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Mon, 23 Oct 2023 15:14:11 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 5/5] MIPS: Allow kernel base to be set from Kconfig for all platforms Date: Mon, 23 Oct 2023 20:14:00 +0100 Message-Id: <20231023191400.170052-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There are some platforms in wild that generic loading address won't work with them due to memory layout. Allow PHYSICAL_START to be override from Kconfig, introduce PHYSICAL_START_BOOL symbol as powerpc did. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc8421859006..bfedc8b48a81 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC config ARCH_SUPPORTS_CRASH_DUMP def_bool y +config PHYSICAL_START_BOOL + bool "Set physical address where the kernel is loaded" + default y if CRASH_DUMP + help + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. + + Say N here unless you know what you are doing. + config PHYSICAL_START - hex "Physical address where the kernel is loaded" - default "0xffffffff84000000" - depends on CRASH_DUMP + hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL + default "0xffffffff84000000" if CRASH_DUMP + default "0xffffffff80100000" help - This gives the CKSEG0 or KSEG0 address where the kernel is loaded. + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. If you plan to use kernel for capturing the crash dump change this value to start of the reserved region (the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter