From patchwork Tue Oct 24 10:22:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13434188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD004C07545 for ; Tue, 24 Oct 2023 10:22:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 960DD10E31E; Tue, 24 Oct 2023 10:21:54 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 01B9C10E31C; Tue, 24 Oct 2023 10:21:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698142912; x=1729678912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XPyfBpnhxXPgf0FDxskGfQUAM2UFQpJmgvZkgov5+/Q=; b=ASRcxcy1CqVYJJD/ZhftVvZEhrtF1uC+6bBoMfgD62J4tCe577j4qGnX OB0tB5S6gpY46NYK1S2dkXL4XBvoUsW0JQTKOYMUjgiCJ/UsACshjjAdk 15mb+ILfXJ2gNM31SyJbKle2W9Gtz9LC4NamycbAG2jrHzoh04VpwfaLv VP74nom2pNZ40RnsGlCW1lVsTd5YI1kdacoSYEP7B5qy3Npnwn+bx6qMH oVpI4ew2nueH5s6VT5a3KP6mKBJUQrzKxPzXF0vRCEcO8Yp9Ot3jNC9Gb Y9iSH1ISq5Mv+aH15j/P+PkgDKiDH0qbLCZ8ka+UEZ0z2stEXz2XE755K Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="473251949" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="473251949" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:21:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="902118275" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="902118275" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:19:30 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Oct 2023 13:22:16 +0300 Message-Id: <20231024102219.4035939-1-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024010925.3949910-8-imre.deak@intel.com> References: <20231024010925.3949910-8-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 07/29] drm/dp_mst: Add HBLANK expansion quirk for Synaptics MST hubs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a quirk for Synaptics MST hubs, which require a workaround - at leat on i915 - for some modes, on which the hub applies HBLANK expansion. These modes will only work by enabling DSC decompression for them, a follow-up patch will do this in i915. v2: - Fix the quirk name in its docbook description. Cc: Lyude Paul Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/display/drm_dp_helper.c | 2 ++ include/drm/display/drm_dp_helper.h | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index f3680f4e69708..e5d7970a9ddd0 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2245,6 +2245,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, + /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */ + { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, }; diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 3d74b2cec72fd..da94932f4262b 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -632,6 +632,13 @@ enum drm_dp_quirk { * the DP_MAX_LINK_RATE register reporting a lower max multiplier. */ DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, + /** + * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: + * + * The device applies HBLANK expansion for some modes, but this + * requires enabling DSC. + */ + DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, }; /** From patchwork Tue Oct 24 10:22:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13434189 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6030BC25B47 for ; Tue, 24 Oct 2023 10:22:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7981F10E320; Tue, 24 Oct 2023 10:21:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 67D5310E31C; Tue, 24 Oct 2023 10:21:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698142913; x=1729678913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zMKYhrDM/vW6moOvi9XD9ZbizjNn1UA0fTDC3ROS5MY=; b=MYe82knuzmry6wO65B86dPApeo8exKWwteVH0obz+aAveT6o/e6L1H6T X+b+pgjyeJRiTAWwzLoKCYzxV2EdwrexG8cs40Dv6tCOZQcoa61S3fBgO 4JV9VnkDnd9iFbv51xvrPlZNfZOA7ENMP4n3o29tfGFNbmCBgUKw8/CCK A/5wK6ttKeJJgkAiTuLTvHzZe3JZb3uPEB1FXpvIB/AvQEw+ryRB2Q7H2 qWDU7qu6Q0WpUriwzvoeTqfDhAnd3OXihh0tyJwGcFpH9vinVFeNJj2xC Ct5kZwmFvx89OHwBRB0sU3EZHxwGmTYASFTCkXQUQuaCWmYtIiGCnYOon g==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="473251952" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="473251952" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:21:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="902118299" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="902118299" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:19:31 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Oct 2023 13:22:17 +0300 Message-Id: <20231024102219.4035939-2-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024010925.3949910-9-imre.deak@intel.com> References: <20231024010925.3949910-9-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 08/29] drm/dp: Add helpers to calculate the link BW overhead X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add helpers drivers can use to calculate the BW allocation overhead - due to SSC, FEC, DSC and data alignment on symbol cycles - and the channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On 128b/132b links the FEC overhead is part of the coding efficiency, so not accounted for in the BW allocation overhead. The drivers can use these functions to calculate a ratio, controlling the stream symbol insertion rate of the source device in each SST TU or MST MTP frame. Drivers can calculate this m/n = (pixel_data_rate * drm_dp_bw_overhead()) / (link_data_rate * drm_dp_bw_channel_coding_efficiency()) ratio for a given link and pixel stream and with that the mtp_count = CEIL(64 * m / n) allocated MTPs for the stream in a link frame and pbn = CEIL(64 * dm_mst_get_pbn_divider() * m / n) allocated PBNs for the stream on the MST link path. Take drm_dp_bw_overhead() into use in drm_dp_calc_pbn_mode(), for drivers calculating the PBN value directly. v2: - Add dockbook description to drm_dp_bw_channel_coding_efficiency(). (LKP). - Clarify the way m/n ratio is calculated in the commit log. Cc: Lyude Paul Cc: kernel test robot Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/display/drm_dp_helper.c | 124 ++++++++++++++++++ drivers/gpu/drm/display/drm_dp_mst_topology.c | 23 +++- include/drm/display/drm_dp_helper.h | 11 ++ 3 files changed, 152 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index e5d7970a9ddd0..79629bf7547bf 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -3899,4 +3899,128 @@ int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) } EXPORT_SYMBOL(drm_panel_dp_aux_backlight); +/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */ +static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, + int symbol_size, bool is_mst) +{ + int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); + int align = is_mst ? 4 / lane_count : 1; + + return ALIGN(cycles, align); +} + +static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, + int bpp_x16, int symbol_size, bool is_mst) +{ + int slice_pixels = DIV_ROUND_UP(pixels, slice_count); + int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels, + bpp_x16, symbol_size, is_mst); + int slice_eoc_cycles = is_mst ? 4 / lane_count : 1; + + return slice_count * (slice_data_cycles + slice_eoc_cycles); +} + +/** + * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream + * @lane_count: DP link lane count + * @hactive: pixel count of the active period in one scanline of the stream + * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set + * @bpp_x16: bits per pixel in .4 binary fixed point + * @flags: DRM_DP_OVERHEAD_x flags + * + * Calculate the BW allocation overhead of a DP link stream, depending + * on the link's + * - @lane_count + * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST) + * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR) + * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC) + * - SSC mode (@flags / %DRM_DP_OVERHEAD_SSC) + * as well as the stream's + * - @hactive timing + * - @bpp_x16 color depth + * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC). + * Note that this overhead doesn't account for the 8b/10b, 128b/132b + * channel coding efficiency, for that see + * @drm_dp_link_bw_channel_coding_efficiency(). + * + * Returns the overhead as 100% + overhead% in 1ppm units. + */ +int drm_dp_bw_overhead(int lane_count, int hactive, + int dsc_slice_count, + int bpp_x16, unsigned long flags) +{ + int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8; + bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST; + u32 overhead = 1000000; + int symbol_cycles; + + /* + * DP Standard v2.1 2.6.4.1 + * SSC downspread and ref clock variation margin: + * 5300ppm + 300ppm ~ 0.6% + */ + if (flags & DRM_DP_BW_OVERHEAD_SSC) + overhead += 6000; + + /* + * DP Standard v2.1 2.6.4.1.1: + * FEC symbol insertions for 8b/10b channel coding: + * 2.4% + */ + if (flags & DRM_DP_BW_OVERHEAD_FEC) + overhead += 24000; + + /* + * DP Standard v2.1 2.7.9, 5.9.7 + * The FEC overhead for UHBR is accounted for in its 96.71% channel + * coding efficiency. + */ + WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) && + (flags & DRM_DP_BW_OVERHEAD_FEC)); + + if (flags & DRM_DP_BW_OVERHEAD_DSC) + symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive, + dsc_slice_count, + bpp_x16, symbol_size, + is_mst); + else + symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive, + bpp_x16, symbol_size, + is_mst); + + return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count, + overhead * 16), + hactive * bpp_x16); +} +EXPORT_SYMBOL(drm_dp_bw_overhead); + +/** + * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency + * @is_uhbr: Whether the link has a 128b/132b channel coding + * + * Return the channel coding efficiency of the given DP link type, which is + * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes + * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead + * and for 128b/132b any link or PHY level control symbol insertion overhead + * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the + * corresponding FEC overhead is BW allocation specific, included in the value + * returned by drm_dp_bw_overhead(). + * + * Returns the efficiency in the 100%/coding-overhead% ratio in + * 1ppm units. + */ +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) +{ + if (is_uhbr) + return 967100; + else + /* + * Note that on 8b/10b MST the efficiency is only + * 78.75% due to the 1 out of 64 MTPH packet overhead, + * not accounted for here. + */ + return 800000; +} +EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency); + #endif diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index cc0a8fe84d290..d7383f2fd6cfe 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -4726,17 +4726,28 @@ EXPORT_SYMBOL(drm_dp_check_act_status); int drm_dp_calc_pbn_mode(int clock, int bpp) { /* - * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on * common multiplier to render an integer PBN for all link rate/lane * counts combinations * calculate - * peak_kbps *= (1006/1000) - * peak_kbps *= (64/54) - * peak_kbps *= 8 convert to bytes + * peak_kbps = clock * bpp / 16 + * peak_kbps *= SSC overhead / 1000000 + * peak_kbps /= 8 convert to Kbytes + * peak_kBps *= (64/54) / 1000 convert to PBN */ - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4), - 1000 * 8 * 54 * 1000); + /* + * TODO: Use the actual link and mode parameters to calculate + * the overhead. For now it's assumed that these are + * 4 link lanes, 4096 hactive pixels, which don't add any + * significant data padding overhead and that there is no DSC + * or FEC overhead. + */ + int overhead = drm_dp_bw_overhead(4, 4096, 0, bpp, + DRM_DP_BW_OVERHEAD_MST | + DRM_DP_BW_OVERHEAD_SSC); + + return DIV64_U64_ROUND_UP(mul_u32_u32(clock * bpp, 64 * overhead >> 4), + 1000000ULL * 8 * 54 * 1000); } EXPORT_SYMBOL(drm_dp_calc_pbn_mode); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index da94932f4262b..d0f7406c510a8 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -788,4 +788,15 @@ bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZ const u8 port_cap[4], u8 color_spc); int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); +#define DRM_DP_BW_OVERHEAD_MST BIT(0) +#define DRM_DP_BW_OVERHEAD_UHBR BIT(1) +#define DRM_DP_BW_OVERHEAD_SSC BIT(2) +#define DRM_DP_BW_OVERHEAD_FEC BIT(3) +#define DRM_DP_BW_OVERHEAD_DSC BIT(4) + +int drm_dp_bw_overhead(int lane_count, int hactive, + int dsc_slice_count, + int bpp_x16, unsigned long flags); +int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); + #endif /* _DRM_DP_HELPER_H_ */ From patchwork Tue Oct 24 10:22:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13434190 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70930C07545 for ; Tue, 24 Oct 2023 10:22:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC63510E324; Tue, 24 Oct 2023 10:21:55 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6026110E31D for ; Tue, 24 Oct 2023 10:21:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698142914; x=1729678914; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Gvtq+ZH3dJPgXjm00tLL1GtjA63hzu0xTNHLTDJn+Ug=; b=cCzOkY5+sn47buYPHbddCHswSkh5WuReBH2qn2GkhrRGLwonzsDjCwrd 1DpYqAME7BGkO03xV6O/7MAO4ixrmZXvYrJ3OTKIyYWPZf/v/suAb4QmT 1j3ZPr2W6E8Hc2PaxhU/JrOht9lDQDex3EMafajXQl0AVj2t83QW+Jo0R djjfLqYeXkDoePTED8KBnK+MMB3GIo2kGqJrRTtVFa82FDOW1Y3QnjqP9 JYVij1EdZKH/gRMDYDUnNAtX9W6vVSbV/Qt9YhYocHTK0QS39BCeMQ1ck f+Kfsk+XAgJC3gVztMsc94zFwxICQF27s9TfxXOTlOVKn5ZNlr22kxgIt A==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="473251954" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="473251954" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:21:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="902118301" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="902118301" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:19:33 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Oct 2023 13:22:18 +0300 Message-Id: <20231024102219.4035939-3-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024010925.3949910-23-imre.deak@intel.com> References: <20231024010925.3949910-23-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 22/29] drm/i915/dp: Enable DSC via the connector decompression AUX X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable DSC using the DSC AUX device stored for this purpose in the connector. This prepares for a follow-up patch which toggles DSC for each stream as needed, but for now keeps the current behavior, as DSC is still only enabled for the first MST stream. While at it set/clear only the DP_DECOMPRESSION_EN flag in the DP_DSC_ENABLE DPCD register, preserving the reserved register bits. v2: - Add a helper function setting/clearing the decompression flag, preserving the reserved register bits. Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_ddi.c | 14 ++++--- drivers/gpu/drm/i915/display/intel_dp.c | 46 +++++++++++++++++---- drivers/gpu/drm/i915/display/intel_dp.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +- 4 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index bc438272d6d1a..79e36939d92d1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2539,7 +2539,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_dp_configure_protocol_converter(intel_dp, crtc_state); if (!is_mst) - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector), + crtc_state, true); /* * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit @@ -2692,7 +2693,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_dp_configure_protocol_converter(intel_dp, crtc_state); if (!is_mst) - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true); + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector), + crtc_state, true); /* * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit * in the FEC_CONFIGURATION register to 1 before initiating link @@ -2773,8 +2775,8 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, intel_dp_set_power(intel_dp, DP_SET_POWER_D0); intel_dp_configure_protocol_converter(intel_dp, crtc_state); if (!is_mst) - intel_dp_sink_set_decompression_state(intel_dp, crtc_state, - true); + intel_dp_sink_set_decompression_state(to_intel_connector(conn_state->connector), + crtc_state, true); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); intel_dp_start_link_train(intel_dp, crtc_state); if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && @@ -3354,6 +3356,8 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state, const struct drm_connector_state *old_conn_state) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_connector *connector = + to_intel_connector(old_conn_state->connector); intel_dp->link_trained = false; @@ -3362,7 +3366,7 @@ static void intel_disable_ddi_dp(struct intel_atomic_state *state, intel_psr_disable(intel_dp, old_crtc_state); intel_edp_backlight_off(old_conn_state); /* Disable the decompression in DP Sink */ - intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, + intel_dp_sink_set_decompression_state(connector, old_crtc_state, false); /* Disable Ignore_MSA bit in DP Sink */ intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7d185d6b2fe9d..0101e17515b33 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2937,22 +2937,50 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; } -void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, +static int +write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set) +{ + int err; + u8 val; + + err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val); + if (err < 0) + return err; + + if (set) + val |= flag; + else + val &= ~flag; + + return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val); +} + +static void +intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, + bool enable) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + + if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux, + DP_DECOMPRESSION_EN, enable) < 0) + drm_dbg_kms(&i915->drm, + "Failed to %s sink decompression state\n", + str_enable_disable(enable)); +} + +void intel_dp_sink_set_decompression_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state, bool enable) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int ret; + struct drm_i915_private *i915 = to_i915(connector->base.dev); if (!crtc_state->dsc.compression_enable) return; - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, - enable ? DP_DECOMPRESSION_EN : 0); - if (ret < 0) - drm_dbg_kms(&i915->drm, - "Failed to %s sink decompression state\n", - str_enable_disable(enable)); + if (drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux)) + return; + + intel_dp_sink_set_dsc_decompression(connector, enable); } static void diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 2080575fef69a..a231d234f6e9d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -57,7 +57,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); -void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, +void intel_dp_sink_set_decompression_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state, bool enable); void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b0310f464c1cd..8ef3a2611207c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -735,7 +735,7 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, * TODO: disable decompression for all streams/in any MST ports, not * only in the first downstream branch device. */ - intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, false); + intel_dp_sink_set_decompression_state(connector, old_crtc_state, false); } static void intel_mst_post_disable_dp(struct intel_atomic_state *state, @@ -895,7 +895,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, * TODO: enable decompression for all streams/in any MST ports, not * only in the first downstream branch device. */ - intel_dp_sink_set_decompression_state(intel_dp, pipe_config, true); + intel_dp_sink_set_decompression_state(connector, pipe_config, true); dig_port->base.pre_enable(state, &dig_port->base, pipe_config, NULL); } From patchwork Tue Oct 24 10:22:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 13434191 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 774BAC00A8F for ; Tue, 24 Oct 2023 10:22:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F39110E31F; Tue, 24 Oct 2023 10:21:58 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 78C2E10E31F for ; Tue, 24 Oct 2023 10:21:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698142915; x=1729678915; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=lRd0ye/Wy9LsHis8y4eomIy4JjsRTvvwBclkafTEEm0=; b=Y5cH8aI7OnjAXBtzDlL/CEZYhlqFAYRpoPD9BNHifnAiiZt0h3nAXBzY hS4e44/tV+4NweF9FVYBSpeLEQLJ+mSJsRm+xvw9Ret4gEmutyMCDuFDN +3a4NqbvhlGED7mcHjlhZZr8SUURzK0CtVqdwDxjglM8sQU/aohrvzSZ5 3c7GLLRZzywoU8uqfvdUv7wpRR/UCYrs6M79WhUrNQ8hxSQl0eb96/Ev+ +n2mm/sli1BjUPKT8cpjx12UkYWE0kM98VOJ9Rskp5QnIPBJkMh7IcR12 XzMNUHTNmvRVw4nMh2QNFjYOlSGdvfprCaR/WUzTcGnlC9eyjJyQ3cUgN A==; X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="473251957" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="473251957" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:21:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10872"; a="902118302" X-IronPort-AV: E=Sophos;i="6.03,247,1694761200"; d="scan'208";a="902118302" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2023 03:19:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Oct 2023 13:22:19 +0300 Message-Id: <20231024102219.4035939-4-imre.deak@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231024010925.3949910-24-imre.deak@intel.com> References: <20231024010925.3949910-24-imre.deak@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 23/29] drm/i915/dp_mst: Enable DSC passthrough X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable passing through DSC streams to the sink in last branch devices. v2: - Fix the DPCD register address while setting/clearing the passthrough flag. Signed-off-by: Imre Deak Reviewed-by: Stanislav Lisovskiy --- drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0101e17515b33..51d6ab170a894 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2968,6 +2968,24 @@ intel_dp_sink_set_dsc_decompression(struct intel_connector *connector, str_enable_disable(enable)); } +static void +intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector, + bool enable) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct drm_dp_aux *aux = connector->port ? + connector->port->passthrough_aux : NULL; + + if (!aux) + return; + + if (write_dsc_decompression_flag(aux, + DP_DSC_PASSTHROUGH_EN, enable) < 0) + drm_dbg_kms(&i915->drm, + "Failed to %s sink compression passthrough state\n", + str_enable_disable(enable)); +} + void intel_dp_sink_set_decompression_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state, bool enable) @@ -2980,7 +2998,13 @@ void intel_dp_sink_set_decompression_state(struct intel_connector *connector, if (drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux)) return; - intel_dp_sink_set_dsc_decompression(connector, enable); + if (enable) { + intel_dp_sink_set_dsc_passthrough(connector, true); + intel_dp_sink_set_dsc_decompression(connector, true); + } else { + intel_dp_sink_set_dsc_decompression(connector, false); + intel_dp_sink_set_dsc_passthrough(connector, false); + } } static void