From patchwork Tue Oct 24 15:10:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13434754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45AEEC07545 for ; Tue, 24 Oct 2023 15:12:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dSnelQE+mvW4h7GIt5F+67MZlGt5MHk83AfN2u8Xxi8=; b=DxjrZr1hYct2SH QJPlPzsQxO2DUfNFLDFj+acxUJOI3Va9dRyeFb4hpqfW+yVjbRzbRokrR5xZDpSuYlwbTQNEFkwcZ WrxDjNjZcwOPRSLIatjb0ynfZlXXyULEJVJT14glYJWjTRk2NiyowIcVW55jJ6KOeWEQqoJ0x/xjO 6OpWLFIEm8P0qgHUCPtjySJLhOeOYWZ/rQ6EdVkuqujBE78KWfFf14EVQKbzirY6JwxgDpYFu7pyJ SF9cLViPIMviVpWVaDKRqCkSac6srj+qps3FmG1Pp4qbK7C81mjv03acs/JlgGqAbtG3RV8vUVp4Q aOcrYNExyLxcSWbHgXMA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvJ4E-00ADI4-1b; Tue, 24 Oct 2023 15:11:38 +0000 Received: from mail-lf1-x12b.google.com ([2a00:1450:4864:20::12b]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvJ4B-00ADGB-2b; Tue, 24 Oct 2023 15:11:37 +0000 Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-50802148be9so1825146e87.2; Tue, 24 Oct 2023 08:11:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698160290; x=1698765090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=tjok56bysgEIfmMlNTMUS4bt0vrF/tKjOL5ojA3lAj4=; b=tjbGoMO6v8//AUVT3obCvS4tgKEI/Rlco/OnQntS6MbGh+NhHLQX9XkUImiNIs51ul ooLAuA66QIamM5VO/mXJTSjXK1Z+VrhrVIrd7njiwzRLZXJdiY9k6E25wcjqMv/TbThf 9+6sJm2+u5Soo/C/zdpt47d/KdFTJez5ejZ+iKWTv+/tDAV7edfMBtEg1gFtiiC73gYj /Wk7tcSY2J04/TIthrrEJd4Bd72Vs/hTG3KeBCJxkPK+F27miIRMQxQUSAGNMcpq/mRT 3epELZ0py8zlBMkc9Cuq3Ks+dcUFlOpRpI0hqSli4VjCTfEuYlha5bVeWAcf//nms4D7 1vMw== X-Gm-Message-State: AOJu0YwwDpYOYdW6oCP8v1y4VAF1AWjuC34MvD3MoSFtajv5N5nlihLf dcS2sQe1+bBaJQzWc4WgBdLvi1sAu+/lrg== X-Google-Smtp-Source: AGHT+IGkjHyMvDG6EAQb0xFxTYm/TJqjLv5oKQpSlEQCC5DMQ7GzGPx+GItLE8HrsejZLx1NRhEskA== X-Received: by 2002:a05:6512:48a:b0:507:c872:7f84 with SMTP id v10-20020a056512048a00b00507c8727f84mr8633008lfq.29.1698160289788; Tue, 24 Oct 2023 08:11:29 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id b4-20020ac25e84000000b00507cee141c9sm2180259lfq.32.2023.10.24.08.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:11:29 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 8CFAB1645; Tue, 24 Oct 2023 17:11:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160288; bh=L8JeOW9o9OlpyYp8SHB1xCbEeYmEJRvMKzVVwI04Dng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j1ljPPjtyuxI9/2QJj4h0I/7na6spbL0XYBllWdTXVy1fMqjHsHn7Lll43LTe3a0c CWQ7BL1jl5N9W+OQvpFms0mcUaPKPt+Kfjpz9iBguQScf/efv43NS9rD5k/a149MGH ajERwI6/KmxGMO0bLIp+S2b5SZVgV8pIy0hw4cOU= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 6DD0214DB; Tue, 24 Oct 2023 17:10:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160244; bh=L8JeOW9o9OlpyYp8SHB1xCbEeYmEJRvMKzVVwI04Dng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uPFkoJhQzCTotouNSHQ5d5yXqQtgVNvrxssQNIiRGjZljqNeSck3cOMf+Lqe98O4F DFpvOEt+sQYUASd80WbXc+0bVXhId8ouznlvWlOUafB+CNUKeXDSWddDj12DKJyNXn 4jYl42Aiwaf8K2+7KgAeZClh7mrFfXknuXjdwWro= From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 1/4] dt-bindings: PCI: dwc: rockchip: Add atu property Date: Tue, 24 Oct 2023 17:10:08 +0200 Message-ID: <20231024151014.240695-2-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081135_840843_F2AC77A1 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml using: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# and snps,dw-pcie.yaml does have the atu property defined, in order to be able to use this property, while still making sure 'make CHECK_DTBS=y' pass, we need to add this property to rockchip-dw-pcie.yaml. Signed-off-by: Niklas Cassel --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 1ae8dcfa072c..229f8608c535 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -29,16 +29,20 @@ properties: - const: rockchip,rk3568-pcie reg: + minItems: 3 items: - description: Data Bus Interface (DBI) registers - description: Rockchip designed configuration registers - description: Config registers + - description: iATU registers reg-names: + minItems: 3 items: - const: dbi - const: apb - const: config + - const: atu clocks: minItems: 5 From patchwork Tue Oct 24 15:10:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13434755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72960C07545 for ; Tue, 24 Oct 2023 15:12:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=QyLw1fjdvXBQ11aNuetSEEJsfXRoPK3484/7ctxixIQ=; b=YYCrTefvfc8aH+ ICpddQIMjMwQ1beUIhWMdgF5MYopEFalbX66twAt/ZlwLzZOGwLSlakWeNaY8W4nxwioWhjDJyDLB Y/zLfFoM+cP1KpHLBFM9zTXyoP7nNMeBF2cCsw8lB8tJy0CEznwuR/+cFWzW22qyOw5vMiok4lRwt PRT+8ZYasD47MlEKcedQxt3Rr3LxSEX30Dkx+IfNm01Vn46LU81449I5cdaksOJDXg8LzS6vL83QR C/CMSQPcx/d3zT+qyWjIVScWgRyqWaPjrsNP2T967LQxGwN+Zdyytk9W1RkjebOjxwujj51S/qMhQ pG4ioVFkjF4Ayjuu4/Ng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvJ4i-00ADR7-31; Tue, 24 Oct 2023 15:12:08 +0000 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvJ4e-00ADOe-2F; Tue, 24 Oct 2023 15:12:06 +0000 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c59a4dcdacso4632731fa.1; Tue, 24 Oct 2023 08:12:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698160319; x=1698765119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ErYDPZxHlGKWRGh1uHyf/gkIgr8quGpEBSe4QaL/8Iw=; b=NxwV9llGRRgtJOwni0UZ5B6MqfbnjGhb4i+C7nZpCUZbVFfU2AbaSBQcb+bDsA2Vxy EdgAFIkcwoj/Oy2Pjf9INqUzI82lVgJAJesAeElBDPP5SAWKE1wJ9zB5NPqzq0Tk0AMT RovBgTMEbbhY6tntZc0M0cwGP00GIWxzhDgZZ8X3/wYRG5X+tqNhdaTyRUCllJsh8D2p PHg60XFVyDFtUrODiFqr5fTE3i583oHdUTFdUFR06F69mFC5vDLn4Qb+HQp14qdtLNdb N6pyqgtCsnV17r+YfAKvGLpVlfospmsb/c0DKduVv6pJWw76rHRxvKnXEflC65iZEWDf JpLw== X-Gm-Message-State: AOJu0YyjK3G+RSw8Q/N/hkYW9OsI+yeAeXcarvsWfUT37u73aq7Wq3Cl 5qeY09outy+t89su2ru+P1bOXSBK9aKMhA== X-Google-Smtp-Source: AGHT+IFN6MIIlxF6ojFKfGGggJIrTn7xmWpxlNWpMM5wUt7QTLEU4nncSA6+MbmW6iphDZD/dvcaGA== X-Received: by 2002:a05:651c:2211:b0:2c5:3139:2d04 with SMTP id y17-20020a05651c221100b002c531392d04mr9786686ljq.47.1698160319506; Tue, 24 Oct 2023 08:11:59 -0700 (PDT) Received: from flawful.org (c-f5f0e255.011-101-6d6c6d3.bbcust.telenor.se. [85.226.240.245]) by smtp.gmail.com with ESMTPSA id v1-20020a2e9f41000000b002b70a64d4desm2097562ljk.46.2023.10.24.08.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:11:59 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 0E3B61645; Tue, 24 Oct 2023 17:11:57 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160318; bh=MJQPrt0WclUUI63J7BXde/G6Km1xt1fTunHs0Soe+Yk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fzYLNWT3mkvx4BaQxNBvt0kd9p+zrbVIIZ2kzjgjVfb45e82b5LPvAmrFt+vop4lN lex7v4a2f6Dn2kY4ZuE0yRebcjmXjx3H3YPh6sqBfnC10nRovY7prsoZE9aye23HGA XQU7nvpbluYmVdyvMlxuJQx0v5yUTwuv4TJkbO7Q= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 6B53B14E3; Tue, 24 Oct 2023 17:10:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160245; bh=MJQPrt0WclUUI63J7BXde/G6Km1xt1fTunHs0Soe+Yk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aqo6fhzQyyWCdA5YuF7vVGUiRtxAL4aDO/jIDL3qJTX9sJhZx+WVDfvQoqfYZxS0r Unwk9IjPvWkP79Swc89i1BRyhJlFeLSoNB7Y+93PK/6ATRG4Xfv8DTXSGdiTsjkVdM p1uJ4MiMmqOrFNeNMtjT0A1LYLHuJ+UqpmMqrslA= From: Niklas Cassel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jagan Teki , Kever Yang , Sebastian Reichel Cc: Damien Le Moal , Niklas Cassel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 2/4] arm64: dts: rockchip: add missing mandatory rk3588 PCIe atu property Date: Tue, 24 Oct 2023 17:10:09 +0200 Message-ID: <20231024151014.240695-3-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081204_732824_553DA0A7 X-CRM114-Status: GOOD ( 14.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel From the snps,dw-pcie.yaml devicetree binding: "At least DBI reg-space and peripheral devices CFG-space outbound window are required for the normal controller work. iATU memory IO region is also required if the space is unrolled (IP-core version >= 4.80a)." All the PCIe controllers in rk3588 are using the iATU unroll feature, and thus have to supply the atu property in the device tree node. The size of the iATU region equals to: MAX(num inbound ATU regions, num outbound ATU regions) * 0x200. Where for each 0x200 region, the registers controlling the IATU_REGION_OUTBOUND starts at offset 0x0, and the registers controlling IATU_REGION_INBOUND starts at offset 0x100. pcie3x4 and pcie3x2 have 16 ATU inbound regions, 16 ATU outbound regions, so they have size: max(16, 16) * 0x200 = 0x2000 pcie2x1l0, pcie2x1l1, and pcie2x1l2 have 8 ATU inbound regions, 8 ATU outbound regions, so they have size: max(8, 8) * 0x200 = 0x1000 On the rk3588 based rock-5b board: Before this patch, dw_pcie_iatu_detect() fails to detect all iATUs: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G After this patch, dw_pcie_iatu_detect() succeeds to detect all iATUs: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G Fixes: 8d81b77f4c49 ("arm64: dts: rockchip: add rk3588 PCIe2 support") Fixes: 0acf4fa7f187 ("arm64: dts: rockchip: add PCIe3 support for rk3588") Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++--------- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 ++++++++------ 2 files changed, 20 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5519c1430cb7..d7998a9c0c43 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -119,10 +119,11 @@ pcie3x4: pcie@fe150000 { ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; - reg = <0xa 0x40000000 0x0 0x00400000>, + reg = <0xa 0x40000000 0x0 0x00300000>, <0x0 0xfe150000 0x0 0x00010000>, - <0x0 0xf0000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; + <0x0 0xf0000000 0x0 0x00100000>, + <0xa 0x40300000 0x0 0x00002000>; + reg-names = "dbi", "apb", "config", "atu"; resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; reset-names = "pwr", "pipe"; status = "disabled"; @@ -170,10 +171,11 @@ pcie3x2: pcie@fe160000 { ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; - reg = <0xa 0x40400000 0x0 0x00400000>, + reg = <0xa 0x40400000 0x0 0x00300000>, <0x0 0xfe160000 0x0 0x00010000>, - <0x0 0xf1000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; + <0x0 0xf1000000 0x0 0x00100000>, + <0xa 0x40700000 0x0 0x00002000>; + reg-names = "dbi", "apb", "config", "atu"; resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; reset-names = "pwr", "pipe"; status = "disabled"; @@ -219,10 +221,11 @@ pcie2x1l0: pcie@fe170000 { ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; - reg = <0xa 0x40800000 0x0 0x00400000>, + reg = <0xa 0x40800000 0x0 0x00300000>, <0x0 0xfe170000 0x0 0x00010000>, - <0x0 0xf2000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; + <0x0 0xf2000000 0x0 0x00100000>, + <0xa 0x40b00000 0x0 0x00001000>; + reg-names = "dbi", "apb", "config", "atu"; resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; reset-names = "pwr", "pipe"; #address-cells = <3>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 5544f66c6ff4..286d7b10b9dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1259,10 +1259,11 @@ pcie2x1l1: pcie@fe180000 { ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; - reg = <0xa 0x40c00000 0x0 0x00400000>, + reg = <0xa 0x40c00000 0x0 0x00300000>, <0x0 0xfe180000 0x0 0x00010000>, - <0x0 0xf3000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; + <0x0 0xf3000000 0x0 0x00100000>, + <0xa 0x40f00000 0x0 0x00001000>; + reg-names = "dbi", "apb", "config", "atu"; resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; reset-names = "pwr", "pipe"; #address-cells = <3>; @@ -1310,10 +1311,11 @@ pcie2x1l2: pcie@fe190000 { ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; - reg = <0xa 0x41000000 0x0 0x00400000>, + reg = <0xa 0x41000000 0x0 0x00300000>, <0x0 0xfe190000 0x0 0x00010000>, - <0x0 0xf4000000 0x0 0x00100000>; - reg-names = "dbi", "apb", "config"; + <0x0 0xf4000000 0x0 0x00100000>, + <0xa 0x41300000 0x0 0x00001000>; + reg-names = "dbi", "apb", "config", "atu"; resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id o7-20020a05651205c700b005056ccb222asm2148654lfo.105.2023.10.24.08.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:12:32 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 86FF91645; Tue, 24 Oct 2023 17:12:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160351; bh=nOWykBjoXapYzbbqt/B6vaxHD5OyGUKgl7kHm6hJUts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CfqMVtKXdWU4nwYfFVHbHd9bg4JIR981xpUEQ0AEOJcJjjGKbaKWn4SYdsFRNw4W5 ovfAgmi81UefW/sTD7NR9/3uhC0KEK26qJpEvWUyouNUZf4AtXdEbYwUgJW1wECZRB 1fHoIMOyt5dcRRtT2jqNjuC3HxaHMZVqtgkYxG3o= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 57FF514E7; Tue, 24 Oct 2023 17:10:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160246; bh=nOWykBjoXapYzbbqt/B6vaxHD5OyGUKgl7kHm6hJUts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WAnZ5gtPK8mM3eEH4aTkJGHHxRvBNJtNK4kGrk0CYhTG4AEKnQKNIPRPCcuti4T1E 7oJX1wj0eJ132vMInhvaOTYDmRkFXrouTOzfMVtn3QlFbek8AjJWbl+NL8vVFrDoIt IHHPQpg9jT9kIiC17HA5YFoWQQzPPZ0VnyYB0UAk= From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 3/4] dt-bindings: PCI: dwc: rockchip: Add dma properties Date: Tue, 24 Oct 2023 17:10:10 +0200 Message-ID: <20231024151014.240695-4-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081234_736442_04D3DEEE X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml using: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# and snps,dw-pcie.yaml does have the dma properties defined, in order to be able to use these properties, while still making sure 'make CHECK_DTBS=y' pass, we need to add these properties to rockchip-dw-pcie.yaml. Signed-off-by: Niklas Cassel --- .../bindings/pci/rockchip-dw-pcie.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 229f8608c535..633f8e0e884f 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -35,6 +35,7 @@ properties: - description: Rockchip designed configuration registers - description: Config registers - description: iATU registers + - description: eDMA registers reg-names: minItems: 3 @@ -43,6 +44,7 @@ properties: - const: apb - const: config - const: atu + - const: dma clocks: minItems: 5 @@ -65,6 +67,7 @@ properties: - const: pipe interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -88,14 +91,31 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. 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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id k16-20020ac24f10000000b00507c5216aeasm2170277lfr.263.2023.10.24.08.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:12:52 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id BAA1F1646; Tue, 24 Oct 2023 17:12:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160371; bh=ErqCJiP8U44ISh4Im9EcpFWgOzEosEpfBHoDJ+9Kgdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a6XTnA0RrJtadaLvr5GHrTZu9Fm+nIAvpOL2VT9a4z4fPnNArrlfrMRw12unO3Hzr RYDsnEXTcCy5C88zZBy/gCoaC/5uc99EcPOGovnMDjAnj3pBnshJQb6ZerWVqRiLdb ewHQJ6PasJO2zPzj0Z+GLrCsdktzJdTdcJcqdtjI= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 14D5015E1; Tue, 24 Oct 2023 17:10:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160247; bh=ErqCJiP8U44ISh4Im9EcpFWgOzEosEpfBHoDJ+9Kgdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YPetIezbIGPz/6ySQtofIO1XKUtjvcIGK/RwOaRqbMiPAspV+G+wA19XlHTfwKvMH k/lMSgd2DckEIDOIiVS1bMBWcP7XbW5zAbz7sqw9MpjZnpQqKtAbhr90knfA8lZo0u s9tgKPeOxCbawAWwZVFr7XzoLGyJVZHmuyY/0MeQ= From: Niklas Cassel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 4/4] arm64: dts: rockchip: add missing rk3588 PCIe dma properties Date: Tue, 24 Oct 2023 17:10:11 +0200 Message-ID: <20231024151014.240695-5-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081254_834448_D8D5FCE4 X-CRM114-Status: GOOD ( 13.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel The rk3588 has 5 PCIe controllers, however, according the the rk3588 TRM (Technical Reference Manual), only pcie3x4 supports the embedded DMA controller (eDMA) on the DWC PCIe controller. The size of the eDMA region equals to: 0x200 + MAX(NUM_DMA_RD_CHAN, NUM_DMA_WR_CHAN) * 0x200. Where for each 0x200 region, the registers controlling the write channel starts at offset 0x0, and the registers controlling the read channel starts at offset 0x100. pcie3x4 has two DMA read channels and two DMA write channels, so it has size: 0x200 + max(2, 2) * 0x200 = 0x600 On the rk3588 based rock-5b board, when building with CONFIG_DW_EDMA=y: Before this patch, only the iATUs are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G After this patch, both the iATUs and the eDMA channels are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G rockchip-dw-pcie a40000000.pcie: eDMA: unroll T, 2 wr, 2 rd Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index d7998a9c0c43..e072f5fe655d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -101,8 +101,13 @@ pcie3x4: pcie@fe150000 { , , , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, @@ -122,8 +127,9 @@ pcie3x4: pcie@fe150000 { reg = <0xa 0x40000000 0x0 0x00300000>, <0x0 0xfe150000 0x0 0x00010000>, <0x0 0xf0000000 0x0 0x00100000>, - <0xa 0x40300000 0x0 0x00002000>; - reg-names = "dbi", "apb", "config", "atu"; + <0xa 0x40300000 0x0 0x00002000>, + <0xa 0x40380000 0x0 0x00000600>; + reg-names = "dbi", "apb", "config", "atu", "dma"; resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; reset-names = "pwr", "pipe"; status = "disabled";