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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:05 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones Subject: [PATCH 01/14] target/riscv: Add cfg property for Zvkt extension Date: Wed, 25 Oct 2023 23:13:25 +0800 Message-Id: <20231025151341.725477-2-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=max.chou@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Vector crypto spec defines the Zvkt extension that included all of the instructions of Zvbb & Zvbc extensions and some vector instructions. Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index e7ce977189c..d8d17dedeed 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -94,6 +94,7 @@ struct RISCVCPUConfig { bool ext_zvknhb; bool ext_zvksed; bool ext_zvksh; + bool ext_zvkt; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c5ff03efce9..b9eaecb699c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -499,6 +499,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (cpu->cfg.ext_zvkt) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + /* * In principle Zve*x would also suffice here, were they supported * in qemu From patchwork Wed Oct 25 15:13:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF005C07545 for ; Wed, 25 Oct 2023 15:16:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfaM-00055A-EF; Wed, 25 Oct 2023 11:14:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfaJ-00052M-9M for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:15 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfaH-0003YS-Qc for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:15 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6b20a48522fso4869842b3a.1 for ; Wed, 25 Oct 2023 08:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246852; x=1698851652; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/NG6r7b9rhLCBcUYVSJoZtIoBWMqyY2dfwA7ypnvCr4=; b=eIlWgFBCl5qrn1s/owyq4wub5wXREv4lwVIp5/3ivoTr6BOWZnGehY3fB5wpM96AtN KVwImjogmyroMGvodoQ0/QGe7Ftx+IvZgDsGW9jJBSsacVb1NkJm9d3wxctiBwXWEZzQ A40eU/PDDXc1w4ulee0rfp4Nsc6p+195186/spVhvjw4qjQzei11gy76gP5HWfqwvvSN k4w2y5hFR/1pRHie8+wwTi8tpkXKWTIbTDaPMOn8VxV5SL+xm0NzMNYIB0zh9b/eK7m3 cbTulog1JZotnt0ZgwzB3Oz8Vnfc4TnbLCTll8H4iFT96VovshIPApRnA8BvhVQFuWBB ZYDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246852; x=1698851652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/NG6r7b9rhLCBcUYVSJoZtIoBWMqyY2dfwA7ypnvCr4=; b=FUvFvGppc3+PS8UKty6Xi547KbdPblEgATenVTl/q9RQPx6grHryb7C1pxCydU+9Qo dx+rxqOV5DbnO0uFDj2EM2MpX/0JaJ5oJ+nhUrLYVEwXbf5/zTpdja+XOGKi6Vmxo35b 0RNiNpoF0oUZ/3bHbze//HLI5M8hP/POnHz7fDCJQzEMah6tsDLMRenYgNUEvyTm6mu/ O2Keaib/ROeV4EmN51tZm5fF5iuBZff/tSpW3aqFhuVbHc8xnUCb/bWFqIdC4geZjln0 mqFj/wKbxvjA2Up3Lw0e/eeMNSH6uL9jtxjhQ7EJCmLiftExhrUvTIfDwYDWYadS9/IA 3F2Q== X-Gm-Message-State: AOJu0YwrkXPL4L2h6RVTp2JD0pmdEUxhCs6TWpdKoBmhfnxCI/qWZKke q26j5BbLd7fnrFBZpjv+c5+0n7ADGyDr8EaYDh0YyYK8KKg9C5cScFFwVPZhe5d2ysvs01n0WWN PNMPz06tMBneL7MNih64mzGPPN+yL9y1hHDCcja7v79BekBss0Kk/J5i46UXHCvun1n2I7k/QzU N6 X-Google-Smtp-Source: AGHT+IGTQDW16J1PJioj+iO35PAXQoidZlrataPdtQ4jn4VrA3N/PHnwYKnAwf23JyiolPKDs/DqgA== X-Received: by 2002:a05:6a00:14c4:b0:68a:4d66:caf with SMTP id w4-20020a056a0014c400b0068a4d660cafmr13713388pfu.34.1698246852029; Wed, 25 Oct 2023 08:14:12 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:11 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 02/14] target/riscv: Expose Zvkt extension property Date: Wed, 25 Oct 2023 23:13:26 +0800 Message-Id: <20231025151341.725477-3-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Max Chou --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2881bfa383..5099c786415 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), + ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1375,6 +1376,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), + MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), DEFINE_PROP_END_OF_LIST(), }; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:16 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones Subject: [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension Date: Wed, 25 Oct 2023 23:13:27 +0800 Message-Id: <20231025151341.725477-4-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=max.chou@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is defined as a proper subset of the Zvbb extension. And both the Zvkn and Zvks shorthand extensions replace the included Zvbb extension by Zvkb extnesion. Signed-off-by: Max Chou --- target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index d8d17dedeed..935335e5721 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -88,6 +88,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkb; bool ext_zvkg; bool ext_zvkned; bool ext_zvknha; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index b9eaecb699c..1b08f27eee4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -508,9 +508,9 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) && - !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || + cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"); return; From patchwork Wed Oct 25 15:13:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EF78C25B6D for ; Wed, 25 Oct 2023 15:16:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfaW-00057U-3Q; Wed, 25 Oct 2023 11:14:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfaV-00057H-Ak for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:27 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfaT-0003b3-No for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:27 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6bd32d1a040so5807868b3a.3 for ; Wed, 25 Oct 2023 08:14:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246863; x=1698851663; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CeuH98/Jn7U3mEiXrbYPk6TZIyqSxoArWfMyJGiEIgA=; b=jZbkiVQCWED4PyMLll65g+vf8y9qVHJ3/risrvUP87w/NKibJ+puAddTUgZfEd5e6X gGQrDvypg2xcXfgeTomtd1gzCUnQ1zXPAozT1FqZnjl0BzFSoBdUDXablnstF1O4Jksj H9BnEvCh5tqBaLYRS0fNJjB0KWZ7/9VqfqgtP/HKyXli9UlAhvfaJ7+EJBA9vGzawo6s VqtGjw96yBT1Wm6nOa+w+YrNfXuQDGc830H9XY5x1vDMTc2cSvjFP79mnzbIi28dsiNu tj5ASoHZhWIpvzZlhMW9q9MsgmMRQl3crzQoEe4msY3XkaRBVtX/D5sSw6sfvnOz9OKC u9iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246863; x=1698851663; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CeuH98/Jn7U3mEiXrbYPk6TZIyqSxoArWfMyJGiEIgA=; b=kJ5OtZCh1Le3UBYyhLAVMQGjoV0dxYedz/fPIyBG18bt+bsydaO811jlx7oh84BGhU QxZRpt/YjcWSvJibIcH+zMklbNOsUt9s2p46B1jclTW2VREodSfCJQYX0t2poY1KI7K9 my5Kmkaa5iPtYYiRmiBhkbuO2XD9a30nZC/Dwy6d8NvCo5DP46JatDE2cn0Q/jhM0IcA ksXUKbtJXPd5Oe+r2/71W2K2SxQz/ez0Azl8guNjjUWdSr2/jf4BKkOH182SsgugAAcI vQC2S8x8pnO2xGZjQVnwljisCnY+qjhMofFk1AocG8MkBR10YOdaq5WhDVYutQyHWcbP bypg== X-Gm-Message-State: AOJu0YzTNcleB4OwjunxS/Fh0IZsRkErtKogi2w56xXxNEYhyQ3bjtx0 iN0McGLih2BzJXrXXI+d0Ja2uvI7a2Z2YEUhgGDxpv2JQHiobcFmgLzgW21tRyjRyF+3ObxsXzt 7NsGCtZlSR4E9xjxEdyielmlLmk/YQhs//9p5mXupyYxublY1FZY3vbBrRoJSiZHkyz7i390opM AC X-Google-Smtp-Source: AGHT+IE89PdMGMXk0zWYEUt1M6ffLvdtSmEBaqCfRzDdk3n479TlV0NuiVRYwf08L5yxC59wPqzcfQ== X-Received: by 2002:a05:6a00:158c:b0:690:fe13:1d28 with SMTP id u12-20020a056a00158c00b00690fe131d28mr18751411pfk.33.1698246862683; Wed, 25 Oct 2023 08:14:22 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:22 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Nazar Kazakov , Lawrence Hunter Subject: [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb Date: Wed, 25 Oct 2023 23:13:28 +0800 Message-Id: <20231025151341.725477-5-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The Zvkb extension is a proper subset of the Zvbb extension and includes following instructions: * vandn.[vv,vx] * vbrev8.v * vrev8.v * vrol.[vv,vx] * vror.[vv,vx,vi] Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++++++++++++++--------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc index e691519ed78..3801c16829d 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -112,24 +112,27 @@ GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) return false; \ } -static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) +static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a) { - return opivv_check(s, a) && s->cfg_ptr->ext_zvbb == true; + return opivv_check(s, a) && + (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true); } -static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) +static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a) { - return opivx_check(s, a) && s->cfg_ptr->ext_zvbb == true; + return opivx_check(s, a) && + (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true); } /* vrol.v[vx] */ -GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) -GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvkb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvkb_vx_check) /* vror.v[vxi] */ -GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) -GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) -GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check) +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvkb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvkb_vx_check) +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, + zvkb_vx_check) #define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ @@ -147,8 +150,8 @@ GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx_check } /* vandn.v[vx] */ -GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) -GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvkb_vv_check) +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check) #define GEN_OPIV_TRANS(NAME, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ @@ -188,8 +191,16 @@ static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) vext_check_ss(s, a->rd, a->rs2, a->vm); } -GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) -GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) +static bool zvkb_opiv_check(DisasContext *s, arg_rmr *a) +{ + return (s->cfg_ptr->ext_zvbb == true || s->cfg_ptr->ext_zvkb == true) && + require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, zvkb_opiv_check) +GEN_OPIV_TRANS(vrev8_v, zvkb_opiv_check) GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) From patchwork Wed Oct 25 15:13:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C6C69C0032E for ; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:26 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 05/14] target/riscv: Expose Zvkb extension property Date: Wed, 25 Oct 2023 23:13:29 +0800 Message-Id: <20231025151341.725477-6-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=max.chou@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Max Chou --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5099c786415..992f8e0f7b0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), @@ -1370,6 +1371,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { /* Vector cryptography extensions */ MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), + MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false), MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false), From patchwork Wed Oct 25 15:13:30 2023 Content-Type: text/plain; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:32 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones Subject: [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions Date: Wed, 25 Oct 2023 23:13:30 +0800 Message-Id: <20231025151341.725477-7-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=max.chou@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Vector crypto spec defines the NIST algorithm suite related extensions (Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions. Signed-off-by: Max Chou --- target/riscv/cpu_cfg.h | 3 +++ target/riscv/tcg/tcg-cpu.c | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 935335e5721..fd07aa96a27 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -96,6 +96,9 @@ struct RISCVCPUConfig { bool ext_zvksed; bool ext_zvksh; bool ext_zvkt; + bool ext_zvkn; + bool ext_zvknc; + bool ext_zvkng; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 1b08f27eee4..e460701a13c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -499,6 +499,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + /* + * Shorthand vector crypto extensions + */ + if (cpu->cfg.ext_zvknc) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + + if (cpu->cfg.ext_zvkng) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); + } + + if (cpu->cfg.ext_zvkn) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); + } + if (cpu->cfg.ext_zvkt) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); From patchwork Wed Oct 25 15:13:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436418 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D56AAC0032E for ; Wed, 25 Oct 2023 15:15:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfaz-0005f0-OW; Wed, 25 Oct 2023 11:14:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfap-0005X8-TD for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:48 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfag-0003eL-Rs for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:47 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6bd0e1b1890so4706376b3a.3 for ; Wed, 25 Oct 2023 08:14:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246877; x=1698851677; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=28soGqZ4hmvdB2DBr+8fDTCxvQalUe0nHRzFfVeJIWI=; b=OSBEF9wVIo4XnQfvtUkkqfifwigQrUJql8cBHu/wyMew1CnBaQy3N5ZJU/SECR3xpb Q1JgkMHzz4tdf27GzylovroCUnsiXgnYetnvDQlpArOxKvGWgd1rL4/E8rRlSvMDcvLM jS2sasd09gyDTmRdKxbojRjlzZN/+vx3cP8Hn4K8gWFDBdbcajryOWxXka0vpeeUOUSi 6vN4HagN/Xf7yR6rKQglo8ogkvUg0jIil5182kugwzeIJiN2rMTsC27os7yWFyJ6xRVq IwXiBGZ8eHrI5uh/Rb4p1mdGNz5V+aiZ1ifmjHf2qV8pXuTIMZWhO2S/nsm8qQFT9RjF obGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246877; x=1698851677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=28soGqZ4hmvdB2DBr+8fDTCxvQalUe0nHRzFfVeJIWI=; b=JQaQlbkmFH9CpAOTg4OYRhF52e5kHytbS6Vx/b63yzD+7y+jWRvWycPymUFllwRHNL b1DwLRhE9YeReNfzRpqCN64/jRfCagGihDOSQ2flngqPJUMesAHs8c+rkc/YTIs8vbMV uXkChSxwg5b49pjP7HJ5sh2JygjHf2VFtu7iN3GDcjooMjq7NEmTUWoE+zjpvC/YozHC gTQPqHpIhLp1pyogeguDYlei/kNhkxMBU2ZxFphKzsy6/dKiCH/FG2NgLytIXFznWi8U v8OonTmI0ZR7U+/yMOqOdHxbDxDGKJhRDcwZvrL/pQPsDedaZDxxvPAf4SQOouhDLUYQ sQEg== X-Gm-Message-State: AOJu0YzHyqyI9tihlpdbxOr+AtQdM1lKzgDtTWieh/GSGVeFzwM8x1ER 2rDgyDqHwbSfuA78Fj2lbhDxGkEswvwBlQiA8F1uLyyx7azEh4UY/KdzVCeejhUvxqcUPOosC8N UAhCjwhcqEvtQ1zvDI+q625zQBW48cxE4ie9Y7npYhbDmJbKuOaNPsGJNveNEEZwHN/bawo3V0k vG X-Google-Smtp-Source: AGHT+IGxcCCnBFT2tnBh2OPHcsWBjFpMJruTMgDQckfw3odXjYS2sxLVkvZmB7dqTYIYIwJMU8eByw== X-Received: by 2002:a05:6a20:1609:b0:165:2969:9328 with SMTP id l9-20020a056a20160900b0016529699328mr6555685pzj.22.1698246877224; Wed, 25 Oct 2023 08:14:37 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:37 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties Date: Wed, 25 Oct 2023 23:13:31 +0800 Message-Id: <20231025151341.725477-8-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=max.chou@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose the properties of NIST Algorithm Suite related extensions (Zvkn, Zvknc, Zvkng). Signed-off-by: Max Chou --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 992f8e0f7b0..8eae8d3e59c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -127,7 +127,10 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), + ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn), + ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), + ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), @@ -1379,6 +1382,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), + MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), + MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), + MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), DEFINE_PROP_END_OF_LIST(), }; From patchwork Wed Oct 25 15:13:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F3EEC25B47 for ; Wed, 25 Oct 2023 15:17:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfao-0005W8-JF; Wed, 25 Oct 2023 11:14:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfan-0005Tx-05 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:45 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfal-0003fD-8Q for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:44 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6b1e46ca282so5803679b3a.2 for ; Wed, 25 Oct 2023 08:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246881; x=1698851681; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=npJ2K69OOSsKJtanlFl7eXChj2RfZqQfMPOCGuCNX+0=; b=HcIN8buqXPyvo7Lhc5+Ao1VjxdWA1j4tqVD1vcGDBXok2OU5hWb77nOf325QkZSGVE 9ZkIh3AeaGJBKr4xWWGc7hO4j9oMHPkXQwfAPGLk4qifj0/M0wDLQJzPec+8z2H0jYIJ QIMR2BoKmEC6is55C92s9yE3iXhnD49w2PRDBi1fCBNWAIHBgmNIJW8ACaFV4Sc080h/ OkKbsbk/k7uV0DgzSvkJE7fG6Ts1c4rlPPxid57XmJaCsG8G98f2EcG0QbPGBfGpXQoL WIhbildAi9z/+KcZU2JT14txeYoJXPixX93xBSXOYx/5/N8ZHrwLvXm8HbzODsvOn4QW 72Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246881; x=1698851681; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=npJ2K69OOSsKJtanlFl7eXChj2RfZqQfMPOCGuCNX+0=; b=vQlanZljIhQrUp6aZEg1BoZYmmkBvDWe8R/2k550Lv3ISVkMRrRn9Zo/tZiIAm/SzY ML8F0E/JjTuUe/aXDB56qVB5TIJEhLDaNJ9h/ypz430pyHCAsy+taRCLSc09vllMX62m bUrbzz7+D3cixs3ki2Z4N1wMKVIcpfxU2qb8OaoaSmQIKOLxIGJYsLp/4ehlqjNkw0W+ 3cbxYOPLfwxYLcoZGESWR/4aD3BRPKOfHvTbxpjqTcMUW1ZwdLhpQYbKj7BH3i49TNFw dYaqw9JN6JtG+H6BeaksQvLIBfZN7ZIgKnCSaTVE/xP3ER39FncB2L3KaEEqCnfoRDVp gSTw== X-Gm-Message-State: AOJu0YwUvx8QsAo2eC/kZ6AZ6w3hxKWdDd8hcfbK4T8fm9jD8uKkJX4t nl2MX2FGU59Ci8DYNJ7KF7KNBXKgu95SdrLwdNBMJEgeLWNCRXAYw1XEeRJF5qPDxIXX3Lg3HeE 1ETL1pN5ehOr+dz9uBc+Dy1yXA+QlcuVVfOOYw3rgiZ9e1Uw4u9KuVWwTDmMBAQ38A/YJGRl5st hO X-Google-Smtp-Source: AGHT+IGxeT1XYysuWhzP+XGjVchb7sQ76Y9lFVuO/ahOs9u4ssberv2hYxI/vPlJz08p3CKKT1+D9A== X-Received: by 2002:a05:6a21:788d:b0:13a:6bca:7a84 with SMTP id bf13-20020a056a21788d00b0013a6bca7a84mr6707340pzc.44.1698246881497; Wed, 25 Oct 2023 08:14:41 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:41 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Andrew Jones Subject: [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions Date: Wed, 25 Oct 2023 23:13:32 +0800 Message-Id: <20231025151341.725477-9-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Vector crypto spec defines the ShangMi algorithm suite related extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto extensions. Signed-off-by: Max Chou --- target/riscv/cpu_cfg.h | 3 +++ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fd07aa96a27..7b0ca657a6a 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -99,6 +99,9 @@ struct RISCVCPUConfig { bool ext_zvkn; bool ext_zvknc; bool ext_zvkng; + bool ext_zvks; + bool ext_zvksc; + bool ext_zvksg; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e460701a13c..f9023ca75c7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -519,6 +519,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); } + if (cpu->cfg.ext_zvksc) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); + } + + if (cpu->cfg.ext_zvksg) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true); + } + + if (cpu->cfg.ext_zvks) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true); + } + if (cpu->cfg.ext_zvkt) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true); From patchwork Wed Oct 25 15:13:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47E82C0032E for ; Wed, 25 Oct 2023 15:17:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfas-0005Z0-Ql; Wed, 25 Oct 2023 11:14:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfaq-0005X9-EL for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:48 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfao-0003fy-W1 for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:48 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6bb4abb8100so4866342b3a.2 for ; Wed, 25 Oct 2023 08:14:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246885; x=1698851685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xkwlpLYypRxSWiGHgKxtQp1RAJeqYUNkInw/XRm9smE=; b=Tx616clsBuWXhfVfbRfSkfmgZBvVnrilfxTi9P3N0FEYzGf6TxnPxFxR2iF9nPp3hg kNtqvi/4d0M/OgynWaVakvtLORZsdX9hkXPWbOdJbrcazDBqmfk4+TFPlAuT/Uwh1XBb pQW3st99wLrimDtg2BftvpGxTEC2aCCaeeAosLKZEnK6oYnXjHJ5DAvDCOyy9rY5LZYA hfhYlaC6peWDBz+f0e6uVLEsFes4Us0vkYnjMNiHB5A0rf53JE/+F67/v/i9QuAfXTdD 9bukkWjTP9BLAHUvokoseKQ86Ifauctfvs+42TZpJgLBocURlh+mI8524JOhObo2lAGh e9sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246885; x=1698851685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xkwlpLYypRxSWiGHgKxtQp1RAJeqYUNkInw/XRm9smE=; b=qJPC6EKkDfsz7ff4CNdOLqvLxoAjfH5kmdxhaaY+CQmvr7GErbap7axtEuee5AlYrN hbWO/PrhsqdJUoj/AB2OlRc8Z9Cvj5cxyV5fyFmnG9ek11Rp2ZbNeKndpKdkRch2KtCz kXnxZzicOXunJiNTZalH09s2jZSF4jwPs4q/h8yZqgIVsymh1BA6NmgDWNf1OBpfKPbL jzgnWGRjHTUbIoyyacyya7hTyTuInY06R3BiESB37jsMIYUHy8yzMDUNtNZ5ZxKpygIp Y+lvgvQmjgiLgvzU1xfk6wdodoHZEY4aMQWCHXMb9zE3QeUs3F6YlyyRvOBJNfbXn5Ov 2j2w== X-Gm-Message-State: AOJu0YxXV4o3q/h85NEjMwvfF1EtMHOhr0BShtCCBxitjNZE19zlxFct gBNs5VxnggXEM7wBWCAp6P3Bhzyy1YqIRLsgB3+7IEVi0O/1VwmyFmXjyod098RkWIxcjEINmiP j5VLNz6KEkNMZjlBbrmk6sKfOUx5pyP0Vj4V7uawYWx5rwXXo3wkn1PSdDGF1XrHuphfDgyzm8l nI X-Google-Smtp-Source: AGHT+IFncs2PD3ySzb9eft0mNl8wy3evf61jV1TdCrzvKnTumaRbugZ+e6WjA6LcXTpFY4Od7RBnog== X-Received: by 2002:a05:6a20:3c8a:b0:17e:45d0:7036 with SMTP id b10-20020a056a203c8a00b0017e45d07036mr6616389pzj.11.1698246885399; Wed, 25 Oct 2023 08:14:45 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:45 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties Date: Wed, 25 Oct 2023 23:13:33 +0800 Message-Id: <20231025151341.725477-10-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose the properties of ShangMi Algorithm Suite related extensions (Zvks, Zvksc, Zvksg). Signed-off-by: Max Chou --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8eae8d3e59c..1709df76a9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -133,7 +133,10 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks), + ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), + ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), @@ -1385,6 +1388,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), + MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false), + MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false), + MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false), DEFINE_PROP_END_OF_LIST(), }; From patchwork Wed Oct 25 15:13:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01107C07545 for ; Wed, 25 Oct 2023 15:15:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfax-0005cl-BH; Wed, 25 Oct 2023 11:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfau-0005Zk-BY for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:52 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfas-0003iB-PR for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:14:52 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6934202b8bdso5639648b3a.1 for ; Wed, 25 Oct 2023 08:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246889; x=1698851689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PWrYGN8E3tylotAH/OAbUnzxmsSVvrM8xFBXqtl296k=; b=guQmR5VlmFytiDsbWHRptftsuNDvrW78PCrZGfR7M68KACGmh5j+B+hSl/2mR3CQuq lpCq0iY9sfRHjBvcNxW1Eo7Dt2VuEbJEBmNUWMdp/mxuF86nyj0zYqTdxpyht7axLxZ6 8/twx0y8qkg6EBZ9ExW7qtl5T07ahVxRf+RdTDnYOaMeCBc59lDoDphrGo1Hn44sT2F9 6TqO0gNzPUHKH1c02MeCXWocBHozjnRV5geF5mHWAncUB9qIlGFl8WoZsT6vuwwVv+Ee c8ppHw6ovamZf2eTzGXpt03rvnpql/IWuUzErptt2LB78yAC1JvPkeVre5g92sVrK2// 1Aww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246889; x=1698851689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PWrYGN8E3tylotAH/OAbUnzxmsSVvrM8xFBXqtl296k=; b=vVzGQ6VVNsu1X6WW0dV0dcNh9u8/2BdsOvfZidW+q6XhvCOlZ4eNF3ixxFRsdXRZS5 hWhJBj0Xu22h89xxz0huOhTAUDI1J7GDwcLEMAH2ShbYmeFknn0z9AGOHzWiCDVT0Iho OlsK73Cv8TWd34CBdgOOM+5RafBZnnyK2EvLEt21CVAOzN/Gu3xB0zhUad2bWK0j6Omz PwE9owkFPX6OK4/0CQuSk7o2CwHbphm2rq3Yi9D9/gZc2SUAEfihe/+x6mb+4wBD+ZuW NGtmroJkUaD09tAKBBNsiYBRpqBD7gF7FbkbUMTwXLFhj9qLPHGNWPc17PCQpHUHk1o5 dkmA== X-Gm-Message-State: AOJu0YztcpI43nFjF2JH2LSeKGZEODPQHn9vI1DaJYyQbp/eKY4/xu4v iFyzLXfbPN+9TvGPITjpiocHmgLCkGz2yVqqLeVAFN4kZ1FvichVeUzA8O9zpS/a91xrL/QiCCN UAw1GboSIWsWo36wQTn1h7+K7BZxNq1xZE9ShGmHz+kHpFN8tPzenCs734IMO3YQnqVc4LpiV6x WF X-Google-Smtp-Source: AGHT+IG5aaYA5QecqjCrJdpz/r46e3szGdy1VrE7EdoCmoiiEP3RCqxCJeLv78rkc3SSUJudJb5D5Q== X-Received: by 2002:a05:6a20:840b:b0:17b:426f:829 with SMTP id c11-20020a056a20840b00b0017b426f0829mr7469494pzd.37.1698246889183; Wed, 25 Oct 2023 08:14:49 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:48 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions Date: Wed, 25 Oct 2023 23:13:34 +0800 Message-Id: <20231025151341.725477-11-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Because the vector crypto specification is ratified, so move theses extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions. Signed-off-by: Max Chou --- target/riscv/cpu.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1709df76a9b..5b5805399ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1342,6 +1342,24 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), + /* Vector cryptography extensions */ + MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false), + MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false), + MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false), + MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false), + MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false), + MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false), + MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false), + MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false), + MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false), + MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false), + MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false), + MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false), + MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false), + MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false), + MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false), + MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false), + DEFINE_PROP_END_OF_LIST(), }; @@ -1374,24 +1392,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false), MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false), - /* Vector cryptography extensions */ - MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), - MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), - MULTI_EXT_CFG_BOOL("x-zvkb", ext_zvkg, false), - MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), - MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), - MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false), - MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), - MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), - MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), - MULTI_EXT_CFG_BOOL("x-zvkt", ext_zvkt, false), - MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), - MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), - MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), - MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false), - MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false), - MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false), - DEFINE_PROP_END_OF_LIST(), }; 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Signed-off-by: Max Chou --- disas/riscv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/disas/riscv.h b/disas/riscv.h index 8abb578b515..b242d73b25e 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -274,6 +274,7 @@ enum { #define rv_fmt_vd_vs2_fs1_vm "O\tD,F,4m" #define rv_fmt_vd_vs2_imm_vl "O\tD,F,il" #define rv_fmt_vd_vs2_imm_vm "O\tD,F,im" +#define rv_fmt_vd_vs2_uimm "O\tD,F,u" #define rv_fmt_vd_vs2_uimm_vm "O\tD,F,um" #define rv_fmt_vd_vs1_vs2_vm "O\tD,E,Fm" #define rv_fmt_vd_rs1_vs2_vm "O\tD,1,Fm" From patchwork Wed Oct 25 15:13:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E248C25B70 for ; Wed, 25 Oct 2023 15:18:03 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfb7-0005hv-0P; Wed, 25 Oct 2023 11:15:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfb2-0005gF-Km for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:15:01 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfb0-0003jq-4Q for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:15:00 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6b1e46ca282so5804038b3a.2 for ; Wed, 25 Oct 2023 08:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246897; x=1698851697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uhhXgiA9ijhkCgdvzjre6qvwHLpR2uYfFwrcGxeZDYQ=; b=jBmRWAaGObUfmYDv2nPYBbK/f4OtSnKNApg1F2VPh7imCMjxE9qf42WAnQSfOqkpE+ mheFsqlZ2F7yZRUWDqDHSKlCdRa3f7HAHd29AVcFCYufaEpCaeuy085+gQudrqIwraAG ZAOtwjMhGyPOHA7P6oQQBhhngNRxUef7rfLlfZvh8PkujOEnGPhAnsKWeqAZRp81/xit Mk7yP4ZacBY25eWeQSrmb35JSlDGGmDd+c3gejGFI/KpMinCBjvZy1p+vfHXkAClN4FP ZWZgP5L4TWx55kJqvJU0AL5lFKHEY8XpnLIlMZlqMhLVWWUTUMaWGpSsZIwHYwARV00/ ut/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246897; x=1698851697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uhhXgiA9ijhkCgdvzjre6qvwHLpR2uYfFwrcGxeZDYQ=; b=i0DfqTz1uH9JelYKKQTJeELVA7MwTNZHTfeJplZnRrDxHUvd0YLUoByrBeQgj3IHEn BlTV6McrnEkJ/+pMzMo8S8b9TOJRWxP8FDxaekGuInyxRxO71wWMZMw50QyHl9e49nrY e1jxVlIqcD3ZnVel1r9ilDVJj9Bl8eFJ8wXmVICGigHdEbp7BKWKDxgKIVqSZdBC53eX +nxK4crlaBJotEEd72F/bkiuOh0w+WgY1N8YNeRaFG+MlI6MzHJo3XM9dGhkqaoj/k7n BLKgu6BMe+3UqydwFnJZqXcPUXfZpfC0bfZBpnAc8xd0zP5TurDLpDyTlFn+wC5nD93U +Z5A== X-Gm-Message-State: AOJu0Yy0IC/yRKPcaTOU2YnW6kmcn9cIhm0My7yhYYz6rGahLm+T1cd3 aRWQTVrhab37KQgdNXQWOssSfTan9D5K/K9AtQtKewSVMHYcTbPJZmt2GjJjKNEllVTs/0shnHz VcgQ42s49PnNWdGSrd/VbAoxyeqc7TXCVzasLEhcTXdBYj4lfBIl/a8kxyuC7E4FnkkO5AKcxZm Um X-Google-Smtp-Source: AGHT+IHiNV7l5886K5RJyRZEx4y7KbRDZ5rGOL52oOvaLUaI2tL1RGQ9R2mahd0i/u63Orc5IXa8IA== X-Received: by 2002:a05:6a00:2e97:b0:692:a727:1fdd with SMTP id fd23-20020a056a002e9700b00692a7271fddmr18972961pfb.4.1698246896595; Wed, 25 Oct 2023 08:14:56 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:56 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis Subject: [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi Date: Wed, 25 Oct 2023 23:13:36 +0800 Message-Id: <20231025151341.725477-13-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=max.chou@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou --- disas/riscv.c | 11 +++++++++++ disas/riscv.h | 1 + 2 files changed, 12 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 8e89e1d1157..6d60033abab 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst) return (inst << 34) >> 54; } +static uint32_t operand_vzimm6(rv_inst inst) +{ + return ((inst << 37) >> 63) << 5 | + ((inst << 44) >> 59); +} + static uint32_t operand_bs(rv_inst inst) { return (inst << 32) >> 62; @@ -4393,6 +4399,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) dec->imm = operand_vimm(inst); dec->vm = operand_vm(inst); break; + case rv_codec_vror_vi: + dec->rd = operand_rd(inst); + dec->rs2 = operand_rs2(inst); + dec->imm = operand_vzimm6(inst); + break; case rv_codec_vsetvli: dec->rd = operand_rd(inst); dec->rs1 = operand_rs1(inst); diff --git a/disas/riscv.h b/disas/riscv.h index b242d73b25e..19e5ed2ce63 100644 --- a/disas/riscv.h +++ b/disas/riscv.h @@ -152,6 +152,7 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_vror_vi, rv_codec_zcb_ext, rv_codec_zcb_mul, rv_codec_zcb_lb, From patchwork Wed Oct 25 15:13:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 628D8C0032E for ; Wed, 25 Oct 2023 15:16:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvfbB-0005kV-7L; Wed, 25 Oct 2023 11:15:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvfb8-0005iQ-QH for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:15:07 -0400 Received: from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvfb3-0003l5-Hv for qemu-devel@nongnu.org; Wed, 25 Oct 2023 11:15:06 -0400 Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-5840bb16101so3325660eaf.3 for ; Wed, 25 Oct 2023 08:15:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1698246900; x=1698851700; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N3EycMYI800mCjoad+AIrSiAoDJQpEk4wNkfXQSFIHE=; b=ZN59RBTZuNJN6iGMGa9Ldw9Vtqx3h6G4liGf7RPn7UNvx0KbDR+zRlZaHwTJY6AFgD y8zbSdXQCa1f9+8QBAJYWf0JS5GEanTPJMHEcjbGB52flLf+G6jujxCDE4kFwZUyEAol AG1D2MPv/bw4GALwn7F4BLX0zIddSvHLTbAikszCxEO/aC8DLDBSAQ/ece3KyYMEb8ry 5Ycfbsk3wzSn8NeD1rpBxhzNqzFyiN0nsMFFkKmPBdLups0LlepY6wIY7eJM81SMK9Rv agB1/Ca2RBTEz2wX2ReJnCI3WJCVMojzBgkPfZTFyC9CKnb14C4I0S3O8r7WXoy2K61+ RdYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698246900; x=1698851700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N3EycMYI800mCjoad+AIrSiAoDJQpEk4wNkfXQSFIHE=; b=diWtq6xvX41pivt1Usx9a6dUC3JybkhTnJizQtLQ5kya3NMxf6xO6j/Lrq/8LOziWO 1lhCS7pYHZdOVBBDa0MCXJb7HA3vZ5N579XWRHq/m8aQNu4Efs7cncswo08UOHg3ZcP7 4MVW9NXwIPsGAr5mBhXkVZIChFygDInGZw/eNqJLPZPrjTnygTpDfxAaxRVhqQwnWQ3Y LskDuxwaJFCEVqcaWVItsN29ZFK32IknqUut40WJxHzoSkA0z0NSfckPk3kTNVuih5dj uXZTb0viAZm3RC6ooY3rKPGSI7YQ29EcfqB8EldjSuOlF5ADq4siOd/6cy5yShOrxEH8 /mKg== X-Gm-Message-State: AOJu0YyeHywMCx5JYbk5HKSpzRCN57iF8CNHZy2ALtZJSAON3LGWQr43 qtUvh8ayJC/2Jl2SGclzS1/yYf5VcuU3zRvE2fr/nhx9alsi0CC8QmFz8KdlgcXgqondXlR4fM+ 6mFLOfm4oRhA2oVYcFbGESgOXnRHkWdiabNZguLe3XXFcgbabvJs4y40niOrmgcGn8DVCITA/Fk 9l X-Google-Smtp-Source: AGHT+IGIpaRSQUsFJWpAcTdTX7cHMgleJXAwuMHM8uioSLV4f7U56eNGdShcLhz00F5Dwd1ln1xKhg== X-Received: by 2002:a05:6359:a04:b0:168:d169:44 with SMTP id el4-20020a0563590a0400b00168d1690044mr10539780rwb.1.1698246899907; Wed, 25 Oct 2023 08:14:59 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:59 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis Subject: [PATCH 13/14] disas/riscv: Add support for vector crypto extensions Date: Wed, 25 Oct 2023 23:13:37 +0800 Message-Id: <20231025151341.725477-14-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=max.chou@sifive.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch adds following v1.0.0 ratified vector crypto extensions support to the RISC-V disassembler. - Zvbb - Zvbc - Zvkb - Zvkg - Zvkned - Zvknha - Zvknhb - Zvksed - Zvksh Signed-off-by: Max Chou --- disas/riscv.c | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 6d60033abab..5bfa9390c45 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -862,6 +862,47 @@ typedef enum { rv_op_fltq_q = 831, rv_op_fleq_h = 832, rv_op_fltq_h = 833, + rv_op_vaesdf_vv = 834, + rv_op_vaesdf_vs = 835, + rv_op_vaesdm_vv = 836, + rv_op_vaesdm_vs = 837, + rv_op_vaesef_vv = 838, + rv_op_vaesef_vs = 839, + rv_op_vaesem_vv = 840, + rv_op_vaesem_vs = 841, + rv_op_vaeskf1_vi = 842, + rv_op_vaeskf2_vi = 843, + rv_op_vaesz_vs = 845, + rv_op_vandn_vv = 846, + rv_op_vandn_vx = 847, + rv_op_vbrev_v = 848, + rv_op_vbrev8_v = 849, + rv_op_vclmul_vv = 850, + rv_op_vclmul_vx = 851, + rv_op_vclmulh_vv = 852, + rv_op_vclmulh_vx = 853, + rv_op_vclz_v = 854, + rv_op_vcpop_v = 855, + rv_op_vctz_v = 856, + rv_op_vghsh_vv = 857, + rv_op_vgmul_vv = 858, + rv_op_vrev8_v = 859, + rv_op_vrol_vv = 860, + rv_op_vrol_vx = 861, + rv_op_vror_vv = 862, + rv_op_vror_vx = 863, + rv_op_vror_vi = 864, + rv_op_vsha2ch_vv = 865, + rv_op_vsha2cl_vv = 866, + rv_op_vsha2ms_vv = 867, + rv_op_vsm3c_vi = 868, + rv_op_vsm3me_vv = 869, + rv_op_vsm4k_vi = 870, + rv_op_vsm4r_vv = 871, + rv_op_vsm4r_vs = 872, + rv_op_vwsll_vv = 873, + rv_op_vwsll_vx = 874, + rv_op_vwsll_vi = 875, } rv_op; /* register names */ @@ -2008,6 +2049,47 @@ const rv_opcode_data rvi_opcode_data[] = { { "fltq.q", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, { "fleq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, { "fltq.h", rv_codec_r, rv_fmt_rd_frs1_frs2, NULL, 0, 0, 0 }, + { "vaesdf.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdf.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdm.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesdm.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesef.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesef.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesem.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaesem.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vaeskf1.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaeskf2.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vaesz.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vandn.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vandn.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vbrev.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vbrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vclmul.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vclmul.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vclmulh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vclmulh.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vclz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vcpop.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vctz.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vghsh.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vgmul.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vrev8.v", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 }, + { "vrol.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vrol.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vror.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vror.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vror.vi", rv_codec_vror_vi, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "vsha2ch.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsha2cl.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsha2ms.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsm3c.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm3me.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1, NULL, 0, 0, 0 }, + { "vsm4k.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm, NULL, 0, 0, 0 }, + { "vsm4r.vv", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vsm4r.vs", rv_codec_v_r, rv_fmt_vd_vs2, NULL, 0, 0, 0 }, + { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, + { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, + { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, }; /* CSR names */ @@ -3176,6 +3258,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 0: switch ((inst >> 26) & 0b111111) { case 0: op = rv_op_vadd_vv; break; + case 1: op = rv_op_vandn_vv; break; case 2: op = rv_op_vsub_vv; break; case 4: op = rv_op_vminu_vv; break; case 5: op = rv_op_vmin_vv; break; @@ -3198,6 +3281,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 19: op = rv_op_vmsbc_vvm; break; + case 20: op = rv_op_vror_vv; break; + case 21: op = rv_op_vrol_vv; break; case 23: if (((inst >> 20) & 0b111111) == 32) op = rv_op_vmv_v_v; @@ -3226,6 +3311,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 47: op = rv_op_vnclip_wv; break; case 48: op = rv_op_vwredsumu_vs; break; case 49: op = rv_op_vwredsum_vs; break; + case 53: op = rv_op_vwsll_vv; break; } break; case 1: @@ -3323,6 +3409,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 9: op = rv_op_vaadd_vv; break; case 10: op = rv_op_vasubu_vv; break; case 11: op = rv_op_vasub_vv; break; + case 12: op = rv_op_vclmul_vv; break; + case 13: op = rv_op_vclmulh_vv; break; case 16: switch ((inst >> 15) & 0b11111) { case 0: if ((inst >> 25) & 1) op = rv_op_vmv_x_s; break; @@ -3338,6 +3426,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 5: op = rv_op_vsext_vf4; break; case 6: op = rv_op_vzext_vf2; break; case 7: op = rv_op_vsext_vf2; break; + case 8: op = rv_op_vbrev8_v; break; + case 9: op = rv_op_vrev8_v; break; + case 10: op = rv_op_vbrev_v; break; + case 12: op = rv_op_vclz_v; break; + case 13: op = rv_op_vctz_v; break; + case 14: op = rv_op_vcpop_v; break; } break; case 20: @@ -3406,6 +3500,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 17: op = rv_op_vmadc_vim; break; + case 20: case 21: op = rv_op_vror_vi; break; case 23: if (((inst >> 20) & 0b111111) == 32) op = rv_op_vmv_v_i; @@ -3437,11 +3532,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 45: op = rv_op_vnsra_wi; break; case 46: op = rv_op_vnclipu_wi; break; case 47: op = rv_op_vnclip_wi; break; + case 53: op = rv_op_vwsll_vi; break; } break; case 4: switch ((inst >> 26) & 0b111111) { case 0: op = rv_op_vadd_vx; break; + case 1: op = rv_op_vandn_vx; break; case 2: op = rv_op_vsub_vx; break; case 3: op = rv_op_vrsub_vx; break; case 4: op = rv_op_vminu_vx; break; @@ -3466,6 +3563,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 19: op = rv_op_vmsbc_vxm; break; + case 20: op = rv_op_vror_vx; break; + case 21: op = rv_op_vrol_vx; break; case 23: if (((inst >> 20) & 0b111111) == 32) op = rv_op_vmv_v_x; @@ -3494,6 +3593,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 45: op = rv_op_vnsra_wx; break; case 46: op = rv_op_vnclipu_wx; break; case 47: op = rv_op_vnclip_wx; break; + case 53: op = rv_op_vwsll_vx; break; } break; case 5: @@ -3554,6 +3654,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 9: op = rv_op_vaadd_vx; break; case 10: op = rv_op_vasubu_vx; break; case 11: op = rv_op_vasub_vx; break; + case 12: op = rv_op_vclmul_vx; break; + case 13: op = rv_op_vclmulh_vx; break; case 14: op = rv_op_vslide1up_vx; break; case 15: op = rv_op_vslide1down_vx; break; case 16: @@ -3686,6 +3788,41 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 7: op = rv_op_csrrci; break; } break; + case 29: + if (((inst >> 25) & 1) == 1 && ((inst >> 12) & 0b111) == 2) { + switch ((inst >> 26) & 0b111111) { + case 32: op = rv_op_vsm3me_vv; break; + case 33: op = rv_op_vsm4k_vi; break; + case 34: op = rv_op_vaeskf1_vi; break; + case 40: + switch ((inst >> 15) & 0b11111) { + case 0: op = rv_op_vaesdm_vv; break; + case 1: op = rv_op_vaesdf_vv; break; + case 2: op = rv_op_vaesem_vv; break; + case 3: op = rv_op_vaesef_vv; break; + case 16: op = rv_op_vsm4r_vv; break; + case 17: op = rv_op_vgmul_vv; break; + } + break; + case 41: + switch ((inst >> 15) & 0b11111) { + case 0: op = rv_op_vaesdm_vs; break; + case 1: op = rv_op_vaesdf_vs; break; + case 2: op = rv_op_vaesem_vs; break; + case 3: op = rv_op_vaesef_vs; break; + case 7: op = rv_op_vaesz_vs; break; + case 16: op = rv_op_vsm4r_vs; break; + } + break; + case 42: op = rv_op_vaeskf2_vi; break; + case 43: op = rv_op_vsm3c_vi; break; + case 44: op = rv_op_vghsh_vv; break; + case 45: op = rv_op_vsha2ms_vv; break; + case 46: op = rv_op_vsha2ch_vv; break; + case 47: op = rv_op_vsha2cl_vv; break; + } + } + break; case 30: switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) { From patchwork Wed Oct 25 15:13:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13436426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AD19C25B47 for ; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id w14-20020a63160e000000b005b8ebef9fa0sm2677807pgl.83.2023.10.25.08.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:15:02 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Palmer Dabbelt , Alistair Francis Subject: [PATCH 14/14] disas/riscv: Replace TABs with space Date: Wed, 25 Oct 2023 23:13:38 +0800 Message-Id: <20231025151341.725477-15-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025151341.725477-1-max.chou@sifive.com> References: <20231025151341.725477-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=max.chou@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replaces TABs with spaces, making sure to have a consistent coding style of 4 space indentations. Signed-off-by: Max Chou --- disas/riscv.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/disas/riscv.c b/disas/riscv.c index 5bfa9390c45..128478a3a09 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -3136,12 +3136,12 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) } break; case 89: - switch (((inst >> 12) & 0b111)) { + switch (((inst >> 12) & 0b111)) { case 0: op = rv_op_fmvp_d_x; break; } break; case 91: - switch (((inst >> 12) & 0b111)) { + switch (((inst >> 12) & 0b111)) { case 0: op = rv_op_fmvp_q_x; break; } break; @@ -4578,7 +4578,7 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) break; case rv_codec_zcmt_jt: dec->imm = operand_tbl_index(inst); - break; + break; case rv_codec_fli: dec->rd = operand_rd(inst); dec->imm = operand_rs1(inst);