From patchwork Thu Oct 26 12:44:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437556 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0B7EC25B6B for ; Thu, 26 Oct 2023 12:47:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ygnHttPef4dqKjphJLdmO4Ap4i5Yf8IoOikw+jRA8EY=; b=gc/bo6pb8A9lZn S0Y2S86AQUM+08mchMEED/qKMZRLF7IUDs2/TyCkjpeSmmYrM4i4nI0cVW/EJw21gXjlmV8XpknvV nPNUQXLaQIpbObcvAaiK4GjjKIEzKopZ2ARKUa39VTJrDX57/lfN4bsqEkVwRIZI8hUPyDKME6pLL AsgbutN0yjgaQNKE7NwUKNiMR87qOIXEKW/vWIBHGMZIb+UgMHn8qmgmQX2Tvg1A+1qsxM0eGBkBV /N69jQTSxQSPg8I/J0KcZiEhNFzHO3ZTDN7mdzF+YHf7qbYdYM9p6B3YxOyLm2E1UkUMuZx9G5z/S KpqZm4beNX1BT4XkjhAQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvzl8-00ESl2-15; Thu, 26 Oct 2023 12:46:46 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzl0-00ESeR-0q for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:46:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 873C0CE3F0D; Thu, 26 Oct 2023 12:46:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 03DB8C433CB; Thu, 26 Oct 2023 12:46:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324395; bh=/SsV17JjmcJWXgvKkTqZRVD5akWZYypymBxevZPCiMY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=umjzpE0Q326WUy10ZFOmuReuhYw1cyUt4vgtO8lcUDs5aYU2q/rSCwg9DZAs10iB8 oHTeWWJnjgfaRhIsG9e2hOXgwtAMti8BNyCGQEj+oJ52+jwDdZBjFz+jqALq2ysH5Y gz7R8uFemtjyyBP/67rI21xNAgmYJrkN9tb7F78wrwFYKliZRX+t1TZR3z6u8M5zkM jCP3EQXelzKKzg2W/J3lHdOCjsdN+7UPY5/axMx2nl8duuHF+l2a7BMjSiihKtdpaF LyM5j6P6fyHKDZ1QFe+c3MoiBvXsRCrQlWny5r8L1qBeiDI7JNtFvm6N5XW8IUCuLD RVZNgm9f61xAQ== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:15 +0100 Subject: [PATCH 01/21] arm64/sysreg: Add definition for ID_AA64PFR2_EL1 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-1-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=956; i=broonie@kernel.org; h=from:subject:message-id; bh=/SsV17JjmcJWXgvKkTqZRVD5akWZYypymBxevZPCiMY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+Uv5s65NqMFKzwXuON3ueWSkSrMRqWmMnlFvHq 9F/xllWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflAAKCRAk1otyXVSH0NGDB/ 0fcICQjJwsx5FdjSkdG3BPMzhGWFeXQUR7esZohLu9g6mefV8buYsAc1nCdzY59PRYQ7AgT47jCZjw 55uFH0adbIlwDlFnDr01UXxFtslG16AMMLkfNaVCvpq+1MeE9ck2RroMKWVxWjT2Jkla6+aB6nHfpa gooqN0BEwpJ7QN7xBqhHOg4ibBWuGKImIhSLtDlCekkXRBAMkPq59BZAZ5h6yeQJMUwS2OWY9Eh/DL 5RsIOfiIg138jFiyLuNAmBVQ39/KX4ZV3GeMhxX0TZ099ejdrzFQ+LsDwVz+kEcQGYxVvuMlZjNwNH 3chUCCqwTK85ztKn/byYBMQYuU+Y4n X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054638_477960_DC07F7E3 X-CRM114-Status: UNSURE ( 7.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines a new system register ID_AA64PFR2_EL1 which enumerates FPMR and some new MTE features. Add a definition of this register. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 76ce150e7347..0ea93d166f48 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1002,6 +1002,27 @@ UnsignedEnum 3:0 BT EndEnum EndSysreg +Sysreg ID_AA64PFR2_EL1 3 0 0 4 2 +Res0 63:36 +UnsignedEnum 35:32 FPMR + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 31:12 +UnsignedEnum 11:8 MTEFAR + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 7:4 MTESTOREONLY + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 3:0 MTEPERM + 0b0000 NI + 0b0001 IMP +EndEnum +EndSysreg + Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 Res0 63:60 UnsignedEnum 59:56 F64MM From patchwork Thu Oct 26 12:44:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB927C25B67 for ; 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Thu, 26 Oct 2023 12:46:46 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzl2-00ESfh-1d for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:46:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1F5FE63436; Thu, 26 Oct 2023 12:46:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30B8CC433C8; Thu, 26 Oct 2023 12:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324398; bh=/C6uYsNf+k2NYJmRn5HC5d00qPbiUk6gpp6lP4Wus70=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EUJ9b4fHPp3NmHoLuIb88u3yL123ulXXTz8mujws9Nvs7FXm0ek73iIlGFF8lh4Nr e/whfA+AvR4Fp2ezXzfdeJLxQBgqoF+WSGQAP2IaLud+oswU7x4Leg0IL+wVCg/Shc 8I8c6bRC7FqrdU17LGJeTP1gt8NJFBMAGjvd3Q/bnuLCVo0RX0O1UGUIplQFxgUBK2 j6qSr4pOp9he+ibX1SENsyure3AZqr8I262GKRrDehY1CUv7gFTYFjjT+owxn7lENW uBo5NLBHAPUNj1VpBVdYB4igB67u355AjMXRoJr313OhSkRkaiPNVEcBr+xEJTtuBG /7UraLii886ow== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:16 +0100 Subject: [PATCH 02/21] arm64/sysreg: Update ID_AA64ISAR2_EL1 defintion for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-2-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1340; i=broonie@kernel.org; h=from:subject:message-id; bh=/C6uYsNf+k2NYJmRn5HC5d00qPbiUk6gpp6lP4Wus70=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+V17IIomDsq6mCMkzj7i309UYGqYyGh1zX2T6k nCRjH1aJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflQAKCRAk1otyXVSH0AOkB/ 43X75EYFjRwcuVXX39Xv05Sa90HaJ801YZGPlMrODCNF59tx26HSQ8zz/8ttHJRSN++ro0N3DoRhwi SN4BgwpET5XQYtZ+GKA0nkJXntCc7MEWki9fnkR7j0zCnlsEMukScx9/spVWVc4Sk/pRbVh9TdjMkk IX6mg9pHgvRuRsicEkGGTLDjblxL8INuv2ERRxmaviQeTrW8CzFfCZyYAyEWehBMS27xSm7gZYA46k GScd4LXFgaxzDFeWNVmS3+UntLG5MlokoB9/7y9IokOtjqRkjxRBiehitDE9CIZvRHtSnIhY40d+Sz /9L3Yt1nsp3ZYE+yWsgFdBng60vJwU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054640_586314_42DD36AC X-CRM114-Status: UNSURE ( 8.79 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines some new fields in previously RES0 space in ID_AA64ISAR2_EL1, together with one new enum value. Update the system register definition to reflect this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0ea93d166f48..fcca3a3714b0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1359,7 +1359,14 @@ EndEnum EndSysreg Sysreg ID_AA64ISAR2_EL1 3 0 0 6 2 -Res0 63:56 +UnsignedEnum 63:60 ATS1A + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 59:56 LUT + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI 0b0001 IMP @@ -1368,7 +1375,19 @@ UnsignedEnum 51:48 RPRFM 0b0000 NI 0b0001 IMP EndEnum -Res0 47:32 +Res0 47:44 +UnsignedEnum 43:40 PRFMSLC + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 39:36 SYSINSTR_128 + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 35:32 SYSREG_128 + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 31:28 CLRBHB 0b0000 NI 0b0001 IMP @@ -1392,6 +1411,7 @@ UnsignedEnum 15:12 APA3 0b0011 PAuth2 0b0100 FPAC 0b0101 FPACCOMBINE + 0b0110 PAUTH_LR EndEnum UnsignedEnum 11:8 GPA3 0b0000 NI From patchwork Thu Oct 26 12:44:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8548C25B67 for ; Thu, 26 Oct 2023 12:47:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PDjAJN2xYN0XZ1e8OT9PFHsvApF6XLa7HWXmK5Uhbfg=; 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Thu, 26 Oct 2023 12:46:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324402; bh=ZUqE+FoZ8I0edvZBSg8kbSquWpI5yMoNq50cI0RqCRA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tprJLkklYLd9LU4YRx3zEkYskq13dHHC2DhKzA6CzKjhJDGvRAm+LSGLuX62rkiUC mgh8v98gEYO6Q7HDvqodefGJdSJ/nntVf17lmXoZ033Kf3oIirNGfwYfonuA6eWiUr HNHPJ6O5NL9Q4+9lMul7E5tGQJ/IK4DD9TFJId6VERhWMUCiaQU0aB8ysjWNxxbvDa vNqQSTkVnrdUHLpk5OM0O+cnDANfcL68Y9mcCywePOP2WqeJGG7Hh6FHQqXBoHIRSr fl9bLROlEWhodHkPpWQ60wzkeldHScO4KY6tANyCuIOCs4UPawfMrcU/wwvwYi2Qxg GiDB2wx+dtocw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:17 +0100 Subject: [PATCH 03/21] arm64/sysreg: Add definition for ID_AA64ISAR3_EL1 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-3-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=883; i=broonie@kernel.org; h=from:subject:message-id; bh=ZUqE+FoZ8I0edvZBSg8kbSquWpI5yMoNq50cI0RqCRA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+WUHz+pzcsY08wNR6Kjeb25JKyJyDhzGlPim9E eK8IbOeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflgAKCRAk1otyXVSH0PU0B/ 9GMmBOtiaoARHjbPxYpbTU3Wt0euLtLqlrzKZURVhrsCeiyY1LoZvh0vXbrNdiQ+FEqycACOlXkXsY t0ki7j8v8aD0oQiiB3GBnJjEu9UXCb0sNlD88c7THyIbZ4Il9XLnKOBIt76Q000umfoX3M18aI7k+W Am8FRhvhNbAHQKk59MSLd7zZPCLv6YcrvZ6g7V6LJrDhsYL6AxiL8toCsDsB5fE9izdhNc1jB5KqIs CRXserJ3jo/Sl9vHtq0j2EsRpiXDiGSzEj3+TydR6tNj/Ntv/tSP3sLLHWLMkAjY2iJXTlUxq9EtP+ OO+JMUz0p63D54Lespwq6HZEcBeen+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054643_244459_84805CC0 X-CRM114-Status: UNSURE ( 8.33 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 adds a new system register ID_AA64ISAR3_EL1 enumerating new floating point and TLB invalidation features. Add a defintion for it. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index fcca3a3714b0..0515006a7292 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1427,6 +1427,23 @@ UnsignedEnum 3:0 WFxT EndEnum EndSysreg +Sysreg ID_AA64ISAR3_EL1 3 0 0 6 3 +Res0 63:12 +UnsignedEnum 11:8 TLBIW + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 7:4 FAMINMAX + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 3:0 CPA + 0b0000 NI + 0b0001 IMP + 0b0010 CPA2 +EndEnum +EndSysreg + Sysreg ID_AA64MMFR0_EL1 3 0 0 7 0 UnsignedEnum 63:60 ECV 0b0000 NI From patchwork Thu Oct 26 12:44:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBB8FC25B48 for ; Thu, 26 Oct 2023 12:47:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wZ8c1wAiwORL72bqQR0T2mrM1lVvJkMtQgxxDjzgwcU=; b=oDHcepR6gkqCjR TtjTAC0AFvJjq2XD3hSmdiAGCrb7EiD4ysodU477/eYXwUhoe8kPQV0csec96Ys0phSIaoyuRzZg6 4J0JSooJHKu6sk30KOtWKQ5rYbgpHiXt+0ftsN2CAyD4GAWvf0U5nRXpyH8ww0Uz5w5TcEYFTbzeh 9Dnw8cMg0UX+4Id7VLf8IDs4WJ95HJpON5CSpGSf6oXxgxIhcHnP+Stq7gaOTso9NPUlBN5VncK+I +KXawPA9O8ay1PxCTEaTXKGvZYWyWyi9S9Jq7CR/pY++2txmYc/Sn8r2XDw8iTOnpp1HazCOGB8cj ZzteMUgSZEK79SbB7FWA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlW-00ET5q-2p; Thu, 26 Oct 2023 12:47:10 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzl9-00ESl6-0h for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:46:48 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id EC2AEB82F14; Thu, 26 Oct 2023 12:46:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91771C433C9; Thu, 26 Oct 2023 12:46:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324405; bh=l+HCexWWxMeo4+X882PpIsnRc1YU/TuuwGZRa34ZAVo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HxSkc5zcim4fIsz1of6Y5as+8CAZs7GFuQ5+xfycnsE/b/2Is+MZ0XHH/+pA2B+/W mee0IXbfkhsfej9CSwpQ7eYjTGIdqZkGhP6KqcvEIBkU78CmpAsrNhflVoTcqiR2Wj VPJrybUSoaqp56l6aaITq9xi0eQVFvCKURnJVtZlQS8/Gek11tUj7Vj0xMN5CFJlsN 1llfJiMql9H2UUo/ZsF+4bdzNI0LvtJ77O/O6yTvAxuS0TJhqdKmmy+MOvcYae1X2O KX+F+VLJNuPluO3KRh4m5nzAtWP+tk6lWk+QkHsZ73z7moI0bAYDJxwF2+VI9MOH1Y CoIxE9K75HHEw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:18 +0100 Subject: [PATCH 04/21] arm64/sysreg: Add definition for ID_AA64FPFR0_EL1 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-4-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1020; i=broonie@kernel.org; h=from:subject:message-id; bh=l+HCexWWxMeo4+X882PpIsnRc1YU/TuuwGZRa34ZAVo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+XUuTBqlPY3g709lZjkwYwp+1ZdUE3hY0gt7IQ GpOYfLuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpflwAKCRAk1otyXVSH0K7jB/ 9ICx2WqKsW1ClXsnohdgTF3SOkdLDKnjHNlSqc9Ur0gJ5NCfS6kccYZzLwgEjzoAR5DThfGIZSDJt+ OXOHBgGCBfzN5Ivlaf0WdFkUDQdu+vkrIY0RyNk+2DmE1tUalkkUjydPHS3C6C+ytF3AdgmQNTOGII DS2WsRlR+ll3gC98gzI3fJQXrmiGv3Fni6LVhsUAx+GLfnQIMRIwpFPHauUEAmgTOjR2e2VpiDLhsQ SsIbOH1zVwcZ3vTidZnJxL98YtD9Xqu4iIeF+xPer5Qp7ak4V1fcJMplcR5NKQMOxrYpBYZOBoy/5K Hlgm1bZgqd3CGwsYvIR/0qZHTUCWGz X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054647_402641_95A7EF2A X-CRM114-Status: UNSURE ( 7.76 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines a new feature register ID_AA64FPFR0_EL1 which enumerates a number of FP8 related features. Add a definition for it. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0515006a7292..057cd85d8c2c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1127,6 +1127,35 @@ EndEnum Res0 31:0 EndSysreg +Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 +Res0 63:32 +UnsignedEnum 31 F8CVT + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 30 F8FMA + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 29 F8DP4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 28 F8DP2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 27:2 +UnsignedEnum 1 F8E4M3 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 0 F8E5M2 + 0b0 NI + 0b1 IMP +EndEnum +EndSysreg + Sysreg ID_AA64DFR0_EL1 3 0 0 5 0 Enum 63:60 HPMN0 0b0000 UNPREDICTABLE From patchwork Thu Oct 26 12:44:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2B20C25B6E for ; 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Thu, 26 Oct 2023 12:47:11 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlB-00ESnm-12 for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:46:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id D227C60F9E; Thu, 26 Oct 2023 12:46:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0A68C433CD; Thu, 26 Oct 2023 12:46:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324408; bh=StlnPCfdiEmTpFedQBxetyCeCnpVA1cVpZaBcOnDm18=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LO0/MNI6L6M+MuomX40QF1R89KAblQV6tWAxPl5U1HKGIyUe0hLGhFc5qOUlp83O5 OYFFyntpnJtlJ0GPdQpxvgQNew/REUuy4LR9YfJMM0iPCkjKJDBB2EbROsSq8abd5b FdAZSiNHdgJqYLzET3wzVFwEQQY4LsuD53Z1vD+DpG9UdBwNgvELnmINZilh6aBNiA vL87+SrFNoW0jOcpziXPscop9/9CHloGH1U1d3+9aDuasEG4REhxFxLiV3H1IlZAYS 014Hs8xx3WLlRYP5syWloVDW4cl+OnAya1RMRDY/tcAciLtI20yHp4DJOJ766lTaZb iixhjARLQc+PA== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:19 +0100 Subject: [PATCH 05/21] arm64/sysreg: Update ID_AA64SMFR0_EL1 definition for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-5-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 2023-09 release of DDI0601 defines a number of new feature enumeration fields in ID_AA64SMFR0_EL1. Add these fields. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 057cd85d8c2c..91dd564ee4d3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1075,7 +1075,11 @@ UnsignedEnum 63 FA64 0b0 NI 0b1 IMP EndEnum -Res0 62:60 +Res0 62:61 +UnsignedEnum 60 LUTv2 + 0b0 NI + 0b1 IMP +EndEnum UnsignedEnum 59:56 SMEver 0b0000 SME 0b0001 SME2 @@ -1103,7 +1107,14 @@ UnsignedEnum 42 F16F16 0b0 NI 0b1 IMP EndEnum -Res0 41:40 +UnsignedEnum 41 F8F16 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 40 F8F32 + 0b0 NI + 0b1 IMP +EndEnum UnsignedEnum 39:36 I8I32 0b0000 NI 0b1111 IMP @@ -1124,7 +1135,20 @@ UnsignedEnum 32 F32F32 0b0 NI 0b1 IMP EndEnum -Res0 31:0 +Res0 31 +UnsignedEnum 30 SF8FMA + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 29 SF8DP4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 28 SF8DP2 + 0b0 NI + 0b1 IMP +EndEnum +Res0 27:0 EndSysreg Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 From patchwork Thu Oct 26 12:44:20 2023 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324411; bh=oFpKguHAi/AFRsar5DM/a5DMfjfPrq4L3XQpoObPzvM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ri2qxKBQJNvGpLo9SqHrlKTLrhUlyEBtfOw6XZFetGY83LgK6khVhyFNkAlNaPGgM EuzgIJ6+Q5RyFCqeRjHY2hSlz3CnuWvAnQhX2OMPSA/ZhYTSVr6Fnlirmv4P6tKzWF uV61jkJaN9oE/cr74ZDZksfThi3iOFFDA1lWRkvSo3c3YE9RsPFW76U8qiKISn29+4 FwmVtH5mfvG2AaO/Ot4XHNpfymGAr62Sz0TluE4XF4z83AGUQ710L4FpikaHVt6Mzr sOIK0Cue47t3T8tG1ZFJTZC9Cq5EFPhzBXF1Y5Dlnkis6FY/Q4SgIxzkQW8KHbHcDF VH1TFGa1dkgVg== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:20 +0100 Subject: [PATCH 06/21] arm64/sysreg: Update SCTLR_EL1 for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-6-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=817; i=broonie@kernel.org; h=from:subject:message-id; bh=oFpKguHAi/AFRsar5DM/a5DMfjfPrq4L3XQpoObPzvM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+YSxS2zmLvWTnTnwZBvqOKxHpSW7yOQbtpETEr 08wWXiKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmAAKCRAk1otyXVSH0I7lB/ 4z2aZ2Oe6EpVndXZu3zbSqXy0VedKb+jf6LBimIDci4OA8eeoK2j8sPM7CL+pQ+4UAN50o2mLUJFoX yN9zE697Mv86xaeiE6hIxHV76tlbt/chlS6ZSXE5AQdzosMhqF7GOY5fG2CFjv97Pj30v4P0RPEFjy 7MvXYvW6E9zSxnFlD88mq3qETlhqQuf7ewxi/GCZvNJrfc9HjimY6fUSnQgIDg2SV0xuuzQeXJkmXq gh9YzM/ua14nORpoTlfAIJC5SXeH6XOwsgZu9ya9np79UZtppI12RMSsFpDTj1pkkwXiYAT8aN0M0e HCqzbIruuXhWNjZjGqlutm4x6WBgwU X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054652_693993_A1CB3868 X-CRM114-Status: UNSURE ( 8.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines some new fields in SCTLR_EL1 controlling new MTE and floating point features. Update our sysreg definition to reflect these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 91dd564ee4d3..97d0da472328 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1785,7 +1785,8 @@ Field 63 TIDCP Field 62 SPINTMASK Field 61 NMI Field 60 EnTP2 -Res0 59:58 +Field 59 TCSO +Field 58 TCSO0 Field 57 EPAN Field 56 EnALS Field 55 EnAS0 @@ -1814,7 +1815,7 @@ EndEnum Field 37 ITFSB Field 36 BT1 Field 35 BT0 -Res0 34 +Field 34 EnFPM Field 33 MSCEn Field 32 CMOW Field 31 EnIA From patchwork Thu Oct 26 12:44:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4267AC25B72 for ; Thu, 26 Oct 2023 12:47:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XYXc3Di0lxI+X3hniMRLn3WklIaVoInrZl4ICektDNc=; b=UjvpdK7QIGrkI4 dBADE1a81AxyA2w0BN4PSZUFMnyyQqnpsd/XOWhkKKWoaKKHfbqvYa1d6zSup1sHhUk/ZwFnzkGa2 hReYU1D2flKYKgNPFZqR3Idte3jQzONr/KnWyr3PidEJlypbj0OLjQ8l1rQhXDlweXeAXKM49U7pe 1J3Yi6fVXDweVvrOYaNOMucaeuWOs/G4CG5h6VjVoFKZ+NMqlb614x/mdpUzpXHoircqeAOXgzopf o68YWvDnebIH4qge3B1IkUhqmIFDurtHt7qi9XLqqVtYEIp/bZkBnrSwTRrdkSM8SoUA+QLL25Mnz xd9sHBVVKx0fJSYXCKuQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlZ-00ET8V-2S; Thu, 26 Oct 2023 12:47:13 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlL-00EStw-2f for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:47:02 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id B9FA4CE3F11; Thu, 26 Oct 2023 12:46:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 30C4CC433CC; Thu, 26 Oct 2023 12:46:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324414; bh=bZPOq75obKgR16PHbo86C4WPqSIy0lDpy+567+6KdtA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=VZ9j04voioUdaBycGNSzqTlU6jt2ZX21l8S3Cv5onpRT0ybfRy46GbUaOKuLlwxFC IxmAuzT49WZKLWAzr3WNIVNUrud/7pfA7wOgj1q+0FUoEkYtG4Fk1g1X0+g1MFFCir XXPgX+1WfvEeeg1XZCrcVRWGdezWksoAkuzCfgUeoDOPVNeqREtZsr30IsYmte7fJm P4WUR0fIlKwpJWr59VV8a1xQLcQOv7XvaBqKHDwIsLxPCfGAIbwo9xcBbi8wb1jSDB WENfgGZTmXdWLrSXI+fhx2Um0ruFpZ4KT5nu4vtHVPpO2zYck/oYZnPHQDGISfe2/n q7GAVYEOXMI+w== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:21 +0100 Subject: [PATCH 07/21] arm64/sysreg: Update HCRX_EL2 definition for DDI0601 2023-09 MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-7-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=666; i=broonie@kernel.org; h=from:subject:message-id; bh=bZPOq75obKgR16PHbo86C4WPqSIy0lDpy+567+6KdtA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+ZKpBn2quw+JMOA0wd9IcOAen3LFzhH3lZPbjF 67bDa5qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmQAKCRAk1otyXVSH0Be7B/ 0ZNb48Xv/lVy/VBrcStmABmWW9LC6FiiPirjjfQ8/Fp1JOrtI/9R0v4o61LHJKocZRJLXF6x/sPNh1 SAqdEFkEiArmAeBbjOMS0z1O/Jye1GneG3YH11Bgs2ulbyTCPQ2JBHeqTqBvWOXFkMqktKaYrS2/SB Zrg7vO3Cy+rq6ZvobAsxgkTDMKxF8ZTlWN1ZR2mnBlb77UVFHo/8tAd8k4XBg25/oHexuRSKDLMhWK q/snGPjl4jj/iZYxP9P67e99vQ3bjeb/iPpYgpWcsZfb4/BVp1+ooMP2Npgu8ugcwNUnVR7yWY0SI8 Zwze0pXLG07ZkHk0J8eLE14xO2j741 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054700_046309_EED6D6AA X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines new fields in HCRX_EL2 controlling access to new system registers, update our definition of HCRX_EL2 to reflect this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 97d0da472328..e603a6153527 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2406,7 +2406,9 @@ Fields ZCR_ELx EndSysreg Sysreg HCRX_EL2 3 4 1 2 2 -Res0 63:23 +Res0 63:25 +Field 24 PACMEn +Field 23 EnFPM Field 22 GCSEn Field 21 EnIDCP128 Field 20 EnSDERR From patchwork Thu Oct 26 12:44:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 735A7C25B67 for ; Thu, 26 Oct 2023 12:47:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Tkma+mhr9S+mwQLw4Qq09iUaCLGon7FET62seIAWqJM=; b=ANCds+LDSK3pQo yIfJJrbJp3nsl/5R9oBbvfrHR9avYR6kjVP7nrq8xTjD1sPwJsbuCttBi30iT8cV92Omhw3tRZPOk 2jQefZANdymihwZwqjJ05qgrslyaBwSb9WNRjx6zruU2QS67AicGEEKbfE1Euw7nUigk1l5kjD4Pu ohtUQ5QvLcjXwLApinbMKL/C00JRYDImFB+3zGlLbnoA/FGMbnJCdAbCaCft+H9vF5GJYRy/waOHW 4D+0UCYZz/4ow3WJgilcNOldEXK7z3NArEVyIbyOR8Edec7G74V+CiOWjNmVM7W8q5LwvsrEB33cI JyHWRpD+nDP+Okvu9DmQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvzla-00ET9B-1n; Thu, 26 Oct 2023 12:47:14 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlM-00ESx1-1q for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:47:02 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id EBB6ECE3F14; Thu, 26 Oct 2023 12:46:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 633C8C433C8; Thu, 26 Oct 2023 12:46:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324418; bh=DS16tWYR3F7VpcQzgtoFB6E5W9YGpDiaNegIk+jm1dk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=LFswMmZqU3SzIsT4cDG0KmUSUwDlbWwrxhX5PJgZ76t/gzl/H9OuDg+KCVRqbz8S8 3dBxf3Sw8PH2n/lwpTtukIXGmtJ6Vq7SCY6qg0+90az5UpTO66C48FmMZ7VfgDOF9c Y/43EyWbAbTRctzt67JWPUOlwwG+fBb6rnkNIt2EhfiAqor4bXuEcddu7Zy3PSriXK HKAg4RLURZ34VaKoz2hcmB+yZrkbfbuUkv/CtxsxxCVD/UYNd5PSAVhAgA1kL4noB4 DcUWivDZHqfeyHKMYAcRQowXt25Icjak+WE2pisnvfRqsga2lXWgpiZKulnMpv/10U 0h04t+SWD1KrQ== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:22 +0100 Subject: [PATCH 08/21] arm64/sysreg: Add definition for FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-8-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=975; i=broonie@kernel.org; h=from:subject:message-id; bh=DS16tWYR3F7VpcQzgtoFB6E5W9YGpDiaNegIk+jm1dk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+aQjFzMSMDRU1ddpFtQzfW3+/loKKykxvkfyGR SfYVEO2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmgAKCRAk1otyXVSH0CL+B/ 9EHMME7iyfi+AdW55w4cbU/CSm5218COZm2ZFudBp8G1VQTEoMapJ4r2xkOgLU31sDfxfTf9zw5N3i bydjU5couA1UxqAF9L+JihcjIuIrqjVshBTVvz5vo+fe1ax8L0E8PasQ5RXcxlS8DUV3XcHf1mxJNq PbHDR4EZxkmkLQlgk2EntSgAPBnPSO6Aof9/VEDxU580hwGYrIFuIHcJDsIF96EUILFb85uyqZkwAb Egf87T3GGZ0LXpNyKGlufyVaL+nc6KP1ur80vptObIn3ctJh7bW6luxf6BPhhETNCCL/Egaur41yCg LRaPlzmBREdX+kwW/nUB6RrYvREUO/ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054700_787262_475C210C X-CRM114-Status: UNSURE ( 7.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DDI0601 2023-09 defines a new sysrem register FPMR (Floating Point Mode Register) which configures the new FP8 features. Add a definition of this register. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e603a6153527..3e4cb8a141a3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2132,6 +2132,29 @@ Field 1 ZA Field 0 SM EndSysreg +Sysreg FPMR 3 3 4 4 2 +Res0 63:38 +Field 37:32 LSCALE2 +Field 31:24 NSCALE +Res0 23 +Field 22:16 LSCALE +Field 15 OSC +Field 14 OSM +Res0 13:9 +UnsignedEnum 8:6 F8D + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 5:3 F8S2 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +UnsignedEnum 2:0 F8S1 + 0b000 E5M2 + 0b001 E4M3 +EndEnum +EndSysreg + SysregFields HFGxTR_EL2 Field 63 nAMAIR2_EL1 Field 62 nMAIR2_EL1 From patchwork Thu Oct 26 12:44:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437579 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00EF0C25B48 for ; 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a=openpgp-sha256; l=7897; i=broonie@kernel.org; h=from:subject:message-id; bh=A70TzKLxYRaHLeYspVh0azJqD+i/OcfkNzjW58SbjyM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+bOBPImzncrwOiJOMmRrPjsUx4R3OuZK4fkWNw RZPFvHuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfmwAKCRAk1otyXVSH0IBNB/ 9RsKTxUkLn4gA8r+7NVYEZwuH8kSlA+ENtpVXHHcWz/tY7tu/CzGM06prol7B0wBIK63tT44AczUde hWw6+HAmuCgbv1gApzeASsb9rEyHAGbwhFiNYkR5wAffLwDnUcPbzOJr8nZ2PYd/Ntjhe1gf6re/DP sagT2nV8rk8ubphl0jUUcu+ZecO+eVgS36kgIGTr8rYS4v8tE9szfqjiBHW2tcVVIGpdYxZS+TkJFl pgBRM3PjRLSYpwPs6ae1advdq6X49I6dFPqHfGLnZO3s+uhif9djahiR2U421RP+To0GiqPXjXbbjA 2GIji7GGMBJ4606tuDhLmYEVkb4ueg X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054703_259149_C817FC44 X-CRM114-Status: GOOD ( 11.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 2023 architecture extensions have defined several new ID registers, hook them up to the cpufeature code so we can add feature checks and hwcaps based on their contents. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpu.h | 3 +++ arch/arm64/kernel/cpufeature.c | 28 ++++++++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 3 +++ 3 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index e749838b9c5d..60db584ded55 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -53,14 +53,17 @@ struct cpuinfo_arm64 { u64 reg_id_aa64isar0; u64 reg_id_aa64isar1; u64 reg_id_aa64isar2; + u64 reg_id_aa64isar3; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; u64 reg_id_aa64mmfr2; u64 reg_id_aa64mmfr3; u64 reg_id_aa64pfr0; u64 reg_id_aa64pfr1; + u64 reg_id_aa64pfr2; u64 reg_id_aa64zfr0; u64 reg_id_aa64smfr0; + u64 reg_id_aa64fpfr0; struct cpuinfo_32bit aarch32; diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e638..c1658d893e0e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -234,6 +234,10 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), @@ -267,6 +271,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), @@ -317,6 +325,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), @@ -712,10 +724,12 @@ static const struct __ftr_reg_entry { &id_aa64pfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, &id_aa64pfr1_override), + ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, &id_aa64zfr0_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, &id_aa64smfr0_override), + ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), /* Op1 = 0, CRn = 0, CRm = 5 */ ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), @@ -727,6 +741,7 @@ static const struct __ftr_reg_entry { &id_aa64isar1_override), ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, &id_aa64isar2_override), + ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -1026,14 +1041,17 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); + init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); + init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); + init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) init_32bit_cpu_features(&info->aarch32); @@ -1263,6 +1281,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64isar1, boot->reg_id_aa64isar1); taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, info->reg_id_aa64isar2, boot->reg_id_aa64isar2); + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, + info->reg_id_aa64isar3, boot->reg_id_aa64isar3); /* * Differing PARange support is fine as long as all peripherals and @@ -1282,6 +1302,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); + taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, + info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); @@ -1289,6 +1311,9 @@ void update_cpu_features(int cpu, taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); + taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, + info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); + if (IS_ENABLED(CONFIG_ARM64_SVE) && id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { info->reg_zcr = read_zcr_features(); @@ -1399,8 +1424,10 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64PFR0_EL1); read_sysreg_case(SYS_ID_AA64PFR1_EL1); + read_sysreg_case(SYS_ID_AA64PFR2_EL1); read_sysreg_case(SYS_ID_AA64ZFR0_EL1); read_sysreg_case(SYS_ID_AA64SMFR0_EL1); + read_sysreg_case(SYS_ID_AA64FPFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR0_EL1); read_sysreg_case(SYS_ID_AA64DFR1_EL1); read_sysreg_case(SYS_ID_AA64MMFR0_EL1); @@ -1410,6 +1437,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64ISAR0_EL1); read_sysreg_case(SYS_ID_AA64ISAR1_EL1); read_sysreg_case(SYS_ID_AA64ISAR2_EL1); + read_sysreg_case(SYS_ID_AA64ISAR3_EL1); read_sysreg_case(SYS_CNTFRQ_EL0); read_sysreg_case(SYS_CTR_EL0); diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 98fda8500535..e153c6d2b3fd 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -445,14 +445,17 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); + info->reg_id_aa64isar3 = read_cpuid(ID_AA64ISAR3_EL1); info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1); info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); + info->reg_id_aa64pfr2 = read_cpuid(ID_AA64PFR2_EL1); info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); info->reg_id_aa64smfr0 = read_cpuid(ID_AA64SMFR0_EL1); + info->reg_id_aa64fpfr0 = read_cpuid(ID_AA64FPFR0_EL1); if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) info->reg_gmid = read_cpuid(GMID_EL1); From patchwork Thu Oct 26 12:44:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7B6EBC25B48 for ; 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Thu, 26 Oct 2023 12:48:02 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlV-00ET3B-0a for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:47:11 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 6BD0FCE3F0D; Thu, 26 Oct 2023 12:47:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B61B9C4339A; Thu, 26 Oct 2023 12:47:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324426; bh=Es1HQrf2Y34+Fy2pSDeaIOdQfdboYR0FuIcMBXlX4+E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rg50LsreK3vPIQnUFmO4QXkUaZiJ5uu+B1PwlgA+dWT2+hvnlSu8CfejYBS0jIOqN jm6KPhs9etVVGyPwD3sEzY3TZwQh4hptv7k4MGp1X3G2IAOJCp8HeuBqF06vbriFgk qkvDIr/xldrQYb3bFlPSKifIR7Ir8baQSuxKCxS5NzHbK8kdC1UL56z2OD12o++szv 49aiBP6I8e31ZVskSWCtYq99rxIkhvDT+DXwDeGPZZHsSsOzONPW24DPqcCjsUSwCJ NIVKhB47bS7xGcEF7iJPEc5Gd6gWtvf6uboipUivt8bN0CryYGLbDCMPUqCXLu3DRZ jT1jdbWsALl0A== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:24 +0100 Subject: [PATCH 10/21] arm64/fpsimd: Enable host kernel access to FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-10-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1028; i=broonie@kernel.org; h=from:subject:message-id; bh=Es1HQrf2Y34+Fy2pSDeaIOdQfdboYR0FuIcMBXlX4+E=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+cDio3fVDOG6FkTnDOEe/llr5xX9J3YDZxYQ5e 4EBVfGqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfnAAKCRAk1otyXVSH0KuWB/ 4v50sXhUz0JQ6Df8E+uf8uNMaUfxkYmtpSyW2zLhk5PHHVGCQsyVHKygDY+oINIJP1Am//8A0dhZ5o 1RCYO7dDqCw+olrIQO8LKLKOFNn+tL1rkaIAJVSWu5+qhUkV3m0Tfaux/6l93zI3ginnkp8ohyaucZ wQt5hoE35RQPa/3xJvassbTstV9c02LKJ/mLw2J0zTBtHzJFf0WttobhzE7Ej+i2tqIT/SLAzVshlq jQrdtUDqraR9V4BddiTiGc77Wb4Dxav58X25YbyXOvf20gm0ZAIjOrz8E9cLDXp4MVUvLZTDt+7FeH lWSYXaEk3FeQwEanSBHA3FPQScEbHx X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054709_416041_15E6C07B X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_FPMR provides a new generally accessible architectural register FPMR. This is only accessible to EL0 and EL1 when HCRX_EL2.EnFPM is set to 1, do this when the host is running. The guest part will be done along with context switching the new register and exposing it via guest management. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 1095c6647e96..ef033c6c745c 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -103,7 +103,7 @@ #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) #define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) -#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En) +#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) /* TCR_EL2 Registers bits */ #define TCR_EL2_RES1 ((1U << 31) | (1 << 23)) From patchwork Thu Oct 26 12:44:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B4C3C25B6B for ; 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Thu, 26 Oct 2023 12:48:03 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzlX-00ET5i-08 for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:47:13 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6E6166342B; Thu, 26 Oct 2023 12:47:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 10565C433CB; Thu, 26 Oct 2023 12:47:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324429; bh=P/MK23RoQa3xV9BTA1XSgjVaNHyyLLWBg+19ufBz12Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=O5TiAGsUsHGwNs8g1Ry4TWQRuoKVLW4jkkNl/JjjgKgClIbHm0BSbNFdl3USgrWxF t9dVrLhyGNFCJBXZHiwfy2aqwgyv1l7P2Ib3lK5Lt6HH5+dCbl9nowU9J1jFADd1/T zQa2v1ijroHw2GKzRyH4R6EwFEEbZY8BeR0MGSzUw1pevWtW6rJ4zUiydyAfALwGNY p+sG46Dw8GJPDIhgqPLaLTY/L/DozD4vA843GwUTz2hQkGq/2+skCmVLwXrBV25UML N/sE+fLgTB9kF11RPxXSqGYCiSUJH8WT4DKCzJU3ZTGaOcikuK+od1Pn/MsjhOYy1B /UZ+Yz6mOqd+A== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:25 +0100 Subject: [PATCH 11/21] arm64/fpsimd: Support FEAT_FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-11-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=6769; i=broonie@kernel.org; h=from:subject:message-id; bh=P/MK23RoQa3xV9BTA1XSgjVaNHyyLLWBg+19ufBz12Q=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+cvI35TLTZu/lVQIbg6QyuZqTAbAVwqCaLpoZW kyxfdTKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfnAAKCRAk1otyXVSH0BpPB/ 9rUy788ZDLctH9y03YOLxEstNPheVNgfcVeR/TDoJ72b2DPj1syWiFBF/E2yjVBvwY6LFU0ox9Jmic 4YUAhf2cHDVKNUNf4JTGcLxSVC12tnMx+gEEESJImiTx0jCxhCqwFMoV2iX0EX7M1Ur8sN/BeSGoNk JOiUej3ERdv7FqJASCfRL67SD3RWTe4QhYpETl2IoZWJ3WVZv08nzchtChPS4cp2NkV7EJwMuRlS3a pnxNhtTxTxc126belPuKrOCbEHYBiHXSbvzkJsk80hn/YR1AdDkfRCsjJ7oS+Zq1ThHZqOQ1IBuUS6 EMM6qeZMBetiwo3/cRfxwdMCpAWEEj X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054711_233390_AAF989A2 X-CRM114-Status: GOOD ( 19.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_FPMR defines a new EL0 accessible register FPMR use to configure the FP8 related features added to the architecture at the same time. Detect support for this register and context switch it for EL0 when present. Due to the sharing of responsibility for saving floating point state between the host kernel and KVM FP8 support is not yet implemented in KVM and a stub similar to that used for SVCR is provided for FPMR in order to avoid bisection issues. To make it easier to share host state with the hypervisor we store FPMR immediately after the base floating point state, existing usage means that it is not practical to extend that directly. Signed-off-by: Mark Brown --- arch/arm64/include/asm/cpufeature.h | 5 +++++ arch/arm64/include/asm/fpsimd.h | 2 ++ arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/processor.h | 2 ++ arch/arm64/kernel/cpufeature.c | 9 +++++++++ arch/arm64/kernel/fpsimd.c | 13 +++++++++++++ arch/arm64/kvm/fpsimd.c | 1 + arch/arm64/tools/cpucaps | 1 + 8 files changed, 34 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 5bba39376055..9b93ba4a5a3d 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -779,6 +779,11 @@ static __always_inline bool system_supports_tpidr2(void) return system_supports_sme(); } +static __always_inline bool system_supports_fpmr(void) +{ + return cpus_have_const_cap(ARM64_HAS_FPMR); +} + static __always_inline bool system_supports_cnp(void) { return IS_ENABLED(CONFIG_ARM64_CNP) && diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 8df46f186c64..5f921ebb7ca4 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -63,6 +63,7 @@ struct cpu_fp_state { void *sve_state; void *sme_state; u64 *svcr; + u64 *fpmr; unsigned int sve_vl; unsigned int sme_vl; enum fp_type *fp_type; @@ -127,6 +128,7 @@ extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern void sme_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern void sme2_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern void fa64_kernel_enable(const struct arm64_cpu_capabilities *__unused); +extern void fpmr_kernel_enable(const struct arm64_cpu_capabilities *__unused); extern u64 read_zcr_features(void); extern u64 read_smcr_features(void); diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index af06ccb7ee34..2151c1cbc53d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -481,6 +481,7 @@ struct kvm_vcpu_arch { enum fp_type fp_type; unsigned int sve_max_vl; u64 svcr; + u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index e5bc54522e71..dd3a5b29f76e 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -158,6 +158,8 @@ struct thread_struct { struct user_fpsimd_state fpsimd_state; } uw; + u64 fpmr; /* Adjacent to fpsimd_state for KVM */ + enum fp_type fp_type; /* registers FPSIMD or SVE? */ unsigned int fpsimd_cpu; void *sve_state; /* SVE registers, if any */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index c1658d893e0e..8e8cd411d1a2 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -272,6 +272,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -2747,6 +2748,14 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) }, + { + .desc = "FPMR", + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .capability = ARM64_HAS_FPMR, + .matches = has_cpuid_feature, + .cpu_enable = fpmr_kernel_enable, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) + }, {}, }; diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 91e44ac7150f..88a541b14d39 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -385,6 +385,9 @@ static void task_fpsimd_load(void) WARN_ON(!system_supports_fpsimd()); WARN_ON(!have_cpu_fpsimd_context()); + if (system_supports_fpmr()) + write_sysreg_s(current->thread.fpmr, SYS_FPMR); + if (system_supports_sve() || system_supports_sme()) { switch (current->thread.fp_type) { case FP_STATE_FPSIMD: @@ -472,6 +475,9 @@ static void fpsimd_save(void) if (test_thread_flag(TIF_FOREIGN_FPSTATE)) return; + if (system_supports_fpmr()) + *(last->fpmr) = read_sysreg_s(SYS_FPMR); + /* * If a task is in a syscall the ABI allows us to only * preserve the state shared with FPSIMD so don't bother @@ -716,6 +722,12 @@ static void sve_to_fpsimd(struct task_struct *task) } } +void fpmr_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p) +{ + write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK, + SYS_SCTLR_EL1); +} + #ifdef CONFIG_ARM64_SVE /* * Call __sve_free() directly only if you know task can't be scheduled @@ -1729,6 +1741,7 @@ static void fpsimd_bind_task_to_cpu(void) last->sve_vl = task_get_sve_vl(current); last->sme_vl = task_get_sme_vl(current); last->svcr = ¤t->thread.svcr; + last->fpmr = ¤t->thread.fpmr; last->fp_type = ¤t->thread.fp_type; last->to_save = FP_STATE_CURRENT; current->thread.fpsimd_cpu = smp_processor_id(); diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 8c1d0d4853df..e3e611e30e91 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -153,6 +153,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &vcpu->arch.svcr; + fp_state.fpmr = &vcpu->arch.fpmr; fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index dea3dc89234b..11b0e3360a2a 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -26,6 +26,7 @@ HAS_ECV HAS_ECV_CNTPOFF HAS_EPAN HAS_EVT +HAS_FPMR HAS_FGT HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 From patchwork Thu Oct 26 12:44:26 2023 Content-Type: text/plain; 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Thu, 26 Oct 2023 12:47:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324433; bh=qb52W/FnN/1SulYmCofB+kYw3kMDdBBbntUr0aosnTs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZrNfCl1/bl7Dw8ATVLKX3hSzMdpCuDkyfGPm1s6Prn3GMokNNRfjlBD1o0LRHD0DI Gph6e0BlfyssVsxdu1ayodPMxz7TAtb53sS2rp+Vg6BOY8+zBRQlfW+/DWq0ocOdWw IWQTcjwXJXpVu8ZW32xlwKsJo5ITD/Iw1h45Nirj9L3PzQk2Fw8OQGgMqR/mhVrizL CiPR+sGSEwjc0DOoYxGSiHC4waIL7CLTTT3B347MzQG99zOA8rKI/Ry8yN6QcqyMOB PdEBqOnSZjPI4iK/kE5Zh9lfKFRBlVJimaD/cpBmHSJBJl3yQCVy45lupOb/aX05EG kxm8dVU4lxofg== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:26 +0100 Subject: [PATCH 12/21] arm64/signal: Add FPMR signal handling MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-12-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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The kernel validates the exact size of the FPSIMD registers so we can't readily add it to fpsimd_context without disruption. Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/sigcontext.h | 8 +++++ arch/arm64/kernel/signal.c | 59 ++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h index f23c1dc3f002..8a45b7a411e0 100644 --- a/arch/arm64/include/uapi/asm/sigcontext.h +++ b/arch/arm64/include/uapi/asm/sigcontext.h @@ -152,6 +152,14 @@ struct tpidr2_context { __u64 tpidr2; }; +/* FPMR context */ +#define FPMR_MAGIC 0x46504d52 + +struct fpmr_context { + struct _aarch64_ctx head; + __u64 fpmr; +}; + #define ZA_MAGIC 0x54366345 struct za_context { diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index 0e8beb3349ea..e8c808afcc8a 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -60,6 +60,7 @@ struct rt_sigframe_user_layout { unsigned long tpidr2_offset; unsigned long za_offset; unsigned long zt_offset; + unsigned long fpmr_offset; unsigned long extra_offset; unsigned long end_offset; }; @@ -182,6 +183,8 @@ struct user_ctxs { u32 za_size; struct zt_context __user *zt; u32 zt_size; + struct fpmr_context __user *fpmr; + u32 fpmr_size; }; static int preserve_fpsimd_context(struct fpsimd_context __user *ctx) @@ -227,6 +230,33 @@ static int restore_fpsimd_context(struct user_ctxs *user) return err ? -EFAULT : 0; } +static int preserve_fpmr_context(struct fpmr_context __user *ctx) +{ + int err = 0; + + current->thread.fpmr = read_sysreg_s(SYS_FPMR); + + __put_user_error(FPMR_MAGIC, &ctx->head.magic, err); + __put_user_error(sizeof(*ctx), &ctx->head.size, err); + __put_user_error(current->thread.fpmr, &ctx->fpmr, err); + + return err; +} + +static int restore_fpmr_context(struct user_ctxs *user) +{ + u64 fpmr; + int err = 0; + + if (user->fpmr_size != sizeof(*user->fpmr)) + return -EINVAL; + + __get_user_error(fpmr, &user->fpmr->fpmr, err); + if (!err) + write_sysreg_s(fpmr, SYS_FPMR); + + return err; +} #ifdef CONFIG_ARM64_SVE @@ -590,6 +620,7 @@ static int parse_user_sigframe(struct user_ctxs *user, user->tpidr2 = NULL; user->za = NULL; user->zt = NULL; + user->fpmr = NULL; if (!IS_ALIGNED((unsigned long)base, 16)) goto invalid; @@ -684,6 +715,17 @@ static int parse_user_sigframe(struct user_ctxs *user, user->zt_size = size; break; + case FPMR_MAGIC: + if (!system_supports_fpmr()) + goto invalid; + + if (user->fpmr) + goto invalid; + + user->fpmr = (struct fpmr_context __user *)head; + user->fpmr_size = size; + break; + case EXTRA_MAGIC: if (have_extra_context) goto invalid; @@ -806,6 +848,9 @@ static int restore_sigframe(struct pt_regs *regs, if (err == 0 && system_supports_tpidr2() && user.tpidr2) err = restore_tpidr2_context(&user); + if (err == 0 && system_supports_fpmr() && user.fpmr) + err = restore_fpmr_context(&user); + if (err == 0 && system_supports_sme() && user.za) err = restore_za_context(&user); @@ -928,6 +973,13 @@ static int setup_sigframe_layout(struct rt_sigframe_user_layout *user, } } + if (system_supports_fpmr()) { + err = sigframe_alloc(user, &user->fpmr_offset, + sizeof(struct fpmr_context)); + if (err) + return err; + } + return sigframe_alloc_end(user); } @@ -983,6 +1035,13 @@ static int setup_sigframe(struct rt_sigframe_user_layout *user, err |= preserve_tpidr2_context(tpidr2_ctx); } + /* FPMR if supported */ + if (system_supports_fpmr() && err == 0) { + struct fpmr_context __user *fpmr_ctx = + apply_user_offset(user, user->fpmr_offset); + err |= preserve_fpmr_context(fpmr_ctx); + } + /* ZA state if present */ if (system_supports_sme() && err == 0 && user->za_offset) { struct za_context __user *za_ctx = From patchwork Thu Oct 26 12:44:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 45AD4C25B67 for ; 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Thu, 26 Oct 2023 12:48:04 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvzld-00ETC9-0M for linux-arm-kernel@lists.infradead.org; Thu, 26 Oct 2023 12:47:20 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 85A8F63440; Thu, 26 Oct 2023 12:47:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D89FC43395; Thu, 26 Oct 2023 12:47:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324436; bh=dWbKym9V/87gXqrTEOw7Gdze+KmteiyxYpdHGQXYWrg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eLP82xOI+jsgEF6T9OjGdATQh0IsYAp1RZfl0g2ShRuTCJ304wEzfeOFAoEPJyXQv 7pVHzDt4dS7wamb+A9ptRGSAPS1QqRsoEfMWpuT0riYj/yyS7NNrE/69R5FSycqdXr 4eyKS9SvESRTC27UUYBBVAYLZ2BZNVQqYpQlVMlgBuIVxqKTXjPe8IHHiSirx1yktW japheYAkxvdb3N0zZIsUGqQrQ6rVAw2FVCgI/7+YP18/mup2OZwcQHDaNoGHh6EqCc joudoMKqaUb45t67pcqIdLZIOHOw90yk/Wf98+HkCKQl82Nhz0CJJJx/oVTGI+VTY8 1b1mCs4AZJ/cQ== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:27 +0100 Subject: [PATCH 13/21] arm64/ptrace: Expose FPMR via ptrace MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-13-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=2850; i=broonie@kernel.org; h=from:subject:message-id; bh=dWbKym9V/87gXqrTEOw7Gdze+KmteiyxYpdHGQXYWrg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+ekg/UMcni812l8Ig/UJoR0JEl6TkGXxfX0PmS bCIIHIaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfngAKCRAk1otyXVSH0AZ5B/ 0d/SQSBlLCWftYb2aRs9U0zGgeVFxx+EzKrW0G8CkaEXWZ9kueyv9nVGQ3l54FLgVkRzKrRHI+VYpH LINBRNt/MUZgyjU1AQbsa0aYU9BLUDf5DmCVC8RGiOMsow0dZaO1uEEbCV5+34ITf3aP9Mvlf7h2zW r4j9EcICg3fAuTqcO53k6wwiu/qtRoxpA3E1/odRccMAGDFrVTYUiom5igbJiItOHs+7DasI0tCdJX cnk+hjW4j/0QoaBYdgQp3GLqgx9Aj/1a/eS9inD8eFVKpZaTZmYPfeUQgfbY0dDXhpWy1X/h1EaAg0 DdkjbPR2AjdhvNbI1eFumhMUy/qWrR X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054717_263778_6BF490F6 X-CRM114-Status: GOOD ( 14.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a new regset to expose FPMR via ptrace. It is not added to the FPSIMD registers since that structure is exposed elsewhere without any allowance for extension we don't add there. Signed-off-by: Mark Brown --- arch/arm64/kernel/ptrace.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 2 files changed, 43 insertions(+) diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 20d7ef82de90..cfb8a4d213be 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -697,6 +697,39 @@ static int tls_set(struct task_struct *target, const struct user_regset *regset, return ret; } +static int fpmr_get(struct task_struct *target, const struct user_regset *regset, + struct membuf to) +{ + if (!system_supports_fpmr()) + return -EINVAL; + + if (target == current) + fpsimd_preserve_current_state(); + + return membuf_store(&to, target->thread.fpmr); +} + +static int fpmr_set(struct task_struct *target, const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + unsigned long fpmr; + + if (!system_supports_fpmr()) + return -EINVAL; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fpmr, 0, count); + if (ret) + return ret; + + target->thread.fpmr = fpmr; + + fpsimd_flush_task_state(target); + + return 0; +} + static int system_call_get(struct task_struct *target, const struct user_regset *regset, struct membuf to) @@ -1417,6 +1450,7 @@ enum aarch64_regset { REGSET_HW_BREAK, REGSET_HW_WATCH, #endif + REGSET_FPMR, REGSET_SYSTEM_CALL, #ifdef CONFIG_ARM64_SVE REGSET_SVE, @@ -1495,6 +1529,14 @@ static const struct user_regset aarch64_regsets[] = { .regset_get = system_call_get, .set = system_call_set, }, + [REGSET_FPMR] = { + .core_note_type = NT_ARM_FPMR, + .n = 1, + .size = sizeof(u64), + .align = sizeof(u64), + .regset_get = fpmr_get, + .set = fpmr_set, + }, #ifdef CONFIG_ARM64_SVE [REGSET_SVE] = { /* Scalable Vector Extension */ .core_note_type = NT_ARM_SVE, diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 9b731976ce2f..4c8b4641a306 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -440,6 +440,7 @@ typedef struct elf64_shdr { #define NT_ARM_SSVE 0x40b /* ARM Streaming SVE registers */ #define NT_ARM_ZA 0x40c /* ARM SME ZA registers */ #define NT_ARM_ZT 0x40d /* ARM SME ZT registers */ +#define NT_ARM_FPMR 0x40e /* ARM floating point mode register */ #define NT_ARC_V2 0x600 /* ARCv2 accumulator/extra registers */ #define NT_VMCOREDD 0x700 /* Vmcore Device Dump Note */ #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ From patchwork Thu Oct 26 12:44:28 2023 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324439; bh=DIIfc135uXljK74SaVIpbtbdhvdA87NEj6R4ylFiBfM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qxNrKZ3wkmk1fUZlvBZPIxXdwDUbHDG9C4rE+ZP4AF4KxxbmlNnW3nqBbZjU56gUP T/6BJ8WmEkx1hOHWn7JbF4VmNb2Y2lqJTf9hSqnkt8H3aBoIuqkLPucLEUkK2PrqsP YpLIG7aw92g9acLkWq7d/oIByzbc2v+Vf4TYafF04Cy9HXuuV9ok1p0bFNcC/Lz2er tsZQDWGaA7dZrYxb8PkiPKcg3oPX5Gj56DVuRrI2COQLZduHt2PxC6BOGm8eLCX9ux Dv5V9c3F7HgDb08pMSN/WkAQNjlBKMFBKliFlkHA/IQFl9YhEodRfaT+ZAGfaQvFrx re8lZhJe3eemw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:28 +0100 Subject: [PATCH 14/21] KVM: arm64: Add newly allocated ID registers to register descriptions MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-14-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0afd6136e275..99cdaa594b06 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2016,12 +2016,12 @@ static const struct sys_reg_desc sys_reg_descs[] = { .reset = read_sanitised_id_aa64pfr0_el1, .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, }, ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), + ID_SANITISED(ID_AA64PFR2_EL1), ID_UNALLOCATED(4,3), ID_SANITISED(ID_AA64ZFR0_EL1), ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), + ID_SANITISED(ID_AA64FPFR0_EL1), /* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), @@ -2042,7 +2042,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_SANITISED(ID_AA64ISAR0_EL1), ID_SANITISED(ID_AA64ISAR1_EL1), ID_SANITISED(ID_AA64ISAR2_EL1), - ID_UNALLOCATED(6,3), + ID_SANITISED(ID_AA64ISAR3_EL1), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), From patchwork Thu Oct 26 12:44:29 2023 Content-Type: text/plain; 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Thu, 26 Oct 2023 12:47:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324442; bh=/zcZQXH55IEw2G57GbBx/NCqs0MSdE6qvhCHAjYd0rQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ry+Mpe1V3rsDrUXZ71r8myb+U2s0CLSPgfTxe98suCR9Rx9+KCuekGAXZYWnootDc vKwLHang/k1B4NxAlBVXoZfc1WzS0rbzlGWMxZba7HcXyIznken2n2eakTGRhyOU66 trIxOqzmQXKgwNOv38n8f7Iw7iBhY2GFWAlDAnihF1VZRmoT26KUPqlOHEeezy5Plc VYur9X9zqeLeskQdtQZv/w4D9WgB5dvx2Wro42iMdXs8yvAhqtWsNcphKHLucnb4lj ADypDEHvcxpp5SW/ApWGHyPiKLmnghgG1PM1r61AET3PwmQkst2/UTqJXyfSPGpqag +gizJ/I9RHShA== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:29 +0100 Subject: [PATCH 15/21] KVM: arm64: Support FEAT_FPMR for guests MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-15-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=6361; i=broonie@kernel.org; h=from:subject:message-id; bh=/zcZQXH55IEw2G57GbBx/NCqs0MSdE6qvhCHAjYd0rQ=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+gYc6HbU08LvxZczTbgEDPccS28EHZB1p9z1xq F6RAz+2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfoAAKCRAk1otyXVSH0OjEB/ 95LgZW+8G2B1ksIATpSdo7h6pCG6ILnUjWt2+WgZVeAJiirxhv8pLI2zcuVI7+ECoKgRNYzbkVlV/q lskTpCLOkAfi1WNx3Vfb452zJn4J6tykFOe4HfNZdVfxQNO4HZXt/TkWZW6piiEBgQ2Xd7I+VZ5TGi JLSWpCKA6X0uSwqbJ76OdXrbn0xN80MEu6sdLzv+yjUeYUBu/cj3v/q2iB9kQBZsEOZ3QAyaSvlQdd HL/ZYV3j4PRZXtJLZlMyOtNbOmnh8blqD9BP6LzDVEKGRuFI4Nl5XXBrlA1CPrBZKHYl8ICg/Pf4iw jCJk87Jw908KAVGj3F3sTdhAhHJ5Rn X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054725_829148_F4669C4D X-CRM114-Status: GOOD ( 23.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_FPMR introduces a new system register FPMR which allows configuration of floating point behaviour, currently for FP8 specific features. Allow use of this in guests, disabling the trap while guests are running and saving and restoring the value along with the rest of the floating point state. Since FPMR is stored immediately after the main floating point state we share it with the hypervisor by adjusting the size of the shared region. Access to FPMR is covered by both a register specific trap HCRX_EL2.EnFPM and the overall floating point access trap so we just unconditionally enable the FPMR specific trap and rely on the floating point access trap to detect guest floating point usage. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_arm.h | 2 +- arch/arm64/include/asm/kvm_host.h | 4 +++- arch/arm64/kvm/fpsimd.c | 20 +++++++++++++++++--- arch/arm64/kvm/hyp/include/hyp/switch.h | 7 ++++++- arch/arm64/kvm/sys_regs.c | 11 +++++++++++ 5 files changed, 38 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index ef033c6c745c..2efc7107c9a1 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -102,7 +102,7 @@ #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) -#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) +#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) /* TCR_EL2 Registers bits */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 2151c1cbc53d..ddd31b41bec7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -355,6 +355,8 @@ enum vcpu_sysreg { CNTP_CVAL_EL0, CNTP_CTL_EL0, + FPMR, + /* Memory Tagging Extension registers */ RGSR_EL1, /* Random Allocation Tag Seed Register */ GCR_EL1, /* Tag Control Register */ @@ -481,7 +483,6 @@ struct kvm_vcpu_arch { enum fp_type fp_type; unsigned int sve_max_vl; u64 svcr; - u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; @@ -540,6 +541,7 @@ struct kvm_vcpu_arch { struct kvm_guest_debug_arch external_debug_state; struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ + u64 *host_fpmr; /* hyp VA */ struct task_struct *parent_task; struct { diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index e3e611e30e91..dee078625d0d 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -14,6 +14,16 @@ #include #include +static void *fpsimd_share_end(struct user_fpsimd_state *fpsimd) +{ + void *share_end = fpsimd + 1; + + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + share_end += sizeof(u64); + + return share_end; +} + void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) { struct task_struct *p = vcpu->arch.parent_task; @@ -23,7 +33,7 @@ void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) return; fpsimd = &p->thread.uw.fpsimd_state; - kvm_unshare_hyp(fpsimd, fpsimd + 1); + kvm_unshare_hyp(fpsimd, fpsimd_share_end(fpsimd)); put_task_struct(p); } @@ -45,11 +55,15 @@ int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu) kvm_vcpu_unshare_task_fp(vcpu); /* Make sure the host task fpsimd state is visible to hyp: */ - ret = kvm_share_hyp(fpsimd, fpsimd + 1); + ret = kvm_share_hyp(fpsimd, fpsimd_share_end(fpsimd)); if (ret) return ret; vcpu->arch.host_fpsimd_state = kern_hyp_va(fpsimd); + if (cpus_have_final_cap(ARM64_HAS_FPMR)) { + WARN_ON_ONCE(¤t->thread.fpmr + 1 != fpsimd_share_end(fpsimd)); + vcpu->arch.host_fpmr = kern_hyp_va(¤t->thread.fpmr); + } /* * We need to keep current's task_struct pinned until its data has been @@ -153,7 +167,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &vcpu->arch.svcr; - fp_state.fpmr = &vcpu->arch.fpmr; + fp_state.fpmr = &__vcpu_sys_reg(vcpu, FPMR); fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 9cfe6bd1dbe4..4fad3c7d2d89 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -322,10 +322,15 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) isb(); /* Write out the host state if it's in the registers */ - if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) + if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) { __fpsimd_save_state(vcpu->arch.host_fpsimd_state); + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + *vcpu->arch.host_fpmr = read_sysreg_s(SYS_FPMR); + } /* Restore the guest state */ + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR); if (sve_guest) __hyp_sve_restore_guest(vcpu); else diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 99cdaa594b06..ad6c39178edc 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1806,6 +1806,15 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, .visibility = elx2_visibility, \ } +static unsigned int fpmr_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + return 0; + + return REG_HIDDEN; +} + /* * Since reset() callback and field val are not used for idregs, they will be * used for specific purposes for idregs. @@ -2165,6 +2174,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, { SYS_DESC(SYS_SVCR), undef_access }, + { SYS_DESC(SYS_FPMR), access_rw, reset_unknown, FPMR, + .visibility = fpmr_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0 }, From patchwork Thu Oct 26 12:44:30 2023 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324445; bh=4OXDOFakN2kGeGyBUbfy2pFYD4qDL67ZeSXZ8Z9LAmA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gk9ihdiGGV3KC1p2YzsPscPeHTn8J0JTqJG/cZ1rAhV2detVB0thWf3bSlpZt2LMD y7ShSDegeMFN/DgJNTSu+Bb6Dbv4bLRJoahHs06BE8d6AT20oDLoZ5JOS4y3IFf3Bh H8wGhArBm6igko4WihWjN+tF6GVOxZktgELX9VmKKE2mfbPKips0o7Z1Jitxwpuvyc 5rQk2bKOi9D7oRclFQUdseBUWjAE7fJ6DNMlYdc808Zni/PPEFA62rjT4fVZmiUpOa ag+Zx7rIthCk9hfN9l16ELs8Rh5clsS8rrbLaLcC1di5VHC1rHdYv9UASb4bz4ezrf /pd+mQhFdlR9A== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:30 +0100 Subject: [PATCH 16/21] arm64/hwcap: Define hwcaps for 2023 DPISA features MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-16-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=12791; i=broonie@kernel.org; h=from:subject:message-id; bh=4OXDOFakN2kGeGyBUbfy2pFYD4qDL67ZeSXZ8Z9LAmA=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+gtbgo+cGG4P4PmvpcGxxA5j1nYbpjslXq2Tjr CGkljGOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfoAAKCRAk1otyXVSH0P1JB/ 9U8bkUm8lJD5GRHO3INoQInYh8KdGuaSYUkzl/LdxsTRZKVVlClrJHqRXOEbacKewVcfud/y2oB/sc 4NMFahxfzpv15VmFjdFwYW2CdGxJQu2/BNSgk2E0VULyS06YOdfEVCCa0d5355L0QNzS2as4JKJhKp tGC51WidN6o3gu9oozYQz86Z78j7bx8XCX2AYhEyEnD35V5lYpHJ6m7NAbZpEmkuhfLqUaaVN1vpF4 xV5pJlO5GRHTvQYL8dOF0TyfBHswVRBkYI2fjZdbDizCDJdT6DiG/eq+bru0IqD608b3BMnVNVNzU2 hA1VJ9XIA2DxlNCjeURQ9CI05BgUI5 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054727_036798_E5A7E9E7 X-CRM114-Status: UNSURE ( 9.56 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The 2023 architecture extensions include a large number of floating point features, most of which simply add new instructions. Add hwcaps so that userspace can enumerate these features. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 49 +++++++++++++++++++++++++++++++++ arch/arm64/include/asm/hwcap.h | 15 ++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 15 ++++++++++ arch/arm64/kernel/cpufeature.c | 35 +++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 15 ++++++++++ 5 files changed, 129 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 76ff9d7398fd..777d8b868f98 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -308,6 +308,55 @@ HWCAP2_MOPS HWCAP2_HBC Functionality implied by ID_AA64ISAR2_EL1.BC == 0b0001. +HWCAP2_FPMR + Functionality implied by ID_AA64PFR2_EL1.FMR == 0b0001. + +HWCAP2_LUT + Functionality implied by ID_AA64ISAR2_EL1.LUT == 0b0001. + +HWCAP2_FAMINMAX + Functionality implied by ID_AA64ISAR3_EL1.FAMINMAX == 0b0001. + +HWCAP2_F8CVT + Functionality implied by ID_AA64FPFR0_EL1.F8CVT == 0b1. + +HWCAP2_F8FMA + Functionality implied by ID_AA64FPFR0_EL1.F8FMA == 0b1. + +HWCAP2_F8DP4 + Functionality implied by ID_AA64FPFR0_EL1.F8DP4 == 0b1. + +HWCAP2_F8DP2 + Functionality implied by ID_AA64FPFR0_EL1.F8DP2 == 0b1. + +HWCAP2_F8E4M3 + Functionality implied by ID_AA64FPFR0_EL1.F8E4M3 == 0b1. + +HWCAP2_F8E5M2 + Functionality implied by ID_AA64FPFR0_EL1.F8E5M2 == 0b1. + +HWCAP2_SME_LUTV2 + Functionality implied by ID_AA64SMFR0_EL1.LUTv2 == 0b1. + +HWCAP2_SME_F8F16 + Functionality implied by ID_AA64SMFR0_EL1.F8F16 == 0b1. + +HWCAP2_SME_F8F32 + Functionality implied by ID_AA64SMFR0_EL1.F8F32 == 0b1. + +HWCAP2_SME_SF8FMA + Functionality implied by ID_AA64SMFR0_EL1.SF8FMA == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + +HWCAP2_SME_SF8DP2 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP2 == 0b1. + +HWCAP2_SME_SF8DP4 + Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. + + 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 521267478d18..046978936d25 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -139,6 +139,21 @@ #define KERNEL_HWCAP_SME_F16F16 __khwcap2_feature(SME_F16F16) #define KERNEL_HWCAP_MOPS __khwcap2_feature(MOPS) #define KERNEL_HWCAP_HBC __khwcap2_feature(HBC) +#define KERNEL_HWCAP_FPMR __khwcap2_feature(FPMR) +#define KERNEL_HWCAP_LUT __khwcap2_feature(LUT) +#define KERNEL_HWCAP_FAMINMAX __khwcap2_feature(FAMINMAX) +#define KERNEL_HWCAP_F8CVT __khwcap2_feature(F8CVT) +#define KERNEL_HWCAP_F8FMA __khwcap2_feature(F8FMA) +#define KERNEL_HWCAP_F8DP4 __khwcap2_feature(F8DP4) +#define KERNEL_HWCAP_F8DP2 __khwcap2_feature(F8DP2) +#define KERNEL_HWCAP_F8E4M3 __khwcap2_feature(F8E4M3) +#define KERNEL_HWCAP_F8E5M2 __khwcap2_feature(F8E5M2) +#define KERNEL_HWCAP_SME_LUTV2 __khwcap2_feature(SME_LUTV2) +#define KERNEL_HWCAP_SME_F8F16 __khwcap2_feature(SME_F8F16) +#define KERNEL_HWCAP_SME_F8F32 __khwcap2_feature(SME_F8F32) +#define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) +#define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) +#define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 53026f45a509..0f0aa9006cef 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -104,5 +104,20 @@ #define HWCAP2_SME_F16F16 (1UL << 42) #define HWCAP2_MOPS (1UL << 43) #define HWCAP2_HBC (1UL << 44) +#define HWCAP2_FPMR (1UL << 45) +#define HWCAP2_LUT (1UL << 46) +#define HWCAP2_FAMINMAX (1UL << 47) +#define HWCAP2_F8CVT (1UL << 48) +#define HWCAP2_F8FMA (1UL << 49) +#define HWCAP2_F8DP4 (1UL << 50) +#define HWCAP2_F8DP2 (1UL << 51) +#define HWCAP2_F8E4M3 (1UL << 52) +#define HWCAP2_F8E5M2 (1UL << 53) +#define HWCAP2_SME_LUTV2 (1UL << 54) +#define HWCAP2_SME_F8F16 (1UL << 55) +#define HWCAP2_SME_F8F32 (1UL << 56) +#define HWCAP2_SME_SF8FMA (1UL << 57) +#define HWCAP2_SME_SF8DP4 (1UL << 58) +#define HWCAP2_SME_SF8DP2 (1UL << 59) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 8e8cd411d1a2..2c85bc9e644c 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -220,6 +220,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), @@ -235,6 +236,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -301,6 +303,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -313,6 +317,10 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), @@ -323,10 +331,22 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), ARM64_FTR_END, }; static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -2838,6 +2858,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), + HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), @@ -2850,6 +2871,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), + HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), + HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), @@ -2889,6 +2912,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { #ifdef CONFIG_ARM64_SME HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), + HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), @@ -2896,12 +2920,23 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), + HWCAP_CAP(ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), HWCAP_CAP(ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), HWCAP_CAP(ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), HWCAP_CAP(ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), #endif /* CONFIG_ARM64_SME */ + HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), + HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index e153c6d2b3fd..9ff497ca70b4 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -127,6 +127,21 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_F16F16] = "smef16f16", [KERNEL_HWCAP_MOPS] = "mops", [KERNEL_HWCAP_HBC] = "hbc", + [KERNEL_HWCAP_FPMR] = "fpmr", + [KERNEL_HWCAP_LUT] = "lut", + [KERNEL_HWCAP_FAMINMAX] = "faminmax", + [KERNEL_HWCAP_F8CVT] = "f8cvt", + [KERNEL_HWCAP_F8FMA] = "f8fma", + [KERNEL_HWCAP_F8DP4] = "f8dp4", + [KERNEL_HWCAP_F8DP2] = "f8dp2", + [KERNEL_HWCAP_F8E4M3] = "f8e4m3", + [KERNEL_HWCAP_F8E5M2] = "f8e5m2", + [KERNEL_HWCAP_SME_LUTV2] = "smelutv2", + [KERNEL_HWCAP_SME_F8F16] = "smef8f16", + [KERNEL_HWCAP_SME_F8F32] = "smef8f32", + [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", + [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", + [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", }; #ifdef CONFIG_COMPAT From patchwork Thu Oct 26 12:44:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437589 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BE26C25B67 for ; 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a=openpgp-sha256; l=1642; i=broonie@kernel.org; h=from:subject:message-id; bh=jvyJQ++Epw5Vr3/tG/z6+6Y9vzI/cjN2rH2C/CkHcMI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+hZwT3cvJYy1Fe0uSW7ilAIrLsfVqPDMGDJBj+ sbstakqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfoQAKCRAk1otyXVSH0Hv0B/ 4nU5Ksm38FJDiCveE6OFGBsnIzpJDyX5B6sIhBu3Hl0BRah5M1xTjHcMiIm+tZYNtK7A/5Z9igDFLn vNObblCdl7Pf26XGmZmPx7+GpFxwlq/nn5m/3nes5vNmxDpP90Xu27GOBXleBmDXoapTzQYpSR4tLo cZ71uqvXuuahXvfgmOaWvsaIwHtvghjgiyaXPqaWlx0Zlpe+PnvYO90G3vu8XSdKyDr4/WgJ8UeRDn he7bt6QgTMyill3+AVZfnF0RrEq8sNQSMkcEdwvh0FwSjyh/bzeRq/PRFgckvyBHTxt2G1bofy84dv z/899qHVwAUbBHauS2P+WXL652lg/n X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054730_490824_57952B8A X-CRM114-Status: GOOD ( 10.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Teach the generic signal frame parsing code about the newly added FPMR frame, avoiding warnings every time one is generated. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/testcases/testcases.c | 8 ++++++++ tools/testing/selftests/arm64/signal/testcases/testcases.h | 1 + 2 files changed, 9 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.c b/tools/testing/selftests/arm64/signal/testcases/testcases.c index 9f580b55b388..674b88cc8c39 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.c +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.c @@ -209,6 +209,14 @@ bool validate_reserved(ucontext_t *uc, size_t resv_sz, char **err) zt = (struct zt_context *)head; new_flags |= ZT_CTX; break; + case FPMR_MAGIC: + if (flags & FPMR_CTX) + *err = "Multiple FPMR_MAGIC"; + else if (head->size != + sizeof(struct fpmr_context)) + *err = "Bad size for fpmr_context"; + new_flags |= FPMR_CTX; + break; case EXTRA_MAGIC: if (flags & EXTRA_CTX) *err = "Multiple EXTRA_MAGIC"; diff --git a/tools/testing/selftests/arm64/signal/testcases/testcases.h b/tools/testing/selftests/arm64/signal/testcases/testcases.h index a08ab0d6207a..7727126347e0 100644 --- a/tools/testing/selftests/arm64/signal/testcases/testcases.h +++ b/tools/testing/selftests/arm64/signal/testcases/testcases.h @@ -19,6 +19,7 @@ #define ZA_CTX (1 << 2) #define EXTRA_CTX (1 << 3) #define ZT_CTX (1 << 4) +#define FPMR_CTX (1 << 5) #define KSFT_BAD_MAGIC 0xdeadbeef From patchwork Thu Oct 26 12:44:32 2023 Content-Type: text/plain; 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Thu, 26 Oct 2023 12:47:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324452; bh=irtBwegYB+DXpSWW34B5isPMLTYQBsVR3AqcPDPAR5U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=q7eesor6jinYv1yB55Uk+bcBdg+AJLhjm5ZLF6zBH8KhRoRygSwflSE11ZnmIg8LT HKgn7xLfkovVka3xpV/ctbXpN/RqI2ol9gjPb0kBwz3XVC1FIHCWKNiVhapdKa34JS 0ty5Qt0NdqywOb9aQY0Du0PEo2JuVTUQSpnX0+BMB4gpRcL2n0CcGpZnuKZZGPvJu6 p80vrWDCMXegTUBI59EhRRZoxo/TfWSW27te7L516UJ018JMK5SR3hFQ89f/G3lyHb VDhbqciu58fMVdlwI+c7Uajrj4SIAXfHE0oal89MKEUUwwWRIgg1i/OoQcNaT0//oI Mu54FxoYuiSUg== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:32 +0100 Subject: [PATCH 18/21] kselftest/arm64: Add basic FPMR test MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-18-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/signal/.gitignore | 1 + .../arm64/signal/testcases/fpmr_siginfo.c | 82 ++++++++++++++++++++++ 2 files changed, 83 insertions(+) diff --git a/tools/testing/selftests/arm64/signal/.gitignore b/tools/testing/selftests/arm64/signal/.gitignore index 839e3a252629..1ce5b5eac386 100644 --- a/tools/testing/selftests/arm64/signal/.gitignore +++ b/tools/testing/selftests/arm64/signal/.gitignore @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only mangle_* fake_sigreturn_* +fpmr_* sme_* ssve_* sve_* diff --git a/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c new file mode 100644 index 000000000000..e9d24685e741 --- /dev/null +++ b/tools/testing/selftests/arm64/signal/testcases/fpmr_siginfo.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 ARM Limited + * + * Verify that the FPMR register context in signal frames is set up as + * expected. + */ + +#include +#include +#include +#include +#include +#include + +#include "test_signals_utils.h" +#include "testcases.h" + +static union { + ucontext_t uc; + char buf[1024 * 128]; +} context; + +#define SYS_FPMR "S3_3_C4_C4_2" + +static uint64_t get_fpmr(void) +{ + uint64_t val; + + asm volatile ( + "mrs %0, " SYS_FPMR "\n" + : "=r"(val) + : + : "cc"); + + return val; +} + +int fpmr_present(struct tdescr *td, siginfo_t *si, ucontext_t *uc) +{ + struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context); + struct fpmr_context *fpmr_ctx; + size_t offset; + bool in_sigframe; + bool have_fpmr; + __u64 orig_fpmr; + + have_fpmr = getauxval(AT_HWCAP2) & HWCAP2_FPMR; + if (have_fpmr) + orig_fpmr = get_fpmr(); + + if (!get_current_context(td, &context.uc, sizeof(context))) + return 1; + + fpmr_ctx = (struct fpmr_context *) + get_header(head, FPMR_MAGIC, td->live_sz, &offset); + + in_sigframe = fpmr_ctx != NULL; + + fprintf(stderr, "FPMR sigframe %s on system %s FPMR\n", + in_sigframe ? "present" : "absent", + have_fpmr ? "with" : "without"); + + td->pass = (in_sigframe == have_fpmr); + + if (have_fpmr && fpmr_ctx) { + if (fpmr_ctx->fpmr != orig_fpmr) { + fprintf(stderr, "FPMR in frame is %llx, was %llx\n", + fpmr_ctx->fpmr, orig_fpmr); + td->pass = false; + } + } + + return 0; +} + +struct tdescr tde = { + .name = "FPMR", + .descr = "Validate that FPMR is present as expected", + .timeout = 3, + .run = fpmr_present, +}; From patchwork Thu Oct 26 12:44:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13437591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4AFABC27C48 for ; Thu, 26 Oct 2023 12:48:41 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 26 Oct 2023 12:47:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id C5000B83575; Thu, 26 Oct 2023 12:47:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFA5BC433CD; Thu, 26 Oct 2023 12:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324455; bh=DV5vbUJP6sOS/WhgLcddZ8/jeMJVH5w/HMgfFosNI2U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oJU/6tspXm3T+rmBm1OmP1zOQmItkFTpSPldry2fDspeBQbWeHcZJDMRKHmFC1kdP 34h+Hl/W91keQkXjpR4xyPOdYsjkaPZ8GaLbv/WQ0dwGfXWL9RNA5ZLKlQUjz4TXU6 YkxSw82Kc7Jy5qne7ysYkIlA3Ou2tzFciogJCEyxtdVNQ7gSW4BgRsAmuQ/c41Kqs1 B6vdhUHM3aTxFWlfe9QlAQQr3A6uklC67kAsT1wp+tjaKkAD8YmlCHHq/i8RADYJjZ twoQZXW80OReILO4TR4Tzun95v41dadSIftyGrUYHgRN1IrLHkO63NrMGHxsWpsj+U 85mCU3B59m4Dw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:33 +0100 Subject: [PATCH 19/21] kselftest/arm64: Add 2023 DPISA hwcap test coverage MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-19-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 217 ++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index e3d262831d91..ffc0ad1a9b16 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -58,11 +58,46 @@ static void cssc_sigill(void) asm volatile(".inst 0xdac01c00" : : : "x0"); } +static void f8cvt_sigill(void) +{ + /* FSCALE V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec03c00"); +} + +static void f8dp2_sigill(void) +{ + /* FDOT V0.4H, V0.4H, V0.5H */ + asm volatile(".inst 0xe40fc00"); +} + +static void f8dp4_sigill(void) +{ + /* FDOT V0.2S, V0.2S, V0.2S */ + asm volatile(".inst 0xe00fc00"); +} + +static void f8fma_sigill(void) +{ + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); +} + +static void faminmax_sigill(void) +{ + /* FAMIN V0.4H, V0.4H, V0.4H */ + asm volatile(".inst 0x2ec01c00"); +} + static void fp_sigill(void) { asm volatile("fmov s0, #1"); } +static void fpmr_sigill(void) +{ + asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); +} + static void ilrcpc_sigill(void) { /* LDAPUR W0, [SP, #8] */ @@ -81,6 +116,12 @@ static void lrcpc_sigill(void) asm volatile(".inst 0xb8bfc3e0" : : : ); } +static void lut_sigill(void) +{ + /* LUTI2 V0.16B, { V0.16B }, V[0] */ + asm volatile(".inst 0x4e801000"); +} + static void mops_sigill(void) { char dst[1], src[1]; @@ -202,6 +243,78 @@ static void smef16f16_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } +static void smef8f16_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.H[W0, 0], Z0.B-Z1.B, Z0.B-Z1.B */ + asm volatile(".inst 0xc1a01020" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smef8f32_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT ZA.S[W0, 0], { Z0.B-Z1.B }, Z0.B[0] */ + asm volatile(".inst 0xc1500038" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smelutv2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* LUTI4 { Z0.B-Z3.B }, ZT0, { Z0-Z1 } */ + asm volatile(".inst 0xc08b0000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp2_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.H, Z0.B, Z0.B[0] */ + asm volatile(".inst 0x64204400" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8dp4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FDOT Z0.S, Z0.B, Z0.B[0] */ + asm volatile(".inst 0xc1a41C00" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8fma_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMLALB V0.8H, V0.16B, V0.16B */ + asm volatile(".inst 0xec0fc00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void sve_sigill(void) { /* RDVL x0, #0 */ @@ -320,6 +433,53 @@ static const struct hwcap_data { .cpuinfo = "cssc", .sigill_fn = cssc_sigill, }, + { + .name = "F8CVT", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8CVT, + .cpuinfo = "f8cvt", + .sigill_fn = f8cvt_sigill, + }, + { + .name = "F8DP4", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8DP4, + .cpuinfo = "f8dp4", + .sigill_fn = f8dp4_sigill, + }, + { + .name = "F8DP2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8DP2, + .cpuinfo = "f8dp4", + .sigill_fn = f8dp2_sigill, + }, + { + .name = "F8E5M2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8E5M2, + .cpuinfo = "f8e5m2", + }, + { + .name = "F8E4M3", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8E4M3, + .cpuinfo = "f8e4m3", + }, + { + .name = "F8FMA", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_F8FMA, + .cpuinfo = "f8fma", + .sigill_fn = f8fma_sigill, + }, + { + .name = "FAMINMAX", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_FAMINMAX, + .cpuinfo = "faminmax", + .sigill_fn = faminmax_sigill, + }, { .name = "FP", .at_hwcap = AT_HWCAP, @@ -327,6 +487,14 @@ static const struct hwcap_data { .cpuinfo = "fp", .sigill_fn = fp_sigill, }, + { + .name = "FPMR", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_FPMR, + .cpuinfo = "fpmr", + .sigill_fn = fpmr_sigill, + .sigill_reliable = true, + }, { .name = "JSCVT", .at_hwcap = AT_HWCAP, @@ -364,6 +532,13 @@ static const struct hwcap_data { .sigbus_fn = uscat_sigbus, .sigbus_reliable = true, }, + { + .name = "LUT", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_LUT, + .cpuinfo = "lut", + .sigill_fn = lut_sigill, + }, { .name = "MOPS", .at_hwcap = AT_HWCAP2, @@ -464,6 +639,48 @@ static const struct hwcap_data { .cpuinfo = "smef16f16", .sigill_fn = smef16f16_sigill, }, + { + .name = "SME F8F16", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_F8F16, + .cpuinfo = "smef8f16", + .sigill_fn = smef8f16_sigill, + }, + { + .name = "SME F8F32", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_F8F32, + .cpuinfo = "smef8f32", + .sigill_fn = smef8f32_sigill, + }, + { + .name = "SME LUTV2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_LUTV2, + .cpuinfo = "smelutv2", + .sigill_fn = smelutv2_sigill, + }, + { + .name = "SME SF8FMA", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8FMA, + .cpuinfo = "smesf8fma", + .sigill_fn = smesf8fma_sigill, + }, + { + .name = "SME SF8DP2", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8DP2, + .cpuinfo = "smesf8dp2", + .sigill_fn = smesf8dp2_sigill, + }, + { + .name = "SME SF8DP4", + .at_hwcap = AT_HWCAP2, + .hwcap_bit = HWCAP2_SME_SF8DP4, + .cpuinfo = "smesf8dp4", + .sigill_fn = smesf8dp4_sigill, + }, { .name = "SVE", .at_hwcap = AT_HWCAP, From patchwork Thu Oct 26 12:44:34 2023 Content-Type: text/plain; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324458; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=JwavNWQ7Qw92WJ9PaGFEOjbAckxxdipb5X3kcuitU6FhySsU0xjhk4HSxtN6h21O5 91aWAqZiNQknMOXNqZ9gAgIuVKiPLQQgg70DAR85CjFcIHiPgjAkpYgEcTaoyCeTRA jTwTcjIaO+RK/gVZFYCi69E/pfMpMDdentwpOqgzEL0mIgkJca+6bnn4Y3C1hNEAEh iZXWJdtsrASdl7JIhFUKzB+bEip1ETlQo7cQ4yeUuonHp/nAJa+r7A6v71SS6/a8Ma 7O6PfoHqkQsVb7e32Vix/OCbJvaSfw6bl7AHkOjCp3fT12AwzbSey2KoEBH8g2i4gQ jBvGMw55JuvdA== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:34 +0100 Subject: [PATCH 20/21] KVM: arm64: selftests: Document feature registers added in 2023 extensions MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-20-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; 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Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 709d7d721760..71ea6ecec7ce 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -428,7 +428,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 4, 4), /* ID_AA64ZFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 5), /* ID_AA64SMFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 6), - ARM64_SYS_REG(3, 0, 0, 4, 7), + ARM64_SYS_REG(3, 0, 0, 4, 7), /* ID_AA64FPFR_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 0), /* ID_AA64DFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 1), /* ID_AA64DFR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 2), @@ -440,7 +440,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 6, 0), /* ID_AA64ISAR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 1), /* ID_AA64ISAR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 2), /* ID_AA64ISAR2_EL1 */ - ARM64_SYS_REG(3, 0, 0, 6, 3), + ARM64_SYS_REG(3, 0, 0, 6, 3), /* ID_AA64ISAR3_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 4), ARM64_SYS_REG(3, 0, 0, 6, 5), ARM64_SYS_REG(3, 0, 0, 6, 6), From patchwork Thu Oct 26 12:44:35 2023 Content-Type: text/plain; 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Thu, 26 Oct 2023 12:47:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698324461; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=BCbUeVMSLhmUhFPwkQmPbkSxvD6sZ+0tGomwpFVcTUkvM4DiC6sKCLfmhdX6jP4E/ rE+1Y45LmR+Upf/C2sptY3bG3skk/ISDZ7gu5NJHRHRf7g2xra3piivHUYFVbhfbjU 2v4HDpnpKnSG8SrZRsWPJ8EP7FHASxpCUPHiew+XeqMxCffvaaZqKyvtGq0JEBDFgU +GrRN3mvDRafwD55DvgQhXgKFTGn02jmUarpYR61HBJJsU3ConX42XWkcLGdZs6HlS 5dG3y9diDUDK7potFmEHtJ3f130cKxlGbroXBoxT1mvljL9PhmSAuid6zN4gzgUZkG 9RNyLCXH2YyKw== From: Mark Brown Date: Thu, 26 Oct 2023 13:44:35 +0100 Subject: [PATCH 21/21] KVM: arm64: selftests: Teach get-reg-list about FPMR MIME-Version: 1.0 Message-Id: <20231026-arm64-2023-dpisa-v1-21-8470dd989bb2@kernel.org> References: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> In-Reply-To: <20231026-arm64-2023-dpisa-v1-0-8470dd989bb2@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-0438c X-Developer-Signature: v=1; a=openpgp-sha256; l=1321; i=broonie@kernel.org; h=from:subject:message-id; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBlOl+kwgjY6EVwPCWQAVwgyV3h0FLsAbgfLrWaEGga OKJk0qKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZTpfpAAKCRAk1otyXVSH0D2fB/ 494ePdNnodIbyo2n2nTy3SIDha1NJ+Yk/N/0U2hqFK8LTDjl9leOHfSnS0lYLPhmLkc3P66i2gSxIp DJwCrOWCjxu4pBWqxCZqSHKbUA6bqMTe/2KdxAOOC0k7o6aqIHQnNNpFfi6K7hDd7Ln6Z+6mvvXaTD rgCk1adl3U3KkYLqfLHrypTVRQOOvg8vGWgklqQCDar8031EFJ+bhM6fw1DSLYurB/TMlNj+Xb1o/0 bODwv093DYlcKRSTC43nHEDHKbHp3aSPs0C/7TRWgUmeOuYoNKwYEFp8vf1GE5w0Uw49sO9pDRVupE 7wZB3IlsnyvCjrAr5HMl1su5FB66kq X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231026_054743_948188_493C2106 X-CRM114-Status: UNSURE ( 9.65 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_FPMR defines a new register FMPR which is available at all ELs and is discovered via ID_AA64PFR2_EL1.FPMR, add this to the set of registers that get-reg-list knows to check for with the required identification register depdendency. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 71ea6ecec7ce..1e43511d1440 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -40,6 +40,12 @@ static struct feature_id_reg feat_id_regs[] = { ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ 4, 1 + }, + { + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ + ARM64_SYS_REG(3, 0, 0, 4, 2), /* ID_AA64PFR2_EL1 */ + 32, + 1 } }; @@ -481,6 +487,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ };