From patchwork Fri Oct 27 22:10:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93A28C25B48 for ; Fri, 27 Oct 2023 22:11:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346624AbjJ0WLV (ORCPT ); Fri, 27 Oct 2023 18:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346583AbjJ0WLT (ORCPT ); Fri, 27 Oct 2023 18:11:19 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B18181B6; Fri, 27 Oct 2023 15:11:17 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.west.internal (Postfix) with ESMTP id D0BC43200930; Fri, 27 Oct 2023 18:11:13 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Fri, 27 Oct 2023 18:11:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444673; x= 1698531073; bh=QkagzItTcmygJhd+IgCnn6qdrUYk56vVzdHfbFmNb0k=; b=U 5qTKlfx1FZYPNAKnzlTeLKGKoofCV7h76mwVgJ50l/M6yFvDiBQrVIRc3F3UIamy RNdQTuGM3mqjx+YXckktQGhOPZy0iggxdsf59DjA8s2e29ANS/6kMEEfoOiOQEIi I0C+R/BuYbWM/InhMq1Y9ZTH8awtTpJG9tgUcySj7KuTFnJlAns2fLgbUnz/RXCk xV0Z1vsKuHqotYnHQWDnsCKOL9/6GBvhzmaPeSTTvmn61/gx6VteF2wTx49AErHQ J3meEd9xI2tsXBX+0CqLVKzZdLXQd90xrmovm5tBi/kdQDd/dfiDAbw+0pXu9rws knnY8gcrDNT2F2kqA+F2A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444673; x= 1698531073; bh=QkagzItTcmygJhd+IgCnn6qdrUYk56vVzdHfbFmNb0k=; b=e cq6gFaFi5FoZ0T12bdQZf0URDU0JWp3hUeKNP5Ien5CVyaSgB+YaR3JdtEy179cg ZIPpHfRnST41jiFW9SbwYbObuhqVbHdYRFTMIB9mOqRCk5NqN+Jjx9KUyhHtS2rO eOpQBo5ROzqDAlkwbwZse46nHo1WiCcN+wshDLtlkGI2jWA3OyVrpN1OINqmthI6 Zxp3guM85S8wVpsIZ8Jtfum+0uXb1Mii4+5GIooKn/SrSrj6/av54t7VsIYft6kG VeGr2xSZWfvuynaAkROFIOd3ML7wd7U5TjaKHYb1d/BO9T+lxgYqw1s/UuiJKMtg waHNVGX1XEZ+zl4gBfV3g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvuedvvd egkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhiiigv pedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihgh horghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:12 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 01/10] MIPS: Export higher/highest relocation functions in uasm Date: Fri, 27 Oct 2023 23:10:57 +0100 Message-Id: <20231027221106.405666-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Export uasm_rel_{higher,highest} functions. Those functions can be helpful in dealing with 64bit immediates. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/uasm.h | 2 ++ arch/mips/mm/uasm.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 296bcf31abb5..12db6d2fca07 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr, #ifdef CONFIG_64BIT int uasm_in_compat_space_p(long addr); #endif +int uasm_rel_highest(long val); +int uasm_rel_higher(long val); int uasm_rel_hi(long val); int uasm_rel_lo(long val); void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62..6846bf2084c5 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr) } UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); -static int uasm_rel_highest(long val) +int uasm_rel_highest(long val) { #ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; @@ -433,8 +433,9 @@ static int uasm_rel_highest(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_highest); -static int uasm_rel_higher(long val) +int uasm_rel_higher(long val) { #ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; @@ -442,6 +443,7 @@ static int uasm_rel_higher(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_higher); int uasm_rel_hi(long val) { From patchwork Fri Oct 27 22:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC24AC25B47 for ; Fri, 27 Oct 2023 22:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346633AbjJ0WLV (ORCPT ); Fri, 27 Oct 2023 18:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346620AbjJ0WLU (ORCPT ); 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Fri, 27 Oct 2023 18:11:14 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros Date: Fri, 27 Oct 2023 23:10:58 +0100 Message-Id: <20231027221106.405666-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org KSEGX_SIZE is defined to size of each KSEG segment. TO_CAC and TO_UNCAC are brought to 32bit builds as well, TO_PHYS remains to be 64bit only as we want people to use __pa to avoid mixup compat address space. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/addrspace.h | 5 +++++ arch/mips/include/asm/mach-generic/spaces.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065..03a5e2c8b5dc 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -47,6 +47,11 @@ */ #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) +/* + * Gives the size of each kernel segment + */ +#define KSEGX_SIZE 0x20000000 + /* * Returns the physical address of a CKSEGx / XKPHYS address */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b247575c5e69..05db19521e81 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -79,11 +79,12 @@ #endif #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #endif /* CONFIG_64BIT */ +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) + /* * This handles the memory map. */ From patchwork Fri Oct 27 22:10:59 2023 Content-Type: text/plain; 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Fri, 27 Oct 2023 18:11:17 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 03/10] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Date: Fri, 27 Oct 2023 23:10:59 +0100 Message-Id: <20231027221106.405666-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use {highest, higher, hi, lo} immediate loading sequence to load 64 bit jump address for handler when kernel is loaded to XKPHYS. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/genex.S | 19 +++++++++++++++---- arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..fd765ad9ecac 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler -FEXPORT(except_vec_vi_lui) - lui v0, 0 /* Patched */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) +FEXPORT(except_vec_vi_hi) + lui v0, 0 /* Patched */ +#else +FEXPORT(except_vec_vi_highest) + lui v0, 0 /* Patched */ +FEXPORT(except_vec_vi_higher) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +FEXPORT(except_vec_vi_hi) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +#endif jr v1 -FEXPORT(except_vec_vi_ori) - ori v0, 0 /* Patched */ +FEXPORT(except_vec_vi_lo) + PTR_ADDIU v0, 0 /* Patched */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..60c513c51684 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_hi[]; + extern const u8 except_vec_vi_lo[], except_vec_vi_end[]; +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + extern const u8 except_vec_vi_highest[], except_vec_vi_higher[]; +#endif extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) - const int lui_offset = except_vec_vi_lui - vec_start + 2; - const int ori_offset = except_vec_vi_ori - vec_start + 2; + const int imm_offset = 2; #else - const int lui_offset = except_vec_vi_lui - vec_start; - const int ori_offset = except_vec_vi_ori - vec_start; + const int imm_offset = 0; +#endif +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + const int highest_offset = except_vec_vi_highest - vec_start + imm_offset; + const int higher_offset = except_vec_vi_higher - vec_start + imm_offset; #endif + const int hi_offset = except_vec_vi_hi - vec_start + imm_offset; + const int lo_offset = except_vec_vi_lo - vec_start + imm_offset; + const int handler_len = except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { @@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif - h = (u16 *)(b + lui_offset); - *h = (handler >> 16) & 0xffff; - h = (u16 *)(b + ori_offset); - *h = (handler & 0xffff); +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + h = (u16 *)(b + highest_offset); + *h = uasm_rel_highest(handler); + h = (u16 *)(b + higher_offset); + *h = uasm_rel_higher(handler); +#endif + h = (u16 *)(b + hi_offset); + *h = uasm_rel_hi(handler); + h = (u16 *)(b + lo_offset); + *h = uasm_rel_lo(handler); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } From patchwork Fri Oct 27 22:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DC68C25B6F for ; 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Fri, 27 Oct 2023 18:11:19 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 04/10] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Fri, 27 Oct 2023 23:11:00 +0100 Message-Id: <20231027221106.405666-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org ebase may be in XKPHYS if memblock unable to allocate memory within KSEG0 physical range. To map ebase into uncached space we just convert it back to physical address and then use platform's TO_UNCAC helper to create mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 60c513c51684..230728d76d11 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = TO_UNCAC(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Fri Oct 27 22:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439207 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 045C7C25B6E for ; Fri, 27 Oct 2023 22:11:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346649AbjJ0WLh (ORCPT ); Fri, 27 Oct 2023 18:11:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346662AbjJ0WL3 (ORCPT ); Fri, 27 Oct 2023 18:11:29 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2076A1BC; Fri, 27 Oct 2023 15:11:25 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 1301032008FE; Fri, 27 Oct 2023 18:11:23 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 27 Oct 2023 18:11:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444683; x= 1698531083; bh=B/eSduiT5SSuDZgp+rtGBx4PnZ8+7CU6vuXEb/G0fc4=; b=m N9rnu7TkUZnABboEAbBSpLOUbZO8DRmpIJZCIg4UlizjaOiHmOk74QoeX9/yxQdt jeAgCwWB3rAl6maepDTbAVvr3s1T3GBL0s73+jeIkoPcPu2du6NRVNHnQfGRNKBF 3em1J7RQ1KIHDWKLTP30Jdej1KhmB669bebGwHdkVMZX6o2P/5zUgOel0yFwga+i P1Sg9Pu+7pXtJseN7FDKgTC1UU5Aelx5SW5wQHkexLoWzwtd1ShjvNNTsedcRrqa Kt3L8ez4wIf3Pfej31cC3fiSJ3W6WbEgF/PF3nWkqr/ncO3XivsbJ2irzDwskwGx 606wXrdS/48+pmjkefdSw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444683; x= 1698531083; bh=B/eSduiT5SSuDZgp+rtGBx4PnZ8+7CU6vuXEb/G0fc4=; b=T MpResMzWITJRydGI1GgCvy1enxguXuef6bgLjaYrskbag7X0iEK7kLGSDX1/mpMc kEJQlNF4uVJbgqWNrxkpo4lF1gGK+SjAkcEpv3GDncRqEgXFzlre95X6kXZ3yUwQ 6s/tv/OycMEDudF9LKT3rdTGqswzwKoMMeRqxNbuNBenplljPYHZ4NI6PK2pCy0k Fk4uS09/EFrNabNV1Sy0f0uizFPsEqNdE1pz/A0NCYwSXwrTu2BCmaidifAYYG0n jZEmlXwdywn6LnIQRtX7WmKPxrF5Vq/kTifvLSwcwydTVdw1lG/eMER+Lve7s/Jq z6guz22B+zyTWD+dsHZSg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeevgfdtleegudehgeeiud ejtdfgtedvudejleevheduhfdvieegtddvvdevffdvhfenucffohhmrghinheptghpshdq vhgvtgdrshgsnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepjhhirgiguhhnrdihrghnghesfhhlhihgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:22 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Date: Fri, 27 Oct 2023 23:11:01 +0100 Message-Id: <20231027221106.405666-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/smp-cps.h | 4 +- arch/mips/kernel/cps-vec.S | 110 ++++++++------------- arch/mips/kernel/smp-cps.c | 167 +++++++++++++++++++++++++++----- arch/mips/kernel/traps.c | 2 + 5 files changed, 186 insertions(+), 98 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..15d8d69de455 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 22a572b70fe3..39a602e5fecc 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -24,7 +24,7 @@ struct core_boot_config { extern struct core_boot_config *mips_cps_core_bootcfg; -extern void mips_cps_core_entry(void); +extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); @@ -32,8 +32,6 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); -extern void *mips_cps_core_entry_patch_end; - #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580..8870a2dbc35a 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,6 +4,8 @@ * Author: Paul Burton */ +#include + #include #include #include @@ -81,40 +83,48 @@ nop .endm + __INIT +LEAF(excep_tlbfill) + DUMP_EXCEP("TLB Fill") + b . + nop + END(excep_tlbfill) -.balign 0x1000 +LEAF(excep_xtlbfill) + DUMP_EXCEP("XTLB Fill") + b . + nop + END(excep_xtlbfill) -LEAF(mips_cps_core_entry) - /* - * These first several instructions will be patched by cps_smp_setup to load the - * CCA to use into register s0 and GCR base address to register s1. - */ - .rept CPS_ENTRY_PATCH_INSNS - nop - .endr +LEAF(excep_cache) + DUMP_EXCEP("Cache") + b . + nop + END(excep_cache) - .global mips_cps_core_entry_patch_end -mips_cps_core_entry_patch_end: +LEAF(excep_genex) + DUMP_EXCEP("General") + b . + nop + END(excep_genex) - /* Check whether we're here due to an NMI */ - mfc0 k0, CP0_STATUS - and k0, k0, ST0_NMI - beqz k0, not_nmi +LEAF(excep_intex) + DUMP_EXCEP("Interrupt") + b . nop + END(excep_intex) - /* This is an NMI */ - PTR_LA k0, nmi_handler +LEAF(excep_ejtag) + PTR_LA k0, ejtag_debug_handler jr k0 nop + END(excep_ejtag) + __FINIT -not_nmi: - /* Setup Cause */ - li t0, CAUSEF_IV - mtc0 t0, CP0_CAUSE - - /* Setup Status */ - li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS - mtc0 t0, CP0_STATUS +LEAF(mips_cps_core_boot) + /* Save CCA and GCR base */ + move s0, a0 + move s1, a1 /* We don't know how to do coherence setup on earlier ISA */ #if MIPS_ISA_REV > 0 @@ -178,49 +188,7 @@ not_nmi: PTR_L sp, VPEBOOTCFG_SP(v1) jr t1 nop - END(mips_cps_core_entry) - -.org 0x200 -LEAF(excep_tlbfill) - DUMP_EXCEP("TLB Fill") - b . - nop - END(excep_tlbfill) - -.org 0x280 -LEAF(excep_xtlbfill) - DUMP_EXCEP("XTLB Fill") - b . - nop - END(excep_xtlbfill) - -.org 0x300 -LEAF(excep_cache) - DUMP_EXCEP("Cache") - b . - nop - END(excep_cache) - -.org 0x380 -LEAF(excep_genex) - DUMP_EXCEP("General") - b . - nop - END(excep_genex) - -.org 0x400 -LEAF(excep_intex) - DUMP_EXCEP("Interrupt") - b . - nop - END(excep_intex) - -.org 0x480 -LEAF(excep_ejtag) - PTR_LA k0, ejtag_debug_handler - jr k0 - nop - END(excep_ejtag) + END(mips_cps_core_boot) LEAF(mips_cps_core_init) #ifdef CONFIG_MIPS_MT_SMP @@ -428,7 +396,7 @@ LEAF(mips_cps_boot_vpes) /* Calculate a pointer to the VPEs struct vpe_boot_config */ li t0, VPEBOOTCFG_SIZE mul t0, t0, ta1 - addu t0, t0, ta3 + PTR_ADDU t0, t0, ta3 /* Set the TC restart PC */ lw t1, VPEBOOTCFG_PC(t0) @@ -603,10 +571,10 @@ dcache_done: lw $1, TI_CPU(gp) sll $1, $1, LONGLOG PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest + PTR_ADDU $1, $1, \dest lw $1, 0($1) PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 + PTR_ADDU \dest, \dest, $1 .set pop .endm diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db..9aad678a32bd 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,33 @@ #include #include +#define BEV_VEC_SIZE 0x500 +#define BEV_VEC_ALIGN 0x1000 + +#define A0 4 +#define A1 5 +#define T9 25 +#define K0 26 +#define K1 27 + +#define C0_STATUS 12, 0 +#define C0_CAUSE 13, 0 + +#define ST0_NMI_BIT 19 +#ifdef CONFIG_64BIT +#define ST0_KX_IF_64 ST0_KX +#else +#define ST0_KX_IF_64 0 +#endif + +enum label_id { + label_not_nmi = 1, +}; + +UASM_L_LA(_not_nmi) + static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; struct core_boot_config *mips_cps_core_bootcfg; @@ -34,10 +61,113 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static void __init *mips_cps_build_core_entry(void *addr) +{ + extern void (*nmi_handler)(void); + u32 *p = addr; + u32 val; + struct uasm_label labels[2]; + struct uasm_reloc relocs[2]; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + uasm_i_mfc0(&p, K0, C0_STATUS); + if (cpu_has_mips_r2_r6) + uasm_i_ext(&p, K0, K0, ST0_NMI_BIT, 1); + else { + uasm_i_srl(&p, K0, K0, ST0_NMI_BIT); + uasm_i_andi(&p, K0, K0, 0x1); + } + + uasm_il_bnez(&p, &r, K0, label_not_nmi); + uasm_i_nop(&p); + UASM_i_LA(&p, K0, (long)&nmi_handler); + + uasm_l_not_nmi(&l, p); + + val = CAUSEF_IV; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_CAUSE); + val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_STATUS); + uasm_i_ehb(&p); + uasm_i_ori(&p, A0, 0, read_c0_config() & CONF_CM_CMASK); + UASM_i_LA(&p, A1, (long)mips_gcr_base); +#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) + UASM_i_LA(&p, T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); +#else + UASM_i_LA(&p, T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); +#endif + uasm_i_jr(&p, T9); + uasm_i_nop(&p); + + uasm_resolve_relocs(relocs, labels); + + return p; +} + +static int __init setup_cps_vecs(void) +{ + extern void excep_tlbfill(void); + extern void excep_xtlbfill(void); + extern void excep_cache(void); + extern void excep_genex(void); + extern void excep_intex(void); + extern void excep_ejtag(void); + phys_addr_t cps_vec_pa; + void *cps_vec; + + /* Try to allocate in KSEG1 first */ + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, KSEGX_SIZE - 1); + + if (cps_vec_pa) + core_entry_reg = CKSEG1ADDR(cps_vec_pa) & + CM_GCR_Cx_RESET_BASE_BEVEXCBASE; + + if (!cps_vec_pa && mips_cm_is64) { + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, SZ_4G - 1); + if (cps_vec_pa) + core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | + CM_GCR_Cx_RESET_BASE_MODE; + } + + if (!cps_vec_pa) + return -ENOMEM; + + /* We want to ensure cache is clean before writing uncached mem */ + blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + cps_vec = (void *)TO_UNCAC(cps_vec_pa); + mips_cps_build_core_entry(cps_vec); + + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); + memcpy(cps_vec + 0x300, &excep_cache, 0x80); + memcpy(cps_vec + 0x380, &excep_genex, 0x80); + memcpy(cps_vec + 0x400, &excep_intex, 0x80); + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); + + /* Make sure no prefetched data in cache */ + blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + return 0; +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +224,11 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (setup_cps_vecs()) + pr_err("Failed to setup CPS vectors\n"); + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable, cores_limited; - u32 *entry_code; mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); - /* - * Patch the start of mips_cps_core_entry to provide: - * - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; - uasm_i_addiu(&entry_code, 16, 0, cca); - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); - blast_dcache_range((unsigned long)&mips_cps_core_entry, - (unsigned long)entry_code); - bc_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); - __sync(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); @@ -213,7 +334,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +411,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +434,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 230728d76d11..ea59d321f713 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,6 +74,8 @@ #include "access-helper.h" +#define MAX(a, b) ((a) >= (b) ? (a) : (b)) + extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); extern asmlinkage void handle_int(void); From patchwork Fri Oct 27 22:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5156AC25B47 for ; Fri, 27 Oct 2023 22:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346700AbjJ0WLt (ORCPT ); Fri, 27 Oct 2023 18:11:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346679AbjJ0WLg (ORCPT ); Fri, 27 Oct 2023 18:11:36 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1507D4F; Fri, 27 Oct 2023 15:11:27 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.west.internal (Postfix) with ESMTP id 82BD53200959; Fri, 27 Oct 2023 18:11:26 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Fri, 27 Oct 2023 18:11:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444686; x= 1698531086; bh=U85JK5asZNHXyazqwXB2WH7hdrGFnY8ew4l7GY3z8ws=; b=s 4NE1qnOSBoS2iVrpYr9QuYwILsmugVjmKkQHUkY7J8eFHX0hrCQSvoopDEwBotlW 75gmShT5g5E4tvz1UMAqNrwhCfiAy7gPeH6liU8fgyG7ONmzaNwxhM6iTWVKolBh 7wk5MMtqkFneXOkP52T2QwM7zTBi3plmrHeFLW32f17mrdv00SCDrSMiDxhffARR UTLAyqB/E2ntdb5neEVMIXttkOhNB9bfiYRXLwaDi7n+IU4tGLVhV2LzDnH38R7T /sMJ/Iw9g2d4OYh6ta6PxiUnTzO5P7p163VAgfpkPoarMqyIyHD6bk24vf5LDA3Y me42xe4N4+v9qUtQlL8qw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444686; x= 1698531086; bh=U85JK5asZNHXyazqwXB2WH7hdrGFnY8ew4l7GY3z8ws=; b=q WaspJFc/VKdZJFR+rB5R4nwxBOUuy/43Y/PQaXS4k8QznexnhItpphmt8CEOEvV/ 3CQMgFX28dzc466fVcmMl7zLGoflURVfkm52jqNXskWpLmEv8dLbZXjtqYniJqeO XbYrc8H5MdcYWnyvAlnSb7sGfsqIupovxoibt0LP+VzuT3YA6WVRf94Q53nWAb0N 6ueWERQ1SlYKivZWlIWe76PT25zXu0OmCGiTgNQo5f7o4Pc61ozOT6AbQIEft5XH 9ggqr/gTkNrYZszsGPNIsdvGTKOm5adOefx2T4qa7/Kp1jJZhZp2a4zm98TFysw5 cdAb9K4ONijFXwE2puxbQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvuedvvd egkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhiiigv pedunecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihgh horghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:24 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 06/10] MIPS: Allow kernel base to be set from Kconfig for all platforms Date: Fri, 27 Oct 2023 23:11:02 +0100 Message-Id: <20231027221106.405666-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There are some platforms in wild that generic loading address won't work with them due to memory layout. Allow PHYSICAL_START to be override from Kconfig, introduce PHYSICAL_START_BOOL symbol as powerpc did. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc8421859006..bfedc8b48a81 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC config ARCH_SUPPORTS_CRASH_DUMP def_bool y +config PHYSICAL_START_BOOL + bool "Set physical address where the kernel is loaded" + default y if CRASH_DUMP + help + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. + + Say N here unless you know what you are doing. + config PHYSICAL_START - hex "Physical address where the kernel is loaded" - default "0xffffffff84000000" - depends on CRASH_DUMP + hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL + default "0xffffffff84000000" if CRASH_DUMP + default "0xffffffff80100000" help - This gives the CKSEG0 or KSEG0 address where the kernel is loaded. + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. If you plan to use kernel for capturing the crash dump change this value to start of the reserved region (the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter From patchwork Fri Oct 27 22:11:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85436C25B47 for ; Fri, 27 Oct 2023 22:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346705AbjJ0WLy (ORCPT ); Fri, 27 Oct 2023 18:11:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346685AbjJ0WLt (ORCPT ); Fri, 27 Oct 2023 18:11:49 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F40010CB; Fri, 27 Oct 2023 15:11:30 -0700 (PDT) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailout.west.internal (Postfix) with ESMTP id 043923200917; Fri, 27 Oct 2023 18:11:28 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute3.internal (MEProxy); Fri, 27 Oct 2023 18:11:29 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444688; x= 1698531088; bh=GQtOu2SP23PEZmWtQVCsoCbcovZ67XlhJHkFJBQ+htw=; b=d PUABwfkYjJ8KyexOxaDKxq6pLkPvSXI30MC8tsKixqPCMFpBqmfzsY8dbopgfqbP HPgeKeeXL+nCzC5E/JsjaP73LEbauuqPxyWEou9PQe0ZuOjG7xMAJ0FAgwNJ0V4g 6iBPV8jCPwhqXfa/NtQy+BLHwgq8m+nSeV0A0jqqYn1mDMdCzEGn7bYWZTRYBu9b amflf48Cxp7PIpR1fnKoIVT0Nyl6O+shMLg6qyOBzFJg3tadK79Ia6wf9pt3T+X2 oW2kOjjkbJEbYKkxUxOZxShD1UC39U4fqdJqWnYRT/m/5fkYswQSRwr+20+tFKvw H4tVA4Q54JUv/M0C97zJw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444688; x= 1698531088; bh=GQtOu2SP23PEZmWtQVCsoCbcovZ67XlhJHkFJBQ+htw=; b=t XtfXF8aRtxStrvk6+Ycyb5bEKE5893VEyJUcYWCfNSTIR3pT3eSAzeK4SEOwcLYX 0CdOvEAhGyc/T9tnwh9J3b8NFkHphDBO3VJy70EzVI+L7YHZI/odEpzwbNsDc6tv 067fwzX6/9m2BUF4j9bu+l2ajSgxT0WHb9xOm7XoRk2jP2RvN+eBgzW1+Ta26yO0 WMoGE/Hz6pWHu7IFwVRVeaI1V5A/zP0gugUsVOyKWBKZxLJ7qN3zA1+rZ1+g5j/O p6biZ3vqctJeq84e0hIWddAkGM/ApZrFZlnyjtJ9oG5A5a1k3hGnl/otMi2Ket8I G/O7HDnNjIgg7vEWNmq9A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvuedvvd egkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhiiigv pedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihgh horghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:27 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset Date: Fri, 27 Oct 2023 23:11:03 +0100 Message-Id: <20231027221106.405666-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Some BMIPS cpus has none standard start offset for vector interrupts. Handle those CPUs in vector size calculation and handler setup process. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ea59d321f713..651c9ec6265a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,7 +74,6 @@ #include "access-helper.h" -#define MAX(a, b) ((a) >= (b) ? (a) : (b)) extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) unsigned long ebase; EXPORT_SYMBOL_GPL(ebase); unsigned long exception_handlers[32]; +static unsigned long vi_vecbase; unsigned long vi_handlers[64]; void reserve_exception_space(phys_addr_t addr, unsigned long size) @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) handler = (unsigned long) addr; vi_handlers[n] = handler; - b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); + b = (unsigned char *)(vi_vecbase + n*VECTORSPACING); if (srs >= srssets) panic("Shadow register set %d not supported", srs); @@ -2370,20 +2370,33 @@ void __init trap_init(void) extern char except_vec3_generic; extern char except_vec4; extern char except_vec3_r4000; - unsigned long i, vec_size; + unsigned long i, vec_size, vi_vec_offset; phys_addr_t ebase_pa; check_wait(); + if (cpu_has_veic || cpu_has_vint) { + switch (current_cpu_type()) { + case CPU_BMIPS3300: + case CPU_BMIPS4380: + vi_vec_offset = 0x400; + break; + case CPU_BMIPS5000: + vi_vec_offset = 0x1000; + break; + default: + vi_vec_offset = 0x200; + break; + } + vec_size = vi_vec_offset + VECTORSPACING*64; + } else { + vec_size = 0x400; + } + if (!cpu_has_mips_r2_r6) { ebase = CAC_BASE; - vec_size = 0x400; } else { - if (cpu_has_veic || cpu_has_vint) - vec_size = 0x200 + VECTORSPACING*64; - else - vec_size = PAGE_SIZE; - + vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", @@ -2450,6 +2463,7 @@ void __init trap_init(void) * Initialise interrupt handlers */ if (cpu_has_veic || cpu_has_vint) { + vi_vecbase = ebase + vi_vec_offset; int nvec = cpu_has_veic ? 64 : 8; for (i = 0; i < nvec; i++) set_vi_handler(i, NULL); From patchwork Fri Oct 27 22:11:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43DF9C25B48 for ; Fri, 27 Oct 2023 22:12:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346696AbjJ0WMJ (ORCPT ); Fri, 27 Oct 2023 18:12:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346695AbjJ0WLv (ORCPT ); Fri, 27 Oct 2023 18:11:51 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D72FC10FD; Fri, 27 Oct 2023 15:11:33 -0700 (PDT) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.west.internal (Postfix) with ESMTP id 743653200930; Fri, 27 Oct 2023 18:11:31 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Fri, 27 Oct 2023 18:11:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444690; x= 1698531090; bh=GfLwAORI6DxI0P9SZsCprbtQo1SdXn/VrLRSxzuwQR4=; b=n YG6TLE93W20ZgxBA9/Dos/YhIY0YVVd8oVDdwWSEA7ZjYAJKv6+F741kEGJNM7cu gLwWSDNZ/UKNcv99cnU01CpJW0/xottYJIMzJsJ/oMAiQO/IwZvOEDu9xAryc10+ iqHtWEcvUMqMHVqXzWzDPT0GV7LsEJXUfs2vOnbd7vEL/Ys7H1Bcxz60b7SQqMcY P4yBl+plaV+y0dsckCzB9k4yeLxKuJ6GF9LkCFfQmIcpT590lDw4hZH+J8Pn4651 GdBxLFM634rAPCD2FSgTtyfpvpN6fjkZjGsZfGx/p53AfbGNZJzakSSr22Yw7GUL xp9JsD03HeTw3BYGOATyA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444690; x= 1698531090; bh=GfLwAORI6DxI0P9SZsCprbtQo1SdXn/VrLRSxzuwQR4=; b=M EdwpHWMA7reyomXBT6TJojaPnVxpChevCW3Gzk6MqX1OxezkX1jMWly9yaLymdao SNMVk7xMOeM/pYrmmg9Yxj+qARw6ahUn0wdYmuXhjD+ePukz2akoDWSoJONMNLo1 2kmQ9wClXRB91T8b8Mj4Al36SoEJRNJ3DKTr8ByWfcL6e5f4QMWNEm5UdQAycII1 urJ4c3Lx92LEMoLBSsVaCoThrhZeVwkpYf+kq5hmOsRK6LlfFf6Tf1ObAeBVZraC M0XkTy/90xAd/sXWRigBvXPDzPsB5fj7FJFGamBHc24PEAKqy0q8T1Fm6lK+UEju W+FX/O39Pfb50UkayReZA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeefledufeehgedvuedvvd egkefgvddttedtleeiiefhgeetudegkefhvdfhjeeftdenucevlhhushhtvghrufhiiigv peefnecurfgrrhgrmhepmhgrihhlfhhrohhmpehjihgrgihunhdrhigrnhhgsehflhihgh horghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:29 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 08/10] MIPS: Avoid unnecessary reservation of exception space Date: Fri, 27 Oct 2023 23:11:04 +0100 Message-Id: <20231027221106.405666-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Nowadays we allocate exception base from memblock for r2_r6, so we don't need to reverse exception space at the start of the memory for r2_r6 processors. For older processors the reservation is moved to traps_init where we have knowledge of exact size we need. We also add a sanity check to detect possible overlap with kernel. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/traps.h | 1 - arch/mips/kernel/cpu-probe.c | 5 ----- arch/mips/kernel/cpu-r3k-probe.c | 2 -- arch/mips/kernel/traps.c | 12 +++++++----- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 15cde638b407..d3dddd1c083a 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,7 +24,6 @@ extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); -extern void reserve_exception_space(phys_addr_t addr, unsigned long size); extern char except_vec_nmi[]; #define VECTORSPACING 0x100 /* for EI/VI mode */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b406d8bfb15a..54e8b0fd4a2a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1570,7 +1570,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_BMIPS3300; __cpu_name[cpu] = "Broadcom BMIPS3300"; set_elf_platform(cpu, "bmips3300"); - reserve_exception_space(0x400, VECTORSPACING * 64); break; case PRID_IMP_BMIPS43XX: { int rev = c->processor_id & PRID_REV_MASK; @@ -1581,7 +1580,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS4380"; set_elf_platform(cpu, "bmips4380"); c->options |= MIPS_CPU_RIXI; - reserve_exception_space(0x400, VECTORSPACING * 64); } else { c->cputype = CPU_BMIPS4350; __cpu_name[cpu] = "Broadcom BMIPS4350"; @@ -1598,7 +1596,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS5000"; set_elf_platform(cpu, "bmips5000"); c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; - reserve_exception_space(0x1000, VECTORSPACING * 64); break; } } @@ -1996,8 +1993,6 @@ void cpu_probe(void) if (cpu == 0) __ua_limit = ~((1ull << cpu_vmbits) - 1); #endif - - reserve_exception_space(0, 0x1000); } void cpu_report(void) diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c index be93469c0e0e..05410b743e57 100644 --- a/arch/mips/kernel/cpu-r3k-probe.c +++ b/arch/mips/kernel/cpu-r3k-probe.c @@ -137,8 +137,6 @@ void cpu_probe(void) cpu_set_fpu_opts(c); else cpu_set_nofpu_opts(c); - - reserve_exception_space(0, 0x400); } void cpu_report(void) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 651c9ec6265a..b6e94654f621 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2007,10 +2007,6 @@ unsigned long exception_handlers[32]; static unsigned long vi_vecbase; unsigned long vi_handlers[64]; -void reserve_exception_space(phys_addr_t addr, unsigned long size) -{ - memblock_reserve(addr, size); -} void __init *set_except_vector(int n, void *addr) { @@ -2394,7 +2390,13 @@ void __init trap_init(void) } if (!cpu_has_mips_r2_r6) { - ebase = CAC_BASE; + ebase_pa = 0x0; + ebase = CKSEG0ADDR(ebase_pa); + + if (__pa_symbol(_stext) < (ebase_pa + vec_size)) + pr_err("Insufficient space for exception vectors\n"); + + memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); From patchwork Fri Oct 27 22:11:05 2023 Content-Type: text/plain; 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Fri, 27 Oct 2023 18:11:32 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 09/10] MIPS: traps: Enhance memblock ebase allocation process Date: Fri, 27 Oct 2023 23:11:05 +0100 Message-Id: <20231027221106.405666-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org We try to allocate from KSEG0 accessible space first, and then if we really can't allocate any memory from KSEG0 and we are sure that we support ebase in higher segment, give it another go without restriction. This can maximize the possibility of having ebase in KSEG0. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b6e94654f621..68f1dd54cde1 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2399,7 +2399,12 @@ void __init trap_init(void) memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); - ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + ebase_pa = memblock_phys_alloc_range(vec_size, 1 << fls(vec_size), + 0x0, KSEGX_SIZE - 1); + + if (!ebase_pa && (IS_ENABLED(CONFIG_EVA) || cpu_has_ebase_wg)) + ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", __func__, vec_size, 1 << fls(vec_size)); From patchwork Fri Oct 27 22:11:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13439213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 602C5C25B47 for ; Fri, 27 Oct 2023 22:12:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346646AbjJ0WMU (ORCPT ); Fri, 27 Oct 2023 18:12:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346750AbjJ0WL7 (ORCPT ); Fri, 27 Oct 2023 18:11:59 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08E411734; Fri, 27 Oct 2023 15:11:37 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 4DD703200917; Fri, 27 Oct 2023 18:11:36 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 27 Oct 2023 18:11:36 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1698444695; x= 1698531095; bh=ovE6ErC2FU6MOXhQYQRXjYJQxqoUgfjvz+3gaCNVsfA=; b=u e7ck+5iPL0iPXFtIY+Ef4HQgt0qcg5TNXnQMH8qmACIoCZ4gpNBL0zSWPgifwCIF v7XubnvOnAkAtXObd6PkrAKFcbF8j3Xtpab7Mpovhdr6wyvOy/0W0+IGVH8iehZu pVNvVpPE8BJS6/2+sJatakKTNkqORtnSVHOITvwG841IuRRSY/hVwG7++U24EzFV cwXXJtkQU1+fdYPORtHrxBHUYrwERqpAYFNa2741pSFzr6yiSCoueykoRYVd+9PV NzOLhM2ysyD8w7jSD3vr8W92+Ge74s1U3Ux9mLOEHJ1cdr5Z5phSwEODbgln7Ank VBJFfbkpWEdiCAvU4D7OQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1698444695; x= 1698531095; bh=ovE6ErC2FU6MOXhQYQRXjYJQxqoUgfjvz+3gaCNVsfA=; b=E Yng0q4pCC6u+tC5gUP8F1ecIF+9/AxrER0glqDMx7YsQlmILMYXrn+x6XEBH+wkQ LlnHKkgD4YiQdGgdpPKqSJvoDnKBQK+aamyuSKeIdwNWJL5XUyC/FOqkut0ejlwY 7C7QPYd4+7VjWz7VWAeEfF42lmOz7wvWBhSZkUNynVGcK5pAiEh7wHlExw9lIomB yuThJy4mekqy7tIVBEdiQpAoull3mFh/j/l43QfsTXI2D5tjxF7Xoe0i3aO7axOd CZ2tTIaLi5z0xUt37gOg8n2LoYHsaOGEiBRgeEnhMXonBZiJsaIBTNUZQ5VNBhG8 BLo2J74hv38zDwlIyH6BA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvkedrleehgddtjecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvvefufffkofgjfhgggfestdekre dtredttdenucfhrhhomheplfhirgiguhhnucgjrghnghcuoehjihgrgihunhdrhigrnhhg sehflhihghhorghtrdgtohhmqeenucggtffrrghtthgvrhhnpeeufeefkeffveeuhfevke egheefjeelhfegvdelleeiveduvdevvdfhvdeuleegleenucffohhmrghinhephhgvrggu rdhssgenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpe hjihgrgihunhdrhigrnhhgsehflhihghhorghtrdgtohhm X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Oct 2023 18:11:34 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 10/10] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Date: Fri, 27 Oct 2023 23:11:06 +0100 Message-Id: <20231027221106.405666-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org NO_EXCEPT_FILL is used to indicate platform that does not need to reserve ebase memory at start of kernel. This is true for all R2+ platform as they allocate ebase memory on fly, and also true for any platform that does not load kernel at start of physical memory. Get rid this Kconfig symbol by use macro to detect conditions above. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 9 --------- arch/mips/kernel/head.S | 7 +++++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bfedc8b48a81..e928ebc2cd1f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -149,7 +149,6 @@ config MIPS_GENERIC_KERNEL select MIPS_CPU_SCACHE select MIPS_GIC select MIPS_L1_CACHE_SHIFT_7 - select NO_EXCEPT_FILL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE @@ -210,7 +209,6 @@ config AR7 select CEVT_R4K select CSRC_R4K select IRQ_MIPS_CPU - select NO_EXCEPT_FILL select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_EARLY_PRINTK @@ -265,7 +263,6 @@ config BMIPS_GENERIC select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL select BOOT_RAW - select NO_EXCEPT_FILL select USE_OF select CEVT_R4K select CSRC_R4K @@ -309,7 +306,6 @@ config BCM47XX select HAVE_PCI select IRQ_MIPS_CPU select SYS_HAS_CPU_MIPS32_R1 - select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MIPS16 @@ -445,7 +441,6 @@ config LANTIQ select IRQ_MIPS_CPU select CEVT_R4K select CSRC_R4K - select NO_EXCEPT_FILL select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN @@ -494,7 +489,6 @@ config MACH_LOONGSON64 select ISA select I8259 select IRQ_MIPS_CPU - select NO_EXCEPT_FILL select NR_CPUS_DEFAULT_64 select USE_GENERIC_EARLY_PRINTK_8250 select PCI_DRIVERS_GENERIC @@ -1177,9 +1171,6 @@ config PCI_GT64XXX_PCI0 config PCI_XTALK_BRIDGE bool -config NO_EXCEPT_FILL - bool - config MIPS_SPRAM bool diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index b825ed4476c7..4af53b1628f5 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -59,10 +59,13 @@ #endif .endm -#ifndef CONFIG_NO_EXCEPT_FILL +#if (MIPS_ISA_REV < 2) && \ + ((VMLINUX_LOAD_ADDRESS == KSEG0) || \ + (VMLINUX_LOAD_ADDRESS == CKSEG0)) /* * Reserved space for exception handlers. - * Necessary for machines which link their kernels at KSEG0. + * Necessary for machines which link their kernels at KSEG0 + * and incapable of moving ebase. */ .fill 0x400 #endif