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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:31 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 1/6] mtd: spi-nor: use kernel sized types instead of c99 types Date: Wed, 1 Nov 2023 11:43:20 +0200 Message-Id: <20231101094325.95851-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8738; i=tudor.ambarus@linaro.org; h=from:subject; bh=YuRCpKSiSJk/EOlzNGel/XPp8w1Cwhl7XINE3qqXZ9I=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh28CLWp1IHIWBQ3cwRLqn7MPaoNOajDH80EM kj7yykLg4aJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvAAKCRBLVU9HpY0U 6Y+KB/sEmGM2O+enoI4DA0KqiMgXdufVWO4BTosKi/zp+3aKxBa5MzvcrGEdyoK/khjdo3tGr35 5ih/L5xeRojzyzRWuvmEQ22gx6DnKfvgFjtVahw9HV1GlLwHrgA028v1pwyud/T4QCN8geR/0u0 wt7W0c8tJEAuRSMoFtGHDIUneXM+sfNGuuFW2EFBU+37/hqf4xAe/Hct/6ThCJ3g3fC2BJP8X6x MP6iXqHSpRcDGBvwKtSpkbo1kI9Tfq4QiSdI+9JAJtzZKuW6z5fqhjTqp/B1oDYmz9j+pMku3h7 Ekk8tZAia7N4Z3IslajH8V0wg3LQUd2z9UyHbBDJXL1BK+Ns X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024337_090330_85D3D445 X-CRM114-Status: GOOD ( 19.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The kernel offers and prefers the kernel sized types instead of the c99 types when not in the uapi directory, use them. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/atmel.c | 16 +++++++--------- drivers/mtd/spi-nor/core.c | 5 ++--- drivers/mtd/spi-nor/core.h | 6 +++--- drivers/mtd/spi-nor/sst.c | 6 +++--- drivers/mtd/spi-nor/swp.c | 25 ++++++++++++------------- 5 files changed, 27 insertions(+), 31 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index e13b8d2dd50a..45d1153a04a0 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -16,12 +16,12 @@ * is to unlock the whole flash array on startup. Therefore, we have to support * exactly this operation. */ -static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } -static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -37,7 +37,7 @@ static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) return ret; } -static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } @@ -69,7 +69,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = { * Return: 0 on success, -error otherwise. */ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs, - uint64_t len, bool is_protect) + u64 len, bool is_protect) { int ret; u8 sr; @@ -118,20 +118,18 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs, return spi_nor_write_sr(nor, nor->bouncebuf, 1); } -static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, - uint64_t len) +static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len) { return atmel_nor_set_global_protection(nor, ofs, len, true); } -static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, - uint64_t len) +static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len) { return atmel_nor_set_global_protection(nor, ofs, len, false); } static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs, - uint64_t len) + u64 len) { int ret; diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1c443fe568cf..25a64c65717d 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1799,8 +1799,7 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - u32 addr, len; - uint32_t rem; + u32 addr, len, rem; int ret; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -2146,7 +2145,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (is_power_of_2(page_size)) { page_offset = addr & (page_size - 1); } else { - uint64_t aux = addr; + u64 aux = addr; page_offset = do_div(aux, page_size); } diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 93cd2fc3606d..a456042379ee 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -293,9 +293,9 @@ struct spi_nor_erase_map { * @is_locked: check if a region of the SPI NOR is completely locked */ struct spi_nor_locking_ops { - int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); + int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len); + int (*unlock)(struct spi_nor *nor, loff_t ofs, u64 len); + int (*is_locked)(struct spi_nor *nor, loff_t ofs, u64 len); }; /** diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 44d2a546bf17..180b7390690c 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -13,12 +13,12 @@ #define SST26VF_CR_BPNV BIT(3) -static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } -static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -38,7 +38,7 @@ static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) return spi_nor_global_block_unlock(nor); } -static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 585813310ee1..e48c3cff247a 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -53,7 +53,7 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) } static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, - uint64_t *len) + u64 *len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -90,10 +90,10 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, * (if @locked is false); false otherwise. */ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, - uint64_t len, u8 sr, bool locked) + u64 len, u8 sr, bool locked) { loff_t lock_offs, lock_offs_max, offs_max; - uint64_t lock_len; + u64 lock_len; if (!len) return true; @@ -111,14 +111,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, return (ofs >= lock_offs_max) || (offs_max <= lock_offs); } -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, - u8 sr) +static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, u8 sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } -static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, - uint64_t len, u8 sr) +static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 len, + u8 sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } @@ -156,7 +155,7 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, * * Returns negative on errors, 0 on success. */ -static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -246,7 +245,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) * * Returns negative on errors, 0 on success. */ -static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -331,7 +330,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) * Returns 1 if entire region is locked, 0 if any portion is unlocked, and * negative on errors. */ -static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -353,7 +352,7 @@ void spi_nor_init_default_locking_ops(struct spi_nor *nor) nor->params->locking_ops = &spi_nor_sr_locking_ops; } -static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; @@ -368,7 +367,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return ret; } -static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; @@ -383,7 +382,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return ret; } -static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; From patchwork Wed Nov 1 09:43:21 2023 Content-Type: text/plain; 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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:32 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 2/6] mtd: spi-nor: add erase die (chip) capability Date: Wed, 1 Nov 2023 11:43:21 +0200 Message-Id: <20231101094325.95851-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5146; i=tudor.ambarus@linaro.org; h=from:subject; bh=Vdvn69AuH1lKrPLL0SQfY8OgpwWgJLdtiv1I6TtDpjQ=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh29T9f6MfbIADNw05TejWO4kITgxbmTLTwOd 8Lh2Al34EiJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6b+gB/9abmmSwFI+8tk2zdf9oQIrAQVQmfoW7m302eZEjKfn93VWLISHkFKnknxyZqpFSQdeuTy F7enEKpTGXoBjOgENvUPpg1USwEmPA2+X7omZO8lFNfmi+MAnCjtXeWcS5y4Rkn/aL837fH85GU IG5uGzCS1ILktc48N6y3b2K3xD0UKX+yftmo8qacJE1xjD1kaMjx/4sb4smJ7xMEDAaAzgMugU0 T7/wnHYKWkGDmwN2UPEZ53WhP5RdtB6rUfOSrugo/+vED1lMbIphVMj1rR+NzVBu1UoDRkjXa6F 9L4jzwxX7JQrURBLeAzQN/7HSIi/h/c0ULQXYTFTsorwUt// X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024337_414563_6BB54B42 X-CRM114-Status: GOOD ( 22.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org JESD216 defines a chip as a die, one and the other are the same thing. JESD216 clarifies that the chip erase time defined in BFPT dword(11) applies separately to each die for multi-die devices in which the dice are individually accessed. Based on this, update the spi_nor_erase_chip() method to support multi-die devices. For now, benefit of the die erase when addr and len are aligned with die size. This could be improved however for the uniform and non-uniform erases cases to use the die erase when possible. For example if one requests that an erase of a 2 die device starting from the last 64KB of the first die to the end of the flash size, we could use just 2 commands, a 64KB erase and a die erase. This improvement is left as an exercise for the reader, as I don't have multi die flashes at hand. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 22 +++++++++++++++++++--- drivers/mtd/spi-nor/core.h | 6 ++++-- drivers/mtd/spi-nor/debugfs.c | 2 +- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 25a64c65717d..360fce7ffe82 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1067,17 +1067,21 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) */ static int spi_nor_erase_chip(struct spi_nor *nor) { + u8 opcode = nor->params->chip_erase_opcode; int ret; dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); if (nor->spimem) { - struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP; + struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP(opcode); spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); ret = spi_mem_exec_op(nor->spimem, &op); } else { + if (opcode != SPINOR_OP_CHIP_ERASE) + return -EOPNOTSUPP; + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); @@ -1799,7 +1803,10 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); + u8 n_dice = nor->params->n_dice; + bool die_erase = false; u32 addr, len, rem; + size_t die_size; int ret; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -1814,12 +1821,18 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + if (n_dice) { + die_size = div_u64(mtd->size, n_dice); + if (len == die_size && (addr & (die_size - 1))) + die_erase = true; + } + ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); if (ret) return ret; - /* whole-chip erase? */ - if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { + /* chip (die) erase? */ + if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) || die_erase) { unsigned long timeout; ret = spi_nor_lock_device(nor); @@ -2902,6 +2915,9 @@ static int spi_nor_late_init_params(struct spi_nor *nor) return ret; } + if (nor->params->chip_erase_opcode) + nor->params->chip_erase_opcode = SPINOR_OP_CHIP_ERASE; + /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index a456042379ee..f681a139772f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -85,8 +85,8 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) -#define SPI_NOR_CHIP_ERASE_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), \ +#define SPI_NOR_CHIP_ERASE_OP(opcode) \ + SPI_MEM_OP(SPI_MEM_OP_CMD((opcode), 0), \ SPI_MEM_OP_NO_ADDR, \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) @@ -362,6 +362,7 @@ struct spi_nor_otp { * command in octal DTR mode. * @n_banks: number of banks. * @n_dice: number of dice in the flash memory. + * @chip_erase_opcode: chip (die) erase opcode. Shouldn't be set for single die devices. * @vreg_offset: volatile register offset for each die. * @hwcaps: describes the read and page program hardware * capabilities. @@ -399,6 +400,7 @@ struct spi_nor_flash_parameter { u8 rdsr_addr_nbytes; u8 n_banks; u8 n_dice; + u8 chip_erase_opcode; u32 *vreg_offset; struct spi_nor_hwcaps hwcaps; diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 6e163cb5b478..f242a18e46fc 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -138,7 +138,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data) if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf)); - seq_printf(s, " %02x (%s)\n", SPINOR_OP_CHIP_ERASE, buf); + seq_printf(s, " %02x (%s)\n", nor->params->chip_erase_opcode, buf); } seq_puts(s, "\nsector map\n"); From patchwork Wed Nov 1 09:43:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98F1DC4167D for ; Wed, 1 Nov 2023 09:44:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M2bByq7MUVttTOiCJURnmfWJ+CPgB9VTXJ5xlHSogwA=; b=Z7CtY3QcOEig/9 N7uCs6nF4er/XGNy3TiUSQmVo6Ilqvw/wLn7nr6sRuccFhMUGWqEjo9W7DAFp4zB8o0wDfO0rUK/e fqQADgoi4R6wK2tGRLJ3EgWN2TGcT1oqvPKsVBxwA+ewRs6sYG50RAMz3V5wSH8P6PSaZ0AdY6cKr Kf339utRNow5GRW6XDk/Z8VR4MP2ynEfC4FYwTbCRO4ATejqzEb+zkahKKHzZDcXvb2TNlmDnwhWO 8K+zj6+m6bM1ihQuqrhhsxpFl5UAS677kHRTDuvxGdjX/tlv2WJi9I2KNV1jr5aZcxWUd8X5qeC80 blhxWOOpoLHNscWcnI+g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qy7lL-006yDJ-1P; Wed, 01 Nov 2023 09:43:47 +0000 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qy7lC-006y7J-13 for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 09:43:45 +0000 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-9c773ac9b15so980464266b.2 for ; Wed, 01 Nov 2023 02:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698831814; x=1699436614; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=maW71W19w3xZ4uRCg1NKsmw29lE5F0o2RqhV9nKvSw8=; b=sSWHgjVZRAItsRk2r0lqvRgsLpPYWd79gZpgpa/L5QabEk4TiiVHrx0bJM26Cmxwbi 1vF7efeZEE+JZyM5a5/62QxF9YFcTitCqaLtUD+RfNIVvqXStYhuQRkl2KG4wo9ZOwpK MaoSC4nxnsrwzHKjqCeHOBLjb9qbcMxHosVxANyR+NckQNtyeQOgA/Hk258K+qlBuIb0 A3toLjOSelGwCCbyay7/kNSR4l4MF8T4ES01c+Kb+8ZeUn9uFWY8vsZfpeiRYjNDQN27 LL6hHZgMSeuIXba3BRFp/cgTUSt5xBJ/1/FgznZPCKQVyz8wdNaJD6dy/TkPxOORMSGM k38Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698831814; x=1699436614; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=maW71W19w3xZ4uRCg1NKsmw29lE5F0o2RqhV9nKvSw8=; b=Zb6LszixgqVIxA+Ctnb2mZ0oBSz6WS5WuYbmCMP84nufWInPIGCzwu/CVFiVy/ypPf LQ5ciwXQbab3z/l4PPHYLK+fllPxRaHVssUcMo2s9AivQBhrdtlaalicJgTEYQtWfWCy LIlIcqLgKYQ7hRMToFwJV2+wALhpcWng04rpSDZhz2o6Q2FV89furOeRD2ht54kAfrmV ksfI5sLE2ZUU6f4PBv9mnWlGmEPe7dODTfQtw4pxGrgC9ML7rEcG2kpghzJsHw3DPSP+ ZWPBvhIl51EbvHMyRG3+gs2s2E7VcDsio3Pj+VlF38PohC5xd4Fa1GMbl66gz/csck1V S2yQ== X-Gm-Message-State: AOJu0Yw6tc7oV2DMSuKLnKsh010Ct1PTV1P3+dAzWAdmMqaf2UDL+y31 X8TY/EAMldMgv66IF1WksU5xRp50XCnFMYT0gEM= X-Google-Smtp-Source: AGHT+IFs5FigSHxj/VtvU7igiUS4RhgAVrcRqjd/9bdAqr2gmAZbvn8NIaLBvkVnX2Y4/eTCo3HMGg== X-Received: by 2002:a17:906:bc93:b0:9bd:bbc1:1c5f with SMTP id lv19-20020a170906bc9300b009bdbbc11c5fmr1230099ejb.35.1698831814515; Wed, 01 Nov 2023 02:43:34 -0700 (PDT) Received: from 1.. ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:34 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 3/6] mtd: spi-nor: spansion: enable die erase for multi die flashes Date: Wed, 1 Nov 2023 11:43:22 +0200 Message-Id: <20231101094325.95851-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1641; i=tudor.ambarus@linaro.org; h=from:subject; bh=ksJwE4YNAWP5lDJN39g2w4IJ+ATJr3tJ8N06/D7QgCo=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh29x0fHhXSE9JgafvLMA7XLeUNqtp8nSiGwM MWM5Xo2miKJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6S5/B/0Tb8vjNOpLBZJsjrfnZCUiwUvh4rGCxYaCrSoWEjeQpJvYpWilXERjy6NuNK3bmbH8y2y oERzO4TcCKCMRXSzteea1uskFLfzcdPfHJMsCh4UXH1RSNN4aIWKueDILtA8zsAnHfQt+j2WZKA TueCERkx93HOy2zLVasdBNIsddcM4IzY3Ujr9K0bdSrPUzan4EObuZn2yMjdjoLV5KJRkm/BV86 BZAA+gzZ1WNh2JomKxOC34g++wASRsv4rOXfbFg6mLpElKhIZVwZSvROBMO6bEza3XXPd9ydAfM nuJVh+hiNIJpbkXAfXFdhfsnBNxVYMSvr69lucnF+l0DF4KV X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024338_369227_3CC31804 X-CRM114-Status: GOOD ( 14.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable die erase for spansion multi die flashes. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 12921344373d..1c052786127a 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -17,6 +17,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ +#define SPINOR_OP_CYPRESS_CHIP_ERASE 0x61 /* Chip (die) erase */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -644,6 +645,7 @@ static int s25hx_t_late_init(struct spi_nor *nor) params->ready = cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); + params->chip_erase_opcode = SPINOR_OP_CYPRESS_CHIP_ERASE; return 0; } @@ -933,7 +935,6 @@ static const struct flash_info spansion_nor_parts[] = { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .name = "s25hl02gt", .mfr_flags = USE_CLPEF, - .flags = NO_CHIP_ERASE, .fixups = &s25hx_t_fixups }, { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), @@ -954,7 +955,6 @@ static const struct flash_info spansion_nor_parts[] = { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .name = "s25hs02gt", .mfr_flags = USE_CLPEF, - .flags = NO_CHIP_ERASE, .fixups = &s25hx_t_fixups }, { .id = SNOR_ID(0x34, 0x5a, 0x1a), From patchwork Wed Nov 1 09:43:23 2023 Content-Type: text/plain; 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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:35 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 4/6] mtd: spi-nor: micron-st: use die erase for multi die flashes Date: Wed, 1 Nov 2023 11:43:23 +0200 Message-Id: <20231101094325.95851-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3051; i=tudor.ambarus@linaro.org; h=from:subject; bh=nA2hD+SgRKNyNEk1b0eo3VQFtRBch3W6/UtFaLLl7Dk=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh29+HnAKoB0wCdAIwSEV4jXgOMA9RgPy/RN0 Vr9cMJEYjqJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6eAHB/4/gNKfdAmpU16jjxCn/YJicoFIflbEl40LyKX8S3HfKcm1tvZHbOX2T6y6xdWPPbZCG1H OXG3w6RRcCwVa9OzPwF1BRTa0vv0Ll7nYc3WkQRdmxtIdl0mZ+qTnejPLg0Lnv5l9g1AoJCRbGj qeuDSPgow+8+5zuwT9bun7gtJBrrjsll2Z0P4XqDmy1478kt8w9qFmwAlDp0CaZl06uXIjliEJZ G8xcrPchM60swftI0GUkVgdh6AkhJsgctZTQOalc0jif/7SFAX0EvqjbhCuImJPMGScazOSHwWF l1cuW2I7ESzIl7RoTX0qJJyX/1JHFJWH8bCsjcFFiNKoOeJ+ X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024338_963850_0AB546B7 X-CRM114-Status: GOOD ( 14.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use die erase for multi die flashes, it will speed the erase time. Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_1gb_3v_65nm.pdf?rev=b6eba74759984f749f8c039bc5bc47b7 Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf?rev=43f7f66fc8da4d7d901b35fa51284c8f Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 8920547c12bf..8706ef841375 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -11,6 +11,7 @@ /* flash_info mfr_flag. Used to read proprietary FSR register. */ #define USE_FSR BIT(0) +#define SPINOR_OP_MT_CHIP_ERASE 0xc4 /* Chip (die) erase opcode */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ @@ -192,6 +193,24 @@ static struct spi_nor_fixups mt25qu512a_fixups = { .post_bfpt = mt25qu512a_post_bfpt_fixup, }; +static int st_nor_four_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->chip_erase_opcode = SPINOR_OP_MT_CHIP_ERASE; + params->n_dice = 4; + + return 0; +} + +static struct spi_nor_fixups n25q00_fixups = { + .late_init = st_nor_four_die_late_init, +}; + +static struct spi_nor_fixups mt25q02_fixups = { + .late_init = st_nor_four_die_late_init, +}; + static const struct flash_info st_nor_parts[] = { { .name = "m25p05-nonjedec", @@ -366,16 +385,17 @@ static const struct flash_info st_nor_parts[] = { .name = "n25q00", .size = SZ_128M, .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE, + SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &n25q00_fixups, }, { .id = SNOR_ID(0x20, 0xba, 0x22), .name = "mt25ql02g", .size = SZ_256M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &mt25q02_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x15), .name = "n25q016a", @@ -433,16 +453,16 @@ static const struct flash_info st_nor_parts[] = { .id = SNOR_ID(0x20, 0xbb, 0x21), .name = "n25q00a", .size = SZ_128M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &n25q00_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x22), .name = "mt25qu02g", .size = SZ_256M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &mt25q02_fixups, } }; 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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:37 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 5/6] mtd: spi-nor: remove NO_CHIP_ERASE flag Date: Wed, 1 Nov 2023 11:43:24 +0200 Message-Id: <20231101094325.95851-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1896; i=tudor.ambarus@linaro.org; h=from:subject; bh=qodvSZkEdT/igPH1EKd80cKPj1l48lT2Qmj2i6tTMmA=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh297pYvrWy0+J/XmGtkqJPAYiJOikqbF8ux0 v76yx1hSdWJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6cqOB/4z7qYxEy4qgfj3OB5uYfKpxaXci8KkLPIv8SXh8MBTaeIQcqrhHfcQAx4L2STdEPIt6rv j6Kw0HI8qJZUKNyJVKoljSkhMxdhgypg9+9CTa5uQgqpl51xrligCV81y67MqV8qKrk5Xex7yWO h21H2PhNAuHpufFxU90FoT3sPsAXtaNfdML3zEAJHvmMLFBBgJtYWd7c3bkxPI9un0yJXozBraT KXSuH+e6OgVf3n/QEjFZROVuwWs4gjRZULyvJXWFzeqIjNfTzSmj8j4H9d9djzSeBalkXef+/tP gTTOLUtreXgu6KE4MWUsJlNEMiqYLOhHEqw2TaM1sBI15siU X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024340_305090_41847CBD X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 8 +++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 360fce7ffe82..b9829a1ed192 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2862,9 +2862,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; } - if (flags & NO_CHIP_ERASE) - nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; - if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |= SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index f681a139772f..65207c83b751 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,7 +489,6 @@ struct spi_nor_id { * Usually these will power-up in a write-protected * state. * SPI_NOR_NO_ERASE: no erase command needed. - * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. @@ -539,10 +538,9 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define NO_CHIP_ERASE BIT(7) -#define SPI_NOR_NO_FR BIT(8) -#define SPI_NOR_QUAD_PP BIT(9) -#define SPI_NOR_RWW BIT(10) +#define SPI_NOR_NO_FR BIT(7) +#define SPI_NOR_QUAD_PP BIT(8) +#define SPI_NOR_RWW BIT(9) u8 no_sfdp_flags; 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([79.115.63.76]) by smtp.gmail.com with ESMTPSA id gq23-20020a170906e25700b0099e12a49c8fsm2206415ejb.173.2023.11.01.02.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 02:43:38 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: miquel.raynal@bootlin.com, richard@nod.at, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, Tudor Ambarus Subject: [PATCH 6/6] mtd: spi-nor: micron-st: Add support for mt25qu01g Date: Wed, 1 Nov 2023 11:43:25 +0200 Message-Id: <20231101094325.95851-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231101094325.95851-1-tudor.ambarus@linaro.org> References: <20231101094325.95851-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2847; i=tudor.ambarus@linaro.org; h=from:subject; bh=FN95MDStU0W7lUTO984uRiZPl3auH/CwE9nBkCd1f7s=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlQh29Tu73VMwCQWa+iaS8s1otBhT4eRYpvt5uW 8pnLMmay6qJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZUIdvQAKCRBLVU9HpY0U 6bJgB/9aae6lW7+7fwmO4f4dKxTFCYVv1Ng+WuqbR/MGbOH9XNls7JQIALP02AXbq9waFwyRn0O Gqjua1QcLfXptTip1ychKMMCHmrNTQuz3iQXeyc6iChNIyA666ZxSTr1TKJhsCYsNthoxl2KOkq XLFgYqj3FGVgh/rw/n/RGmHaSoPBpG4ubtNwrHuAyn3oqan3n5Xf8JJJQbJQSDFvUABt7ShNjuC bnfZfyCrgt4OfqxjK0GsCSIweU3oWnLFNVIC/0hHXkaHLcDtpq07Dzl45FofjxBHh9b4vFI0kB4 BFX56yds7XpnFMq3KvnQAW/19e//+iJxivANgSocxILTXXPB X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_024340_033413_762DE3D8 X-CRM114-Status: GOOD ( 12.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Fabio Estevam Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory model. Datasheet: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf Tested on a i.MX8MP based board: # dmesg | grep spi-nor spi-nor spi0.0: mt25qu01g (131072 Kbytes) # cat /proc/mtd dev: size erasesize name mtd0: 08000000 00001000 "30bb0000.spi" ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id 20bb21104400 ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer st ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/partname mt25qu01g ~# xxd -p /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 53464450060101ff00060110300000ff84000102800000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e 03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff ffffffffffffffffffe7ffff21dcffff ~# md5sum /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 9d28d1b11de8b15ba9152644219d9a78 /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp Signed-off-by: Fabio Estevam [ta: introduce die erase] Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 8706ef841375..6d8dd6bfbf69 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -203,10 +203,24 @@ static int st_nor_four_die_late_init(struct spi_nor *nor) return 0; } +static int st_nor_two_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->chip_erase_opcode = SPINOR_OP_MT_CHIP_ERASE; + params->n_dice = 2; + + return 0; +} + static struct spi_nor_fixups n25q00_fixups = { .late_init = st_nor_four_die_late_init, }; +static struct spi_nor_fixups mt25q01_fixups = { + .late_init = st_nor_two_die_late_init, +}; + static struct spi_nor_fixups mt25q02_fixups = { .late_init = st_nor_four_die_late_init, }; @@ -449,6 +463,11 @@ static const struct flash_info st_nor_parts[] = { SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + }, { + .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), + .name = "mt25qu01g", + .mfr_flags = USE_FSR, + .fixups = &mt25q01_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x21), .name = "n25q00a",