From patchwork Wed Nov 1 14:58:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91664C4332F for ; Wed, 1 Nov 2023 14:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qyVgV6BGods/5B8xU39XOWLLqY9I7Uh0QeMLvGu7AXQ=; b=wBfABM9cylNVFx hHYTV3oc7LONmjKBhf9F3ae4ZPaljqY9n5ZFIxTtJ6YN1+SIodkVhETepHhTrl/NBo7xEXQyBb+r0 zly7LrzVq+1tL2EgnhQPWgaKNPY/Fy3OQPV/05dKQ3mfdC3G4uo2ZoxZPquPp6u0gNNyRew1e2APu +DdfoPwTFfY2gFZlTt/PczG5uKSaF3BCPHRN22WdHI3Btm1j5IihX2g6F046FY3MpqlWdPGCER5+N 9ULBCqnXC4hAXAAjYfbVrizoiBs3pT5swrEUm/hyLNvDaODwLi65bvdbUoTolxxZWNgOyuntmsJpO 0ZVC7WINaBFjGdKUDXbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCge-007gjw-03; Wed, 01 Nov 2023 14:59:16 +0000 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgR-007gd5-2w for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:11 +0000 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-9a6190af24aso1064146266b.0 for ; Wed, 01 Nov 2023 07:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850739; x=1699455539; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ftD45+94BE7lGnnuN8b0M61zwN6yhXdQsDaemRaqwM4=; b=nNPNoCvgzZN0XbYu9/1jtqakNqQw0PHvkpG0ekTF54EMjKJHiVzCIliby7OwVJg340 QVzf+CbHH+wlzsbrNtENMc/S21T0zxp2ctIWbFAZItMGW5t8yjE2DKQ3lEk7fB1z36Qz 5ak213x17jtTHp7Dwag9t2hVXIZqd6QyJM6lvwlu8NOOQXcF2Fccw6RUgwktykAY+GBk 52io2XAKkVDmUmhb8okhAhP1XJTzWQOAKinPdy089vXI1Gk0aSl0mLfs3jep6sWaoaiC 66TXtauhPsnTo2MVEVJkliYM6rxQ4ORqK5RTN/IReBgef5qNuB4SJKzOG9TV2p8HfrVy 1VSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850739; x=1699455539; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ftD45+94BE7lGnnuN8b0M61zwN6yhXdQsDaemRaqwM4=; b=pkpp8EJebLeRqLcxBBEB/U8hlYuM7QQeN+Le8hFVEUjH7O5vUhR8gzIpKWz14C2+Pj UshXnM7vt2zTVEUKs0ge5QCJps7a/XzHnBC1NOMiS8qJXnDoKJbZPcCg8bxbpNPLZqfx /YWox4QPxO+o7O8+0rrVGLeoFILuUx+si8/ZyS35DGfgSM7Nj5z/NTyFwi7PwC7murbb EP319xRRxYZfM3E10S1XWj8/rCa7xmcnYnjqK6r9G5yzraSgc3iIyK6MRxW89mp73gjH P8pOFV0HJ+mzLJUQiPjjHnVpxFhWG5LFNMTm9y0nRK0J/pQfnZvpUVgzixF3MIMXi+8W 6ACg== X-Gm-Message-State: AOJu0YzRfqWzNu2JLZchBKafaYKsTk2ZK7dLt9ffgDfdYBvlFrGsDmgO c/dzme3cDpifKBcd/ef/sF7Eeg== X-Google-Smtp-Source: AGHT+IF6oznjB9sjYq+mm/3VckJ2AhbXYtNHqWTUI31WItTpPA0dINfCOkgnCLucoMuKRjaAdk/bRA== X-Received: by 2002:a17:907:3181:b0:9bf:b5bc:6c4b with SMTP id xe1-20020a170907318100b009bfb5bc6c4bmr2444624ejb.62.1698850739253; Wed, 01 Nov 2023 07:58:59 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:58:58 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 1/6] mtd: spi-nor: use kernel sized types instead of c99 types Date: Wed, 1 Nov 2023 14:58:48 +0000 Message-ID: <20231101145853.524045-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075904_004413_A07915A9 X-CRM114-Status: GOOD ( 19.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The kernel offers and prefers the kernel sized types instead of the c99 types when not in the uapi directory, use them. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/atmel.c | 16 +++++++--------- drivers/mtd/spi-nor/core.c | 5 ++--- drivers/mtd/spi-nor/core.h | 6 +++--- drivers/mtd/spi-nor/sst.c | 6 +++--- drivers/mtd/spi-nor/swp.c | 25 ++++++++++++------------- 5 files changed, 27 insertions(+), 31 deletions(-) diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index e13b8d2dd50a..45d1153a04a0 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -16,12 +16,12 @@ * is to unlock the whole flash array on startup. Therefore, we have to support * exactly this operation. */ -static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } -static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -37,7 +37,7 @@ static int at25fs_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) return ret; } -static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int at25fs_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } @@ -69,7 +69,7 @@ static const struct spi_nor_fixups at25fs_nor_fixups = { * Return: 0 on success, -error otherwise. */ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs, - uint64_t len, bool is_protect) + u64 len, bool is_protect) { int ret; u8 sr; @@ -118,20 +118,18 @@ static int atmel_nor_set_global_protection(struct spi_nor *nor, loff_t ofs, return spi_nor_write_sr(nor, nor->bouncebuf, 1); } -static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, - uint64_t len) +static int atmel_nor_global_protect(struct spi_nor *nor, loff_t ofs, u64 len) { return atmel_nor_set_global_protection(nor, ofs, len, true); } -static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, - uint64_t len) +static int atmel_nor_global_unprotect(struct spi_nor *nor, loff_t ofs, u64 len) { return atmel_nor_set_global_protection(nor, ofs, len, false); } static int atmel_nor_is_global_protected(struct spi_nor *nor, loff_t ofs, - uint64_t len) + u64 len) { int ret; diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 1c443fe568cf..25a64c65717d 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1799,8 +1799,7 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); - u32 addr, len; - uint32_t rem; + u32 addr, len, rem; int ret; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -2146,7 +2145,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, if (is_power_of_2(page_size)) { page_offset = addr & (page_size - 1); } else { - uint64_t aux = addr; + u64 aux = addr; page_offset = do_div(aux, page_size); } diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 93cd2fc3606d..a456042379ee 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -293,9 +293,9 @@ struct spi_nor_erase_map { * @is_locked: check if a region of the SPI NOR is completely locked */ struct spi_nor_locking_ops { - int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len); - int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); + int (*lock)(struct spi_nor *nor, loff_t ofs, u64 len); + int (*unlock)(struct spi_nor *nor, loff_t ofs, u64 len); + int (*is_locked)(struct spi_nor *nor, loff_t ofs, u64 len); }; /** diff --git a/drivers/mtd/spi-nor/sst.c b/drivers/mtd/spi-nor/sst.c index 44d2a546bf17..180b7390690c 100644 --- a/drivers/mtd/spi-nor/sst.c +++ b/drivers/mtd/spi-nor/sst.c @@ -13,12 +13,12 @@ #define SST26VF_CR_BPNV BIT(3) -static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_lock(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } -static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -38,7 +38,7 @@ static int sst26vf_nor_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) return spi_nor_global_block_unlock(nor); } -static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int sst26vf_nor_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { return -EOPNOTSUPP; } diff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c index 585813310ee1..e48c3cff247a 100644 --- a/drivers/mtd/spi-nor/swp.c +++ b/drivers/mtd/spi-nor/swp.c @@ -53,7 +53,7 @@ static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor) } static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, - uint64_t *len) + u64 *len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -90,10 +90,10 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, * (if @locked is false); false otherwise. */ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, - uint64_t len, u8 sr, bool locked) + u64 len, u8 sr, bool locked) { loff_t lock_offs, lock_offs_max, offs_max; - uint64_t lock_len; + u64 lock_len; if (!len) return true; @@ -111,14 +111,13 @@ static bool spi_nor_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, return (ofs >= lock_offs_max) || (offs_max <= lock_offs); } -static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, - u8 sr) +static bool spi_nor_is_locked_sr(struct spi_nor *nor, loff_t ofs, u64 len, u8 sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, true); } -static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, - uint64_t len, u8 sr) +static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, u64 len, + u8 sr) { return spi_nor_check_lock_status_sr(nor, ofs, len, sr, false); } @@ -156,7 +155,7 @@ static bool spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, * * Returns negative on errors, 0 on success. */ -static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -246,7 +245,7 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) * * Returns negative on errors, 0 on success. */ -static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len) { struct mtd_info *mtd = &nor->mtd; u64 min_prot_len; @@ -331,7 +330,7 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) * Returns 1 if entire region is locked, 0 if any portion is unlocked, and * negative on errors. */ -static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len) { int ret; @@ -353,7 +352,7 @@ void spi_nor_init_default_locking_ops(struct spi_nor *nor) nor->params->locking_ops = &spi_nor_sr_locking_ops; } -static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; @@ -368,7 +367,7 @@ static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return ret; } -static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; @@ -383,7 +382,7 @@ static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) return ret; } -static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) +static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, u64 len) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; From patchwork Wed Nov 1 14:58:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 691A6C4167D for ; Wed, 1 Nov 2023 14:59:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5H18pqH5DlKZZuNxDaWLNVllNl+oESYwuPXklW/arJ4=; b=i3JI/G/e0Uiapb RLQMqrnNCmG+BxUpuhSFE/FI5NC5Uwkc2c4NXBTXF+a3IRxLcUxwDzl8i6cuLPc9JqllAoG8toZth s2EuD4bgBdfoRcv4cniOWuFgL+iRvWIeVqr+0nOooA+OM4yhs9CzL/xGSCBQcZeekuKXv2rqqh0qB b+m8U0JftlYJ3qlxaGepT8lSTgNzFFisHTHLM4gaFgZbcvSn2YlKwjAQ1AUfJdS6kjNJu8ZTUexC9 jz4FFgnL/3v/wnuzPVd5Uc2z3XCIqCnIQRwVh+6b3Wyq7dcVPf9pi+6Vq495CMwEJGFeMj7jp7vNa 3Qk9V2UvZPjcD1sqzLAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgX-007ggZ-03; Wed, 01 Nov 2023 14:59:09 +0000 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgR-007gdG-2g for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:07 +0000 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-53de8fc1ad8so11399998a12.0 for ; Wed, 01 Nov 2023 07:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850741; x=1699455541; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q4tJ4GOKVAMYiRqtkpPxgpMnp8wqfNy+IrCACp9J/W0=; b=CP5V/TZGTMYhltsT7fLlAxRpfSlXTckHx65rR/NOvMT6HEkqG7F2dPZMz6+psDOb3p Sazn2RiQ5GMoi7JIK4oYU2fA0QgsiVihyUthgC3U2iBB5FQVPYWXfIHcUOsDNUCTCNKC z2+9Q5VggC8hUo/sEBJYydhPf2z8sGbmnac/Sa4spUl6yWtfMT1lzShz3bSwcWN8v1vF 2hV9r6UzhzG1YWMBDQUNyoubgEp/8zmYNxgtcii9aRkFJ/lGFMgpNJisZspbBLycZsWU Wo2FxJg80Ivlh4dInGAe4jRWVR5NSCj8+hTyk6n38l9xHbYejtHf2DLtOIWi7Pkr0hfQ eA3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850741; x=1699455541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q4tJ4GOKVAMYiRqtkpPxgpMnp8wqfNy+IrCACp9J/W0=; b=MOo6vtrqJzAdUE9XyyvBogXLB0vPOeVFK4GhcJ/vEoI/QlrkfwAHVXoTH05Z+yoJ0f Pfhz8nh7S2Xg/GweW1blxUnsivcdMieIlvVuk4SPNKI415J8C8efW1sYMihIzHAp1OBT krtMkhBKcRIRVTEk6RXePxKZ3i+4MKHlFzBrZU/cDY99sKhaoZA9gckYR+f1d+7gKGoT sEH0LHdyxUZpfdnhPjoAuJyAUaj7DxGOhh3RHbRXLgyr0DTrQTrZl1hccng5ZJyyRZbb ll1Yc/UpcHmdBFXsBsPyi5jiklfZucg+Yh4B0Ame0Bx9D0hymumuQNZ60Mp/vnRsymoJ duSg== X-Gm-Message-State: AOJu0YyYCeiHgaY/3HVvthKXjADCkcIzqSlhV6PNvm/VF8ei/Tii9VHi 2L/j+S8bRwezOfLUkH/8zW1sBstNg7xn8xJm6JA= X-Google-Smtp-Source: AGHT+IH/8gsOuXf6sYmJYsmU54xjggL87VxdM5USH1Sap1Lr2Wch+iERnHSu6OWTllRrz12qntgw9A== X-Received: by 2002:a17:906:db0d:b0:9d3:ccd1:a922 with SMTP id xj13-20020a170906db0d00b009d3ccd1a922mr2114912ejb.58.1698850740759; Wed, 01 Nov 2023 07:59:00 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:59:00 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 2/6] mtd: spi-nor: add erase die (chip) capability Date: Wed, 1 Nov 2023 14:58:49 +0000 Message-ID: <20231101145853.524045-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075903_870224_E465E285 X-CRM114-Status: GOOD ( 26.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org JESD216 defines a chip as a die, one and the other are the same thing. JESD216 clarifies that the chip erase time defined in BFPT dword(11) applies separately to each die for multi-die devices in which the dice are individually accessed. Based on this, update the spi_nor_erase_chip() method to support multi-die devices. For now, benefit of the die erase when addr and len are aligned with die size. This could be improved however for the uniform and non-uniform erases cases to use the die erase when possible. For example if one requests that an erase of a 2 die device starting from the last 64KB of the first die to the end of the flash size, we could use just 2 commands, a 64KB erase and a die erase. This improvement is left as an exercise for the reader, as I don't have multi die flashes at hand. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 104 +++++++++++++++++++++++----------- drivers/mtd/spi-nor/core.h | 8 ++- drivers/mtd/spi-nor/debugfs.c | 2 +- 3 files changed, 78 insertions(+), 36 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 25a64c65717d..ac2651e76285 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1065,19 +1065,25 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_erase_chip(struct spi_nor *nor) +static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size) { + bool multi_die = nor->mtd.size == die_size; int ret; - dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); + dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10)); if (nor->spimem) { - struct spi_mem_op op = SPI_NOR_CHIP_ERASE_OP; + struct spi_mem_op op = + SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode, + nor->addr_nbytes, addr, multi_die); spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); ret = spi_mem_exec_op(nor->spimem, &op); } else { + if (multi_die) + return -EOPNOTSUPP; + ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); @@ -1792,6 +1798,51 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) return ret; } +static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr, + size_t len, size_t die_size) +{ + unsigned long timeout; + int ret; + + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(nor->mtd.size / SZ_2M)); + + do { + ret = spi_nor_lock_device(nor); + if (ret) + return ret; + + ret = spi_nor_write_enable(nor); + if (ret) { + spi_nor_unlock_device(nor); + return ret; + } + + ret = spi_nor_erase_die(nor, addr, die_size); + + spi_nor_unlock_device(nor); + if (ret) + return ret; + + ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); + if (ret) + return ret; + + addr += die_size; + len -= die_size; + + } while (len); + + return 0; +} + /* * Erase an address range on the nor chip. The address range may extend * one or more erase sectors. Return an error if there is a problem erasing. @@ -1799,7 +1850,10 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor = mtd_to_spi_nor(mtd); + u8 n_dice = nor->params->n_dice; + bool multi_die_erase = false; u32 addr, len, rem; + size_t die_size; int ret; dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -1814,39 +1868,22 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) addr = instr->addr; len = instr->len; + if (n_dice) { + die_size = div_u64(mtd->size, n_dice); + if (len == die_size && (addr & (die_size - 1))) + multi_die_erase = true; + } else { + die_size = mtd->size; + } + ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); if (ret) return ret; - /* whole-chip erase? */ - if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { - unsigned long timeout; - - ret = spi_nor_lock_device(nor); - if (ret) - goto erase_err; - - ret = spi_nor_write_enable(nor); - if (ret) { - spi_nor_unlock_device(nor); - goto erase_err; - } - - ret = spi_nor_erase_chip(nor); - spi_nor_unlock_device(nor); - if (ret) - goto erase_err; - - /* - * Scale the timeout linearly with the size of the flash, with - * a minimum calibrated to an old 2MB flash. We could try to - * pull these from CFI/SFDP, but these values should be good - * enough for now. - */ - timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, - CHIP_ERASE_2MB_READY_WAIT_JIFFIES * - (unsigned long)(mtd->size / SZ_2M)); - ret = spi_nor_wait_till_ready_with_timeout(nor, timeout); + /* chip (die) erase? */ + if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) || + multi_die_erase) { + ret = spi_nor_erase_dice(nor, addr, len, die_size); if (ret) goto erase_err; @@ -2902,6 +2939,9 @@ static int spi_nor_late_init_params(struct spi_nor *nor) return ret; } + if (!nor->params->die_erase_opcode) + nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE; + /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index a456042379ee..b43ea2d49e74 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -85,9 +85,9 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) -#define SPI_NOR_CHIP_ERASE_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), \ - SPI_MEM_OP_NO_ADDR, \ +#define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) @@ -362,6 +362,7 @@ struct spi_nor_otp { * command in octal DTR mode. * @n_banks: number of banks. * @n_dice: number of dice in the flash memory. + * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE. * @vreg_offset: volatile register offset for each die. * @hwcaps: describes the read and page program hardware * capabilities. @@ -399,6 +400,7 @@ struct spi_nor_flash_parameter { u8 rdsr_addr_nbytes; u8 n_banks; u8 n_dice; + u8 die_erase_opcode; u32 *vreg_offset; struct spi_nor_hwcaps hwcaps; diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 6e163cb5b478..2dbda6b6938a 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -138,7 +138,7 @@ static int spi_nor_params_show(struct seq_file *s, void *data) if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf)); - seq_printf(s, " %02x (%s)\n", SPINOR_OP_CHIP_ERASE, buf); + seq_printf(s, " %02x (%s)\n", nor->params->die_erase_opcode, buf); } seq_puts(s, "\nsector map\n"); From patchwork Wed Nov 1 14:58:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442857 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA791C0018A for ; Wed, 1 Nov 2023 14:59:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1mT8ADvbSepmei6oEyNEEQiZN3EAyhjzpzy2vh4wC5g=; b=pgYzvKCBOpgOIn xdT1U1r//VYsOdi3NBLiju9XFd1PRR6Ck8SEABFKHpuJu1T79Ah1RuMDM2uC2uLmndGEHPj9jyFMh aW8v/6EpQR1S7ZKyW6I7JAurhHnRpzCzvvfV5xIMh8wt4xIGR4uPSgGzb5zZlWy6ZlRwkkgywy+P2 hR6GfOTAwfwqXvV1Mrp+Sx6S3vKiUSDz1fEgSx/F/T36Nh5miOxR0CZLFnNAe+tqC7lDfcaefsulK mle40GgPi2qOLGmK7ngzwLVJxu0hg2rRngofgN1JpK4qOYBpJtklVDLLct0KXnmOIUTaO7RtKFR5v JIxRBDYRGytrabeTYv9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgg-007glT-0a; Wed, 01 Nov 2023 14:59:18 +0000 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgW-007gdO-2k for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:15 +0000 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-9c5b313b3ffso1030771666b.0 for ; Wed, 01 Nov 2023 07:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850742; x=1699455542; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ONuosEbnLZ1tPZuBFPTx9Yzln1hf9IkS1/qIj5roSRc=; b=senej+frpeh8KWMYhlehHBjf40b5JdtROP6oYYR9CiTlpqv2IkFgclXoo+3FFeLE6O TuyLV8znKQGL501yTXGnpJPRo8fNAQSJPNs3B6iMS9qkQrw65HNenDyLC1io4Uc7R5vP IDhZGWcK7c9O3lL3s7Kj15W3rU5ZP0RWoc5gsI+UFRNVpuBwvPCeCMIY/a0QxeaNeaO8 ycbUFcX4FVj+y4KGrkWIjDXZi/LZoAZW9Mae0p0zumu2Q8U0ViL9DAt7LnwTb+lH/pIl ePnSLzZoi+FgVjfGku8srLpC4S+1P8FPSuD2FDN7J83FYtjvkrnhxEY32vGVl/LUCe9s /CIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850742; x=1699455542; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ONuosEbnLZ1tPZuBFPTx9Yzln1hf9IkS1/qIj5roSRc=; b=HMP7Wn0tJLKmdto64pXLq/Q6pwdAvCkTLweX04+QjPdY8vabEUzs6YQzyJ8b5fAVbi xs1CTk4OWZ8YG4CEQCnhtB8kVTC+Tbxv7sVdC31tM7jPsXgHfhBrO3r+b1vGFZdUaIDY OKN7wKjiF50N/ezto9jQBmI4V+IZXV0T+vtq2VGfCB/A9sIYYCbfwISZPz9rmZc6jhRZ n7exhLtlhiypgX152W0GIjDZwfgVtKkexXBdRmWys9UzVsDAHWOmua1Vz4UKoWo8XCJY znQPMNtOZcl8wZZgO8IfM6T3dCSW6LRCbu/c+C+xe8Ell27ktnm544GkynBvlvc6PPmA 7L1Q== X-Gm-Message-State: AOJu0Yw77Fcu/hruVsCBcB5Iy9arArVzeKZGpifBci66k7bcEzb1jH8l UO1h04XoFDvCyAh72c5lc6jN9w== X-Google-Smtp-Source: AGHT+IHzEdY4U7xwj2/PYKQtwgxUY11nL7vsa7XXb5Sh6zSeW24LIPh2B2gKcwpU9pSYvp5lN4D8jg== X-Received: by 2002:a17:907:9306:b0:9c7:5667:5643 with SMTP id bu6-20020a170907930600b009c756675643mr2266070ejc.72.1698850742306; Wed, 01 Nov 2023 07:59:02 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:59:01 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 3/6] mtd: spi-nor: spansion: enable die erase for multi die flashes Date: Wed, 1 Nov 2023 14:58:50 +0000 Message-ID: <20231101145853.524045-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075908_887714_8111D08D X-CRM114-Status: GOOD ( 13.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable die erase for spansion multi die flashes. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/spansion.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 12921344373d..6cc237c24e07 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -17,6 +17,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ +#define SPINOR_OP_CYPRESS_DIE_ERASE 0x61 /* Chip (die) erase */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -644,6 +645,7 @@ static int s25hx_t_late_init(struct spi_nor *nor) params->ready = cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); + params->die_erase_opcode = SPINOR_OP_CYPRESS_DIE_ERASE; return 0; } @@ -933,7 +935,6 @@ static const struct flash_info spansion_nor_parts[] = { .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .name = "s25hl02gt", .mfr_flags = USE_CLPEF, - .flags = NO_CHIP_ERASE, .fixups = &s25hx_t_fixups }, { .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), @@ -954,7 +955,6 @@ static const struct flash_info spansion_nor_parts[] = { .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .name = "s25hs02gt", .mfr_flags = USE_CLPEF, - .flags = NO_CHIP_ERASE, .fixups = &s25hx_t_fixups }, { .id = SNOR_ID(0x34, 0x5a, 0x1a), From patchwork Wed Nov 1 14:58:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F406BC4167B for ; Wed, 1 Nov 2023 14:59:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X3M029qJ9EH3gxH7htdG/CHNsk7B/yMzptGf0WQDpb0=; b=b4FH5TQos0pUvu bsh6UzsppxyoKBzUEGKwXUbqAwKZanbvgo8iKBTnKewJppoG2GmzykNTszsVx8Ua4GvcrqtNBoliM r+MzpQtbBJeLfgeHMc4ZqWG80i0rshazHk563B+JnD+P3FB7XlXShLQFZWDLk165O+r4p2TEioJGp j2zB7kGc46YAk0WodPPBjNpXG9CwBZkmksTTNS83won+MHGXsZZkVyHbs1laZ6UfFPFznOUBA8gHu fpyTJ1BHhKHJMQ1/A4tP74RrRMeehA0PZWyyu9H7KmZW4FqJn8vERGEdYJ0wgNg3Q+hd7KT/SYa5Q gQWtnvlvSTUrrFzI6esQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgh-007gmw-2u; Wed, 01 Nov 2023 14:59:19 +0000 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgY-007geV-0w for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:15 +0000 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-99c3c8adb27so1026784566b.1 for ; Wed, 01 Nov 2023 07:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850744; x=1699455544; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s1CaHujmlwRIOeKj3JlukIW6XiKQyNNWj005IH+mxcs=; b=aheJfTXf0ZCKVQe4VXI9vyACNrxIeOHxMVyAaENHbPW0GBQJuxZxcpPFTs9g26jZl5 UGdp2Yuu5e8E0ZYmRvFveI9w22tqMrwpK2D2KeYngF/d/Nz3+aVzpmU/YpQTGTnaDLXL uiXVf+DZu6KowCOPvl/Uw1AQaQSEbQ9vl/l7RqXfHA9QNFEzcZpuITVKKTg6p6K7VP7n UpcvKLIXVvE0V/nvRQjEAeVJvmRL47EeY6cdbo+na5J/tYtA8Tnwn/dX57yUSW/qqINa 4Kx1ZPecSHTKN7ZbxFA9Eq9zlMS6XY36jED9iljmgADeiIZpbH28w0HAG50TknJtdnnU Mnyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850744; x=1699455544; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s1CaHujmlwRIOeKj3JlukIW6XiKQyNNWj005IH+mxcs=; b=ByZV5RauOmw/TYHLjQj1GLu7NrNVbtk2AsYTRoJh/WqnT7gcnrznFdlvwjQNewyOwI iEjCUQ7hu8a1u9/Yd6qHdkcaCrIX9cHvOp4QrhcgbDBvqrHXnzGLiVr8KrF8KjTs9riy mU7VXXGbg60fJi4hJJE17rQLoziX0ZFeZs27ZC2S1LL67eHcyLbT+F7CFq011NkHz9+R bNCS7715BTwuoivb81okmne/oiq+nukBnhuU+c84ohS2iy8K0GobBbIFdXH8PdkJ5tKq dvxgSKW0HmrqGUeGp19QH6sECf6riKwuc8R+PvpvYZt2UJgyCTlMF88tGfDks8gB84Or lMOw== X-Gm-Message-State: AOJu0YxKH0d8sNfhwoZbNAH6ncGu+ZLwb5z453iRcyU+9S2PiNPBKQF2 TW1IJguFAXkBSIMh4tRD1tz60g== X-Google-Smtp-Source: AGHT+IHP3t+7SWk9N1xYbrdMhm8RoSoWabQNo8OWn08AM3L4gpOP+NAUQFo9ObOSImVDnQpy6uObfg== X-Received: by 2002:a17:907:c007:b0:9d4:55b1:a45f with SMTP id ss7-20020a170907c00700b009d455b1a45fmr2083066ejc.43.1698850743867; Wed, 01 Nov 2023 07:59:03 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:59:03 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 4/6] mtd: spi-nor: micron-st: enable die erase for multi die flashes Date: Wed, 1 Nov 2023 14:58:51 +0000 Message-ID: <20231101145853.524045-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075910_326264_D7AE75D1 X-CRM114-Status: GOOD ( 14.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable die erase for multi die flashes, it will speed the erase time. Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_1gb_3v_65nm.pdf?rev=b6eba74759984f749f8c039bc5bc47b7 Link: https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf?rev=43f7f66fc8da4d7d901b35fa51284c8f Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 8920547c12bf..ab8a53f0c99f 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -11,6 +11,7 @@ /* flash_info mfr_flag. Used to read proprietary FSR register. */ #define USE_FSR BIT(0) +#define SPINOR_OP_MT_DIE_ERASE 0xc4 /* Chip (die) erase opcode */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ @@ -192,6 +193,24 @@ static struct spi_nor_fixups mt25qu512a_fixups = { .post_bfpt = mt25qu512a_post_bfpt_fixup, }; +static int st_nor_four_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; + params->n_dice = 4; + + return 0; +} + +static struct spi_nor_fixups n25q00_fixups = { + .late_init = st_nor_four_die_late_init, +}; + +static struct spi_nor_fixups mt25q02_fixups = { + .late_init = st_nor_four_die_late_init, +}; + static const struct flash_info st_nor_parts[] = { { .name = "m25p05-nonjedec", @@ -366,16 +385,17 @@ static const struct flash_info st_nor_parts[] = { .name = "n25q00", .size = SZ_128M, .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE, + SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &n25q00_fixups, }, { .id = SNOR_ID(0x20, 0xba, 0x22), .name = "mt25ql02g", .size = SZ_256M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &mt25q02_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x15), .name = "n25q016a", @@ -433,16 +453,16 @@ static const struct flash_info st_nor_parts[] = { .id = SNOR_ID(0x20, 0xbb, 0x21), .name = "n25q00a", .size = SZ_128M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &n25q00_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x22), .name = "mt25qu02g", .size = SZ_256M, - .flags = NO_CHIP_ERASE, .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + .fixups = &mt25q02_fixups, } }; From patchwork Wed Nov 1 14:58:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D905C4167D for ; Wed, 1 Nov 2023 14:59:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vMITjgFJyQE0+FEga+GuTXCO55RfbYg9FWp4nZNBh3w=; b=edelrjDC1AEryE iBArqwqGw3xPPtmPvR10ShbKlsziXjuaoZWLeRo/eHmMd1CiKJYJ8Ll0/4bTHOmgK8z0f3qEVSVCX Wwkg1Z0J7QU+NPW+3/jy8HkqtiaV7valkG/zGbaqxjt/mWEegsvJ4NIN0/E0YsbwFVlzviaD9sjK0 w2AgpJBghCVBiaGMRGuj95QcUlBixPx1zk/JEM+CnCM2rLajn6SQHug6JLv1AAbk3tJwfrPhj+KbE cD/QseLhnefQJC8mOSTMIDm9jT96xRsQeIavY02MvKX9xIneUjJGg4MmjP0EkzeRh3lelhQm+sTOy +PV9kqk63LnpZDAdmarg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgh-007gmP-13; Wed, 01 Nov 2023 14:59:19 +0000 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgY-007gfQ-1q for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:15 +0000 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-9d8d3b65a67so91382766b.2 for ; Wed, 01 Nov 2023 07:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850745; x=1699455545; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AreOz513apIKgSX7yxcLMNB3mQeH4jejqLS8mho2UN8=; b=hhDdmKQMesgSRHk9M0qIn9eErTJRhIff7f4C8bOZ0LvYv1JRkdnmdeb0Et+wi0Dbwk 5QpiR3GHOj64kNZEAr9vQvsn43FTAIsILj20r0qPm0KL8oSpmxQs3gY8/l+t2un7xG83 uOZagpJP3aVeHWjZqQjrEh/K79vc+mrzjlAuFqEzznMjc68C569cq/TezDvhpTUiGQiL IQUWiY5PlPm0eSC1vLJkAZI1qDlIOKGkfsnAQMI7YHLTAxdMuoQkMpU15iIdLDNNsyaV ELK83MI0dpcrKXr/fyclhZqyknGoxYonBz6gHv6d03I9McK8o6C+F+nnMpa6I2UXowGl QlmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850745; x=1699455545; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AreOz513apIKgSX7yxcLMNB3mQeH4jejqLS8mho2UN8=; b=tMuhoVlElau600aUZA7mYqUe4exsMbxt8Ph7jfonw3gXsgk65v5Z1l1qgqDFuOcwVx qK0o1B1dahcrV8hzvsXIfySN9sJ1zdxMThJOufhjQ8tVBePrCG8EDoXt1EW1nN6Wg8Yb 49prPtKbadyHgwQNWzXdGsanztlZeXzfiVW6JUSW19kGe9kSb0rz1W4vqdwcT10nS8rK Kl6KFAw5XyXXoQfExYZ9B1BLRZzCRJoi/f6o1RRRRfJ92blqapigFZGKLLi7acPit2k8 4hcxZg9Ma2469g3ldxtzYIKC4Lz/2kp2aDpJrN6DyhUaT4X25zF6OgCloqmGrvUMtqri 6x0w== X-Gm-Message-State: AOJu0YxsQ9Ccfy9j9rZOdK4k7AXtnGyZaah2sv4EOB65KQ7jZYxfHkQi tNv916qe9eNeQcQZj4CVmPWQrQ== X-Google-Smtp-Source: AGHT+IGLBqDAENsbfx2hnYk/H7r4yocREQG2lYOF6Bhdp3ECspGPpIVw0IsQQg81a5zNi+pT/mZkoA== X-Received: by 2002:a17:907:7b9f:b0:9c2:a072:78bf with SMTP id ne31-20020a1709077b9f00b009c2a07278bfmr2308631ejc.26.1698850745585; Wed, 01 Nov 2023 07:59:05 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:59:04 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 5/6] mtd: spi-nor: remove NO_CHIP_ERASE flag Date: Wed, 1 Nov 2023 14:58:52 +0000 Message-ID: <20231101145853.524045-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075910_606156_E538294A X-CRM114-Status: GOOD ( 12.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 8 +++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index ac2651e76285..af8f3fc30256 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2886,9 +2886,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |= SNOR_F_HAS_SR_BP3_BIT6; } - if (flags & NO_CHIP_ERASE) - nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; - if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |= SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b43ea2d49e74..29ed67725b18 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,7 +489,6 @@ struct spi_nor_id { * Usually these will power-up in a write-protected * state. * SPI_NOR_NO_ERASE: no erase command needed. - * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. @@ -539,10 +538,9 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define NO_CHIP_ERASE BIT(7) -#define SPI_NOR_NO_FR BIT(8) -#define SPI_NOR_QUAD_PP BIT(9) -#define SPI_NOR_RWW BIT(10) +#define SPI_NOR_NO_FR BIT(7) +#define SPI_NOR_QUAD_PP BIT(8) +#define SPI_NOR_RWW BIT(9) u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) From patchwork Wed Nov 1 14:58:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13442856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B90E5C0018C for ; Wed, 1 Nov 2023 14:59:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZQqeFVV3mNblZcEf8FCzeEAjUBtw8SGkPQqyEjAmmKQ=; b=Csk8zht2ArFn0q cqWCZkdNQX+4w/IKU0YhdZ8VroinXV+WjMx9jQX16Kiw8IDp4U9Fxc7m6GgYPCYmLYL9NxGUuwVgt yicrifeAcfAtNW3EsmRtj460LriFH5VF6CHds+GSyoXdUV/Iq8kCCCnpTHeE2lS4YubbOrtIr/i/C zCeEVpCDrXyvJHAJiKvdVTyM/qkvMoJRkx/WM3zqBFJt0q/raidMnVmuQxzwMRxD5N1ruEyzCmuTh zdZZBEjvqqhGE2pbRhMJO9nu/AtLBMGL3cyJhXcOO8Hhz3nx2QP7Fsi1gqlUofXkY+5MOs0TGuo18 rOUEl9vFmJ11LkcIpqtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgi-007gnX-1d; Wed, 01 Nov 2023 14:59:20 +0000 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qyCgZ-007gfm-0E for linux-arm-kernel@lists.infradead.org; Wed, 01 Nov 2023 14:59:16 +0000 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-9becde9ea7bso200444666b.0 for ; Wed, 01 Nov 2023 07:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698850747; x=1699455547; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cc2RTGlWARp3griB6t8kpC6hCXGRaWKDTaju6cr+XBI=; b=ZUWlLANPRu9zAYpnvoFeoyj3cChkdNP05gJAhaU1qoFh7mLln+Tt9wjdMS6ikvrm4J z0Onlny5L7AB4A4PLLjHeI+S0TA9Mdx1I0UAmFjAxOkqbXCJtUWZ08ZM/q43SBM6QwSc VWucvZVCLzQIDJAlmU9gS823Mhgz09Eb7MV22WbR/TfNPB8Yxp7VH5hvD/jg1vdZY+vI qPIj/C2LHXDKcTTqtdULqzViSnRmNVhxEHOLMleukZ0NF2DBbn1MbjOOq/iPuUwLsHiE rijVCGRvRKjTBacwAJyzo92+RabLwKLse0Wowo6KCDF+Jh7V5fYr1ePmEqh4V7mEeoUs D27A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698850747; x=1699455547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cc2RTGlWARp3griB6t8kpC6hCXGRaWKDTaju6cr+XBI=; b=cR8+BrttYmO4BXpLTOD+vOGi+kQubxvk2uWq5n+W3/g//uo4StjNmbVfWL1Mk3BYu5 SpFSUj+cTPrvpk16u+k5RMYxCc2xhLfaktvj6CoFjvZRN9Dem8VV7Ckg8cEVz+2AxgMn RtGkQScSg+SAgOpFcpQSJOGwfokTC6Prd8HyfxNRSh9zT4Qz95GU6Y8MvCyK0lQkEuPK rHOniutCpHPYludDjeHLG3KLwLgHuq8kCQnF+qBblBFGlXyWIjQ4sW2jPhPH92s1FO2L ioRnDHvRx3uvOQRPQf+0Koze1gDiVvqlqcHh36wrEbZwQMh4+QG29aG9Pr9DEMvQjHtw CgJA== X-Gm-Message-State: AOJu0Yyds/BeQQ1kLFW/05s5J+Cv/4OgCdYUhr5g0ych/XH4wkwd3iJ2 qB2ap6rZRjmCLaY/ajzMuatkrA== X-Google-Smtp-Source: AGHT+IFeHd2qAYY0FBzh63fvqvnbs/U3KH/28ZQtZLMHKMAnCTOsRCvAWN/9IFwyxwrP+OVaU3T+Sw== X-Received: by 2002:a17:906:b11a:b0:9aa:206d:b052 with SMTP id u26-20020a170906b11a00b009aa206db052mr2270730ejy.27.1698850747065; Wed, 01 Nov 2023 07:59:07 -0700 (PDT) Received: from tudordana.roam.corp.google.com ([79.115.63.76]) by smtp.gmail.com with ESMTPSA id i18-20020a170906115200b009ad8acac02asm20448eja.172.2023.11.01.07.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 07:59:06 -0700 (PDT) From: Tudor Ambarus To: michael@walle.cc, festevam@denx.de, takahiro.kuwano@infineon.com Cc: pratyush@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, bacem.daassi@infineon.com, miquel.raynal@bootlin.com, richard@nod.at, Tudor Ambarus Subject: [PATCH v2 6/6] mtd: spi-nor: micron-st: Add support for mt25qu01g Date: Wed, 1 Nov 2023 14:58:53 +0000 Message-ID: <20231101145853.524045-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.42.0.820.g83a721a137-goog In-Reply-To: <20231101145853.524045-1-tudor.ambarus@linaro.org> References: <20231101145853.524045-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231101_075911_108214_4A5AAA42 X-CRM114-Status: GOOD ( 12.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Fabio Estevam Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory model. Datasheet: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf Tested on a i.MX8MP based board: # dmesg | grep spi-nor spi-nor spi0.0: mt25qu01g (131072 Kbytes) # cat /proc/mtd dev: size erasesize name mtd0: 08000000 00001000 "30bb0000.spi" ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/jedec_id 20bb21104400 ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/manufacturer st ~# cat /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/partname mt25qu01g ~# xxd -p /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 53464450060101ff00060110300000ff84000102800000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e 03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff ffffffffffffffffffe7ffff21dcffff ~# md5sum /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp 9d28d1b11de8b15ba9152644219d9a78 /sys/devices/platform/soc@0/30800000.bus/30bb0000.spi/spi_master/spi0/spi0.0/spi-nor/sfdp Signed-off-by: Fabio Estevam [ta: introduce die erase] Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/micron-st.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index ab8a53f0c99f..42daa2116752 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -203,10 +203,24 @@ static int st_nor_four_die_late_init(struct spi_nor *nor) return 0; } +static int st_nor_two_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params = nor->params; + + params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE; + params->n_dice = 2; + + return 0; +} + static struct spi_nor_fixups n25q00_fixups = { .late_init = st_nor_four_die_late_init, }; +static struct spi_nor_fixups mt25q01_fixups = { + .late_init = st_nor_two_die_late_init, +}; + static struct spi_nor_fixups mt25q02_fixups = { .late_init = st_nor_four_die_late_init, }; @@ -449,6 +463,11 @@ static const struct flash_info st_nor_parts[] = { SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags = USE_FSR, + }, { + .id = SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), + .name = "mt25qu01g", + .mfr_flags = USE_FSR, + .fixups = &mt25q01_fixups, }, { .id = SNOR_ID(0x20, 0xbb, 0x21), .name = "n25q00a",