From patchwork Wed Nov 1 18:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13442988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 730FEC4167D for ; Wed, 1 Nov 2023 18:33:10 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 060FD900017; Wed, 1 Nov 2023 14:33:10 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 0109B90000D; Wed, 1 Nov 2023 14:33:09 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id DA5FB900017; Wed, 1 Nov 2023 14:33:09 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id CB24690000D for ; Wed, 1 Nov 2023 14:33:09 -0400 (EDT) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay10.hostedemail.com (Postfix) with ESMTP id 9B8DBC0D2E for ; Wed, 1 Nov 2023 18:33:09 +0000 (UTC) X-FDA: 81410232498.12.D428D07 Received: from mail-oo1-f50.google.com (mail-oo1-f50.google.com [209.85.161.50]) by imf14.hostedemail.com (Postfix) with ESMTP id BAA3F10000D for ; Wed, 1 Nov 2023 18:33:07 +0000 (UTC) Authentication-Results: imf14.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=vElO8PAI; dmarc=none; spf=pass (imf14.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.50 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1698863587; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=bmX47uOjeBLgcqnLG2LWRRnp8TOL9YLBnfsBk3939lI=; b=tmh+hkf5TKXt4znzwWnFTTQ+zgbCmR3S0D3FE23SgS6cY82p6JfBMpDRwKvYhFrnTv4Pkt 8x6oENtwl9ntathD8AcvsNOX5uHYEWR36/vbMry/gNbKzpVXVbu+QMcfSHmMShYkQUKoiM Qe+avpvdQltj+mlgsSb5bOZ2s+Ret8s= ARC-Authentication-Results: i=1; imf14.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=vElO8PAI; dmarc=none; spf=pass (imf14.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.50 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1698863587; a=rsa-sha256; cv=none; b=VtBfFB+q1GjKHYb/dmrmokuSPefeWM4FIVf09qRp6vHE2KVhncw7LsTIe5CK8Q2lXgM8VE t+Mg7JwCQgq+klcnztsCJoz3X0l7X6zZevxMLvNARo88OL1p6wF1TVzaOnHDA6WlszXM30 FuAtjXUVjuop8WSo+HWrgXOlpRsv+es= Received: by mail-oo1-f50.google.com with SMTP id 006d021491bc7-5842a7fdc61so39313eaf.3 for ; Wed, 01 Nov 2023 11:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698863587; x=1699468387; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bmX47uOjeBLgcqnLG2LWRRnp8TOL9YLBnfsBk3939lI=; b=vElO8PAIbXTbrmHWNUqd26L9S4Ib3ewA8Svge9zOw3xq2VckgXP7Hjf6okV+cMNshv 4uWLv9ZUm2cIvEhDoLroJ3J/z92Aek38ae8Uius5Res2hGklC+SAL/8xS6N1t0sha4SQ ZG53JhZd4e1jr/3+uJ+mpsdPtttJKyfPVlaJ/w7gS7IWTHngexjyEliyKEIi2eDOQm58 JMYaR7Hn3rs9s18QmLBzduTT/V7ab3n7pL6cAIf7K8BZ+tMjmYkJ+3kXzxX4bOTJNu/Q blFkshYvu6hUWYwGptQGAHXa4mOsN4zIqdKxgb3T/J2bBoky8FGZ0fdt1YsO/bCkZlWL Jx+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698863587; x=1699468387; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bmX47uOjeBLgcqnLG2LWRRnp8TOL9YLBnfsBk3939lI=; b=cAkGdnrs0OkG6zfcMWnEa985GNbgBaJzTxrjR7pUrlkipdYlq3ESUYKxqJdZRQh7Np 8HOz9xZseCXY7P8U3FpO2SQkMcGonm/MwNb4WXWjZ+zuvrdUz00E9iKeuZul3Ez88/6w nBJeWGCrnsipLHYX/qIc2UXiOKoq6rF8/6qiZmZU7eUVHUr1Q+k3CpMtKNy7NWeP6pRk 2chxj3BSKPuFYWBZcazi5SQHCouHQpc+5zA1CJIVui9UmrhtZCdK5qvhvJ7gJDpe0otB bKbozVb0U0o1P9SQTixqRJN6I4Rd3jxZrbFy132UHfnomgnO2jlta9+RX6xy5F5TSXQ7 JLpw== X-Gm-Message-State: AOJu0YwKwOHe1nudxOtH71swLhJBob7mLu6InYMNbYgAj5pLBYjzVuQg D4MM7a/IjDktBvtx/+Oez22HQQ== X-Google-Smtp-Source: AGHT+IEy6ddaceBESFTSWHP+MOBVo7SllhOU1bINZBrAu1EBzKWDnREAu5ah35KCCWiY3grX8PD/MA== X-Received: by 2002:a4a:a649:0:b0:582:c8b4:d9df with SMTP id j9-20020a4aa649000000b00582c8b4d9dfmr16068466oom.1.1698863586805; Wed, 01 Nov 2023 11:33:06 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m14-20020a4aab8e000000b00581e090fd1fsm686331oon.8.2023.11.01.11.33.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 11:33:06 -0700 (PDT) From: Charlie Jenkins Date: Wed, 01 Nov 2023 11:32:59 -0700 Subject: [PATCH v9 1/3] riscv: Avoid unaligned access when relocating modules MIME-Version: 1.0 Message-Id: <20231101-module_relocations-v9-1-8dfa3483c400@rivosinc.com> References: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> In-Reply-To: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Nelson Chu , Charlie Jenkins , Emil Renner Berthing X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: BAA3F10000D X-Rspam-User: X-Rspamd-Server: rspam05 X-Stat-Signature: ks1o5fs6njieadbisp8quxxmx6yedem6 X-HE-Tag: 1698863587-474527 X-HE-Meta: U2FsdGVkX19cPhpLiU3MJs8jkO54G4o9GJbp6skGxYYUVxVgvIpGRiFYnPgrsWhkeP3AgxMRo7+BReHUbXXF/9W2vrGV1UY/XI64pwn1MYV4PTIUVVoiRcBNs5GVXTvAG0kPi1hNNKMRIu4dU5c419pIwmuLAG+lfDDi85yx3ZsqHmwp3Xxb//1VhUgBB1/zg4o+w3TpJy0ZX4tUeVdId/WDHV8dVMAKSEPFrd00DZMMRO/e7mp6db9fi3Oyete+Z2BxC0AQdxp7doWmrKy8/LwzBm1SbIvNZUeICgDu/L0xhsrXlCT9rFtRKTYNoM02Xw/A4UOdyzeHSbaSBHwSR9rV3hwax6S2YYjeQY7CpJj5WYKJgh0YuGhsZrIHn15JsY2gITAjrdtE/jiySLiqve4XZrO1vRU13xH0YygsyJhpsaw+POrnKd8qMGAb+77aQ6isYdRULOaYezW1kqOkxHT5GDupe9Z9mN4VBG0u4yY0lINAjqh4C7fV6JsS4Hx8m4Rwl3/uYqIg6yqzyouzS9JmEsFFK8xUlBvTI7185kzneSWzLwkDJnHjoXeXQRToaWPqhwChBnXwSqA7CBM2Z11Sj0GZVZE5mmInVuoVhLlr80hLcVK7Z0J1octQCvgjC/nN8PsA9KWbf6LEOsGwWTJnaY9cHUsdcGFjBRLTtSB+VMbLIrgykZ+FYTtSoksxbao5hXHXUB+/7H9bLQe6+/lW9vRRRUL6CJ5pWlAPR5y5zVoCS4KyagoEisxL5jdqtiLUwKhZL567Hd0SDY3C2JpfAKUDLaQVsVH82CPHZT6zXKFTTzTXF4IMKdTmPH30KIHan24qOHe4hKlbZ57D20dXOMJyt2l1+CsEytdM3ZNcLfSVtrqNjwevpTDLhcdaVzrwj98V7C5X68FmCnjLNNC6l4SKon3Vhv9wwGA4LX1QDbrsdpBayamSojdM5aigdK548grMFXkM32KBOVH 3B5COMfI aoh69ct+hz0qE8ZrE7T1u1Yx1JcJS3OwFX8Otwhb4mfk9nk/Es6kckO3hZw+QoPwLVc6VDP7WFiUnwm1KrYaPvkELi4NxJSa8e1cImRaxxGCW+ktQFglJtXgH4t0KFCAsznUcF+fjZChTO6qhK0yIb7Z/rOApj1S9utWaRXIOoTZjs4IzscH0MXgKewQv03i75VMosrodyjbxdEtGgfz360gyk4dO53tBwJev2Hhgy3C3NjEdrQ5FbrCjSsK1EPr1vRrK+1Dl1qHzp4PUhId5t1GdSmzsa5z+L/7M7EcB9PnkVWIXASmza95ZYWg70yARjjXjk49nDTYZsT6o+yJHlRvySi6jamIlBhDHRECyZZH8J5xz7adP7iEPzorvkGmpCq03P9y6NYoO9zgrOOS0By0kcvK5S4dxbgbFPLBaEvEbDkNkkZgKaug7YMCtqNqjDdPjF3X/jpADiTVprbU7+UfGx7cC7JkLJop/jN1TPUNbRTSCwZcZLgncUJoNdDIEp2wxP6vxJLDIsva1EQXNkj4hu+a4XT9eZYzG X-Bogosity: Ham, tests=bogofilter, spamicity=0.000591, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Emil Renner Berthing With the C-extension regular 32bit instructions are not necessarily aligned on 4-byte boundaries. RISC-V instructions are in fact an ordered list of 16bit little-endian "parcels", so access the instruction as such. This should also make the code work in case someone builds a big-endian RISC-V machine. Signed-off-by: Emil Renner Berthing Signed-off-by: Charlie Jenkins --- arch/riscv/kernel/module.c | 157 +++++++++++++++++++++++---------------------- 1 file changed, 81 insertions(+), 76 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 7c651d55fcbd..8286d3bb04f4 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -27,68 +27,90 @@ static bool riscv_insn_valid_32bit_offset(ptrdiff_t val) #endif } -static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v) +static int riscv_insn_rmw(void *location, u32 keep, u32 set) +{ + u16 *parcel = location; + u32 insn = (u32)le16_to_cpu(parcel[0]) | (u32)le16_to_cpu(parcel[1]) << 16; + + insn &= keep; + insn |= set; + + parcel[0] = cpu_to_le16(insn); + parcel[1] = cpu_to_le16(insn >> 16); + return 0; +} + +static int riscv_insn_rvc_rmw(void *location, u16 keep, u16 set) +{ + u16 *parcel = location; + u16 insn = le16_to_cpu(*parcel); + + insn &= keep; + insn |= set; + + *parcel = cpu_to_le16(insn); + return 0; +} + +static int apply_r_riscv_32_rela(struct module *me, void *location, Elf_Addr v) { if (v != (u32)v) { pr_err("%s: value %016llx out of range for 32-bit field\n", me->name, (long long)v); return -EINVAL; } - *location = v; + *(u32 *)location = v; return 0; } -static int apply_r_riscv_64_rela(struct module *me, u32 *location, Elf_Addr v) +static int apply_r_riscv_64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location = v; return 0; } -static int apply_r_riscv_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u32 imm12 = (offset & 0x1000) << (31 - 12); u32 imm11 = (offset & 0x800) >> (11 - 7); u32 imm10_5 = (offset & 0x7e0) << (30 - 10); u32 imm4_1 = (offset & 0x1e) << (11 - 4); - *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm12 | imm11 | imm10_5 | imm4_1); } -static int apply_r_riscv_jal_rela(struct module *me, u32 *location, +static int apply_r_riscv_jal_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u32 imm20 = (offset & 0x100000) << (31 - 20); u32 imm19_12 = (offset & 0xff000); u32 imm11 = (offset & 0x800) << (20 - 11); u32 imm10_1 = (offset & 0x7fe) << (30 - 10); - *location = (*location & 0xfff) | imm20 | imm19_12 | imm11 | imm10_1; - return 0; + return riscv_insn_rmw(location, 0xfff, imm20 | imm19_12 | imm11 | imm10_1); } -static int apply_r_riscv_rvc_branch_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_branch_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u16 imm8 = (offset & 0x100) << (12 - 8); u16 imm7_6 = (offset & 0xc0) >> (6 - 5); u16 imm5 = (offset & 0x20) >> (5 - 2); u16 imm4_3 = (offset & 0x18) << (12 - 5); u16 imm2_1 = (offset & 0x6) << (12 - 10); - *(u16 *)location = (*(u16 *)location & 0xe383) | - imm8 | imm7_6 | imm5 | imm4_3 | imm2_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe383, + imm8 | imm7_6 | imm5 | imm4_3 | imm2_1); } -static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, +static int apply_r_riscv_rvc_jump_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u16 imm11 = (offset & 0x800) << (12 - 11); u16 imm10 = (offset & 0x400) >> (10 - 8); u16 imm9_8 = (offset & 0x300) << (12 - 11); @@ -98,16 +120,14 @@ static int apply_r_riscv_rvc_jump_rela(struct module *me, u32 *location, u16 imm4 = (offset & 0x10) << (12 - 5); u16 imm3_1 = (offset & 0xe) << (12 - 10); - *(u16 *)location = (*(u16 *)location & 0xe003) | - imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1; - return 0; + return riscv_insn_rvc_rmw(location, 0xe003, + imm11 | imm10 | imm9_8 | imm7 | imm6 | imm5 | imm4 | imm3_1); } -static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_pcrel_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset = (void *)v - location; if (!riscv_insn_valid_32bit_offset(offset)) { pr_err( @@ -116,23 +136,20 @@ static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, return -EINVAL; } - hi20 = (offset + 0x800) & 0xfffff000; - *location = (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } -static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, u32 *location, +static int apply_r_riscv_pcrel_lo12_i_rela(struct module *me, void *location, Elf_Addr v) { /* * v is the lo12 value to fill. It is calculated before calling this * handler. */ - *location = (*location & 0xfffff) | ((v & 0xfff) << 20); - return 0; + return riscv_insn_rmw(location, 0xfffff, (v & 0xfff) << 20); } -static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, u32 *location, +static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, void *location, Elf_Addr v) { /* @@ -142,15 +159,12 @@ static int apply_r_riscv_pcrel_lo12_s_rela(struct module *me, u32 *location, u32 imm11_5 = (v & 0xfe0) << (31 - 11); u32 imm4_0 = (v & 0x1f) << (11 - 4); - *location = (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } -static int apply_r_riscv_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_hi20_rela(struct module *me, void *location, Elf_Addr v) { - s32 hi20; - if (IS_ENABLED(CONFIG_CMODEL_MEDLOW)) { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n", @@ -158,22 +172,20 @@ static int apply_r_riscv_hi20_rela(struct module *me, u32 *location, return -EINVAL; } - hi20 = ((s32)v + 0x800) & 0xfffff000; - *location = (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, ((s32)v + 0x800) & 0xfffff000); } -static int apply_r_riscv_lo12_i_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_i_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ s32 hi20 = ((s32)v + 0x800) & 0xfffff000; s32 lo12 = ((s32)v - hi20); - *location = (*location & 0xfffff) | ((lo12 & 0xfff) << 20); - return 0; + + return riscv_insn_rmw(location, 0xfffff, (lo12 & 0xfff) << 20); } -static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, +static int apply_r_riscv_lo12_s_rela(struct module *me, void *location, Elf_Addr v) { /* Skip medlow checking because of filtering by HI20 already */ @@ -181,20 +193,18 @@ static int apply_r_riscv_lo12_s_rela(struct module *me, u32 *location, s32 lo12 = ((s32)v - hi20); u32 imm11_5 = (lo12 & 0xfe0) << (31 - 11); u32 imm4_0 = (lo12 & 0x1f) << (11 - 4); - *location = (*location & 0x1fff07f) | imm11_5 | imm4_0; - return 0; + + return riscv_insn_rmw(location, 0x1fff07f, imm11_5 | imm4_0); } -static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, +static int apply_r_riscv_got_hi20_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; - s32 hi20; + ptrdiff_t offset = (void *)v - location; /* Always emit the got entry */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset = module_emit_got_entry(me, v); - offset = (void *)offset - (void *)location; + offset = (void *)module_emit_got_entry(me, v) - location; } else { pr_err( "%s: can not generate the GOT entry for symbol = %016llx from PC = %p\n", @@ -202,22 +212,19 @@ static int apply_r_riscv_got_hi20_rela(struct module *me, u32 *location, return -EINVAL; } - hi20 = (offset + 0x800) & 0xfffff000; - *location = (*location & 0xfff) | hi20; - return 0; + return riscv_insn_rmw(location, 0xfff, (offset + 0x800) & 0xfffff000); } -static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_plt_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u32 hi20, lo12; if (!riscv_insn_valid_32bit_offset(offset)) { /* Only emit the plt entry if offset over 32-bit range */ if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { - offset = module_emit_plt_entry(me, v); - offset = (void *)offset - (void *)location; + offset = (void *)module_emit_plt_entry(me, v) - location; } else { pr_err( "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n", @@ -228,15 +235,14 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, hi20 = (offset + 0x800) & 0xfffff000; lo12 = (offset - hi20) & 0xfff; - *location = (*location & 0xfff) | hi20; - *(location + 1) = (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } -static int apply_r_riscv_call_rela(struct module *me, u32 *location, +static int apply_r_riscv_call_rela(struct module *me, void *location, Elf_Addr v) { - ptrdiff_t offset = (void *)v - (void *)location; + ptrdiff_t offset = (void *)v - location; u32 hi20, lo12; if (!riscv_insn_valid_32bit_offset(offset)) { @@ -248,18 +254,17 @@ static int apply_r_riscv_call_rela(struct module *me, u32 *location, hi20 = (offset + 0x800) & 0xfffff000; lo12 = (offset - hi20) & 0xfff; - *location = (*location & 0xfff) | hi20; - *(location + 1) = (*(location + 1) & 0xfffff) | (lo12 << 20); - return 0; + riscv_insn_rmw(location, 0xfff, hi20); + return riscv_insn_rmw(location + 4, 0xfffff, lo12 << 20); } -static int apply_r_riscv_relax_rela(struct module *me, u32 *location, +static int apply_r_riscv_relax_rela(struct module *me, void *location, Elf_Addr v) { return 0; } -static int apply_r_riscv_align_rela(struct module *me, u32 *location, +static int apply_r_riscv_align_rela(struct module *me, void *location, Elf_Addr v) { pr_err( @@ -268,49 +273,49 @@ static int apply_r_riscv_align_rela(struct module *me, u32 *location, return -EINVAL; } -static int apply_r_riscv_add16_rela(struct module *me, u32 *location, +static int apply_r_riscv_add16_rela(struct module *me, void *location, Elf_Addr v) { *(u16 *)location += (u16)v; return 0; } -static int apply_r_riscv_add32_rela(struct module *me, u32 *location, +static int apply_r_riscv_add32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location += (u32)v; return 0; } -static int apply_r_riscv_add64_rela(struct module *me, u32 *location, +static int apply_r_riscv_add64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location += (u64)v; return 0; } -static int apply_r_riscv_sub16_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub16_rela(struct module *me, void *location, Elf_Addr v) { *(u16 *)location -= (u16)v; return 0; } -static int apply_r_riscv_sub32_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub32_rela(struct module *me, void *location, Elf_Addr v) { *(u32 *)location -= (u32)v; return 0; } -static int apply_r_riscv_sub64_rela(struct module *me, u32 *location, +static int apply_r_riscv_sub64_rela(struct module *me, void *location, Elf_Addr v) { *(u64 *)location -= (u64)v; return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, +static int (*reloc_handlers_rela[]) (struct module *me, void *location, Elf_Addr v) = { [R_RISCV_32] = apply_r_riscv_32_rela, [R_RISCV_64] = apply_r_riscv_64_rela, @@ -342,9 +347,9 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, struct module *me) { Elf_Rela *rel = (void *) sechdrs[relsec].sh_addr; - int (*handler)(struct module *me, u32 *location, Elf_Addr v); + int (*handler)(struct module *me, void *location, Elf_Addr v); Elf_Sym *sym; - u32 *location; + void *location; unsigned int i, type; Elf_Addr v; int res; From patchwork Wed Nov 1 18:33:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13442987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F755C0018A for ; Wed, 1 Nov 2023 18:33:13 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id BD494900018; Wed, 1 Nov 2023 14:33:12 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id B82EE90000D; Wed, 1 Nov 2023 14:33:12 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 9D52E900018; Wed, 1 Nov 2023 14:33:12 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 8B1C190000D for ; Wed, 1 Nov 2023 14:33:12 -0400 (EDT) Received: from smtpin10.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id 48BB8409AC for ; Wed, 1 Nov 2023 18:33:12 +0000 (UTC) X-FDA: 81410232624.10.BED44CC Received: from mail-oo1-f48.google.com (mail-oo1-f48.google.com [209.85.161.48]) by imf01.hostedemail.com (Postfix) with ESMTP id 5898F40011 for ; Wed, 1 Nov 2023 18:33:10 +0000 (UTC) Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NMRV6HWi; dmarc=none; spf=pass (imf01.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.48 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1698863590; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=FtzZIf8mBJ7+Ey08l6PkxF7Ft7nE+u+N8GihK+Ta5xM=; b=UnFVX2R64L+Niabbf3o7h1TssFniRLUcIENEHlG0taLg+9+y5AuMwa5iD5m/YX0bkKU3I8 otDZKEHv8EpO+ZcEumsNoNQAdzXjev2Hqdg4MrwY/KS79CK9gz5gmFc96WjXhJPZP2UUK1 3rSBDqQRtWnau0wBOKqg8sSD39OyR6o= ARC-Authentication-Results: i=1; imf01.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=NMRV6HWi; dmarc=none; spf=pass (imf01.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.48 as permitted sender) smtp.mailfrom=charlie@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1698863590; a=rsa-sha256; cv=none; b=hVV9JjaSlF9mZyMrxM35HKplTg7gSF90rBPMm3fsLsjUuWaMiUHieg6IDc7fgttte0umuu 3bBdqF7cyf724prP9x0vCSeAdyhM5nbdevmqXMtO0qVEAI2aQGD66lLoydOdcU+E2js3Ux y1ntARTn8xLCzsIT9idOEPORlBpOZKw= Received: by mail-oo1-f48.google.com with SMTP id 006d021491bc7-57d086365f7so51108eaf.0 for ; Wed, 01 Nov 2023 11:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698863589; x=1699468389; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FtzZIf8mBJ7+Ey08l6PkxF7Ft7nE+u+N8GihK+Ta5xM=; b=NMRV6HWiKG2SIeH6mWWuRgkl+A0oh6LqA8ol3dckUp6AMSa4oXOmw88arnJ+Ltj8Kv BYmEuuCTwOoQqw+xEw/HlP4/uDJTm8j9pn/f1nZuUlVq0Eq8IQPqe50T7QiNRJ15PpTG T7y5/03RYX3uVjj2VbCU3wxB9EgVoSq7NZ/UvzRImNlbF2Q8xQgbrvlHEIOSfiNrQLKq o5S0Kq8N9xV2KMHQDpiFg+uzBf0H3UkBFslm+pOVL5kmmhXE9PNf8EE3u5TVf1uPilDZ s+4h6LFQBeSEN3+Zf8cBrz4yD7nmzl39Kp0YdiGCn4OnToK3gSTXMjWQX/8AsxBWBNhV gugQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698863589; x=1699468389; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FtzZIf8mBJ7+Ey08l6PkxF7Ft7nE+u+N8GihK+Ta5xM=; b=A/ueBuJksfJKHAFP/syUPXMBUIg5L+zs1i328gIVcUAMCxE4gm0BjdvMDMJxyqmgR4 9ZhU8SXiVqEekm2EJIvqYoDVAicBEBkOAQE/VH6cJXt1d5Ol3ZEETxHFZ9vVtcdqu3zx bM1hTYlgbYmYZjsXY6iz2lHcV+WX0P0+jgu94Uls0+unKo9ht252eopwH76b/oYd7+mr x05VVW8Vhj425kJbASV9JzEDT/HSJcFwjZcX34g7CRgak5If7g+pCUrYEhRWt13MNAV+ BBVzMr64NeXJKLB6TSPKDWawKkm/Yl0qUriOU3/pVdc1fBlwvHeKe7lRDH4j5lmLsriH gKkA== X-Gm-Message-State: AOJu0YwlPwIGVufQ+i9GnQR+1xoOMShErw8ykNctmA3lmVarukAuc37Y 7W5ShPKhoNtyhv9MzKs/DvnTXw== X-Google-Smtp-Source: AGHT+IGOPe0WC74Ig9kJeU3G4KlQqvKETUNZbt/Zr27obVfknfcp5jVZziY/hDC8A4yjnciu2NhRQg== X-Received: by 2002:a05:6820:1799:b0:581:ea96:f800 with SMTP id bs25-20020a056820179900b00581ea96f800mr18272643oob.6.1698863589482; Wed, 01 Nov 2023 11:33:09 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m14-20020a4aab8e000000b00581e090fd1fsm686331oon.8.2023.11.01.11.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 11:33:08 -0700 (PDT) From: Charlie Jenkins Date: Wed, 01 Nov 2023 11:33:00 -0700 Subject: [PATCH v9 2/3] riscv: Add remaining module relocations MIME-Version: 1.0 Message-Id: <20231101-module_relocations-v9-2-8dfa3483c400@rivosinc.com> References: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> In-Reply-To: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Nelson Chu , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 5898F40011 X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: adyzb43zmttw8amd66k6futyz3axcnjd X-HE-Tag: 1698863590-658636 X-HE-Meta: U2FsdGVkX19Px3YWGErDtOAQ+QZKGd4F0GTKtGy09L10Mz6VoN1naQwi1BlBP50CVZX8h+anjMGADGTGOMeJEieukssZ/jWzwXdyj9yJVZ/eTKgXX2oIIsyKsHzfjgkTFHxc1LKRPlxfKIe8hvEfB5U2vGaSdeMEhBXoL7BfZqebu1S+vCU4+9YPeM7D/faAhoIkylWPCfmkHDSCexO6xBCXV5KI7R5bjhcfZSLYVy8Eys0Xn8hmWMVqvBeiSJMec3aJ1YCrljIMOpOD65rnCTsHIjuzPj5xZLDUmTyeArH46vRsCS/m9CggakQYx4K2579mEAT2lswK5phEDkRnO/RP+7HQgx2KyVVhDZ9HvGVhJx+XQk1Sv8HsLpImz8sjE/o9KSVmfkL0JVcZ6XiyymZMIxVPgG9xjNRvkxB8RwEPZwojrETcO/N7q3AxN1qoiRtLUZ8Ewot2CQUZD1rQiSEjfZQB9Igcd9r7fjIKtynMr4SXekwc8jam7UBjVdNinCCBsuho2RokC68dSWXEW8+fmSsO80DkRFvbnkaMkNq08vezeXsxfZz5447UWmxiVFh91ZtqYcEbli83ZK7KyvZy5hbzoLYWOzLvzYFjM0Op6B0VLqtsvWPh90aF/iqeAoyA2yjozrPkfQaI8Y72D9KYyvgq8ayc7XQFUfVwNlEuukM0+eG3P8Y06cTjF82NT07MXKf3eSCU0rBcF4YK0eQFlvEFwExcgZldHmoaH4N811qavml/vkXg85Tt6tguoxhAiCrVhBSd/zzIbTc6xUYOR3WN6JT+O4OqZ8ydLarcEUb7YamiLDR29rimiBH1qu9CLaB9VL4Yt3EnhL/Giei4pnh9/6DhRlZK/ODEOU2BdoXCfxUY8YiIVaOAHhz4qp9lNTTByzmFDNJV088eg4zOPAhVBL5YC2n8hJr++HNSVp0xOkWtDgmI2ada+FByBngdUJceteGbbK9L2q1 674LYGfA KScShIj0RWEjO/08M5kKGO+Y07pkQYUYR7WUPc1zy0JcZ6CrhSHa4YMXkxXqipYlGc/l99BhFLbcP2T4naR/bowYJ8bFNERqjAKUkPHlDzIn/2mu6VrQZUxpSAiCIHQPfYSqmCKWlNX3BN8pRv6GBISs25dCj/na21LDCf5MykjMBFkEANeFeADMRxzI0YH9rTcBJXxFLIyE9TwwGrWX2TK+nRuedO8aG7u09qI0UKSMHEb9/O4TP+NnaYzDCdINr7MfrEdq0Ml5oyFSrA/k6aUE3aZl+A1GXYHfO5TjiG2p3bIVOXSSzYXBiFgdBYW8aFf7l8e90Ga2b2W2Z7F30bqufnZZp66KFSIWJ1kTM11x14N1eF5XEweu93nK1eJthlO03PZpoqLlOSVJlqdIf4SxW8ss/uIAEU1rXGsATFD2N+GiRvWUPHwICb+PG7WDeIziLn0BGO7apoHg= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add all final module relocations and add error logs explaining the ones that are not supported. Implement overflow checks for ADD/SUB/SET/ULEB128 relocations. Signed-off-by: Charlie Jenkins --- arch/riscv/include/uapi/asm/elf.h | 5 +- arch/riscv/kernel/module.c | 448 +++++++++++++++++++++++++++++++++++--- 2 files changed, 423 insertions(+), 30 deletions(-) diff --git a/arch/riscv/include/uapi/asm/elf.h b/arch/riscv/include/uapi/asm/elf.h index d696d6610231..11a71b8533d5 100644 --- a/arch/riscv/include/uapi/asm/elf.h +++ b/arch/riscv/include/uapi/asm/elf.h @@ -49,6 +49,7 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_TLS_DTPREL64 9 #define R_RISCV_TLS_TPREL32 10 #define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_IRELATIVE 58 /* Relocation types not used by the dynamic linker */ #define R_RISCV_BRANCH 16 @@ -81,7 +82,6 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_ALIGN 43 #define R_RISCV_RVC_BRANCH 44 #define R_RISCV_RVC_JUMP 45 -#define R_RISCV_LUI 46 #define R_RISCV_GPREL_I 47 #define R_RISCV_GPREL_S 48 #define R_RISCV_TPREL_I 49 @@ -93,6 +93,9 @@ typedef union __riscv_fp_state elf_fpregset_t; #define R_RISCV_SET16 55 #define R_RISCV_SET32 56 #define R_RISCV_32_PCREL 57 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 #endif /* _UAPI_ASM_RISCV_ELF_H */ diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index 8286d3bb04f4..4b339729d5ec 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -14,6 +17,38 @@ #include #include +struct used_bucket { + struct list_head head; + struct hlist_head *bucket; +}; + +struct relocation_head { + struct hlist_node node; + struct list_head *rel_entry; + void *location; +}; + +struct relocation_entry { + struct list_head head; + Elf_Addr value; + unsigned int type; +}; + +struct relocation_handlers { + int (*reloc_handler)(struct module *me, void *location, Elf_Addr v); + int (*accumulate_handler)(struct module *me, void *location, + long buffer); +}; + +unsigned int initialize_relocation_hashtable(unsigned int num_relocations); +void process_accumulated_relocations(struct module *me); +int add_relocation_to_accumulate(struct module *me, int type, void *location, + unsigned int hashtable_bits, Elf_Addr v); + +struct hlist_head *relocation_hashtable; + +struct list_head used_buckets_list; + /* * The auipc+jalr instruction pair can reach any PC-relative offset * in the range [-2^31 - 2^11, 2^31 - 2^11) @@ -273,6 +308,12 @@ static int apply_r_riscv_align_rela(struct module *me, void *location, return -EINVAL; } +static int apply_r_riscv_add8_rela(struct module *me, void *location, Elf_Addr v) +{ + *(u8 *)location += (u8)v; + return 0; +} + static int apply_r_riscv_add16_rela(struct module *me, void *location, Elf_Addr v) { @@ -294,6 +335,12 @@ static int apply_r_riscv_add64_rela(struct module *me, void *location, return 0; } +static int apply_r_riscv_sub8_rela(struct module *me, void *location, Elf_Addr v) +{ + *(u8 *)location -= (u8)v; + return 0; +} + static int apply_r_riscv_sub16_rela(struct module *me, void *location, Elf_Addr v) { @@ -315,33 +362,369 @@ static int apply_r_riscv_sub64_rela(struct module *me, void *location, return 0; } -static int (*reloc_handlers_rela[]) (struct module *me, void *location, - Elf_Addr v) = { - [R_RISCV_32] = apply_r_riscv_32_rela, - [R_RISCV_64] = apply_r_riscv_64_rela, - [R_RISCV_BRANCH] = apply_r_riscv_branch_rela, - [R_RISCV_JAL] = apply_r_riscv_jal_rela, - [R_RISCV_RVC_BRANCH] = apply_r_riscv_rvc_branch_rela, - [R_RISCV_RVC_JUMP] = apply_r_riscv_rvc_jump_rela, - [R_RISCV_PCREL_HI20] = apply_r_riscv_pcrel_hi20_rela, - [R_RISCV_PCREL_LO12_I] = apply_r_riscv_pcrel_lo12_i_rela, - [R_RISCV_PCREL_LO12_S] = apply_r_riscv_pcrel_lo12_s_rela, - [R_RISCV_HI20] = apply_r_riscv_hi20_rela, - [R_RISCV_LO12_I] = apply_r_riscv_lo12_i_rela, - [R_RISCV_LO12_S] = apply_r_riscv_lo12_s_rela, - [R_RISCV_GOT_HI20] = apply_r_riscv_got_hi20_rela, - [R_RISCV_CALL_PLT] = apply_r_riscv_call_plt_rela, - [R_RISCV_CALL] = apply_r_riscv_call_rela, - [R_RISCV_RELAX] = apply_r_riscv_relax_rela, - [R_RISCV_ALIGN] = apply_r_riscv_align_rela, - [R_RISCV_ADD16] = apply_r_riscv_add16_rela, - [R_RISCV_ADD32] = apply_r_riscv_add32_rela, - [R_RISCV_ADD64] = apply_r_riscv_add64_rela, - [R_RISCV_SUB16] = apply_r_riscv_sub16_rela, - [R_RISCV_SUB32] = apply_r_riscv_sub32_rela, - [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, +static int dynamic_linking_not_supported(struct module *me, void *location, + Elf_Addr v) +{ + pr_err("%s: Dynamic linking not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int tls_not_supported(struct module *me, void *location, Elf_Addr v) +{ + pr_err("%s: Thread local storage not supported in kernel modules PC = %p\n", + me->name, location); + return -EINVAL; +} + +static int apply_r_riscv_sub6_rela(struct module *me, void *location, Elf_Addr v) +{ + u8 *byte = location; + u8 value = v; + + *byte = (*byte - (value & 0x3f)) & 0x3f; + return 0; +} + +static int apply_r_riscv_set6_rela(struct module *me, void *location, Elf_Addr v) +{ + u8 *byte = location; + u8 value = v; + + *byte = (*byte & 0xc0) | (value & 0x3f); + return 0; +} + +static int apply_r_riscv_set8_rela(struct module *me, void *location, Elf_Addr v) +{ + *(u8 *)location = (u8)v; + return 0; +} + +static int apply_r_riscv_set16_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u16 *)location = (u16)v; + return 0; +} + +static int apply_r_riscv_set32_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location = (u32)v; + return 0; +} + +static int apply_r_riscv_32_pcrel_rela(struct module *me, void *location, + Elf_Addr v) +{ + *(u32 *)location = v - (uintptr_t)location; + return 0; +} + +static int apply_r_riscv_plt32_rela(struct module *me, void *location, + Elf_Addr v) +{ + ptrdiff_t offset = (void *)v - location; + + if (!riscv_insn_valid_32bit_offset(offset)) { + /* Only emit the plt entry if offset over 32-bit range */ + if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) { + offset = (void *)module_emit_plt_entry(me, v) - location; + } else { + pr_err("%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n", + me->name, (long long)v, location); + return -EINVAL; + } + } + + *(u32 *)location = (u32)offset; + return 0; +} + +static int apply_r_riscv_set_uleb128(struct module *me, void *location, Elf_Addr v) +{ + *(long *)location = v; + return 0; +} + +static int apply_r_riscv_sub_uleb128(struct module *me, void *location, Elf_Addr v) +{ + *(long *)location -= v; + return 0; +} + +static int apply_6_bit_accumulation(struct module *me, void *location, long buffer) +{ + u8 *byte = location; + u8 value = buffer; + + if (buffer > 0x3f) { + pr_err("%s: value %ld out of range for 6-bit relocation.\n", + me->name, buffer); + return -EINVAL; + } + + *byte = (*byte & 0xc0) | (value & 0x3f); + return 0; +} + +static int apply_8_bit_accumulation(struct module *me, void *location, long buffer) +{ + if (buffer > U8_MAX) { + pr_err("%s: value %ld out of range for 8-bit relocation.\n", + me->name, buffer); + return -EINVAL; + } + *(u8 *)location = (u8)buffer; + return 0; +} + +static int apply_16_bit_accumulation(struct module *me, void *location, long buffer) +{ + if (buffer > U16_MAX) { + pr_err("%s: value %ld out of range for 16-bit relocation.\n", + me->name, buffer); + return -EINVAL; + } + *(u16 *)location = (u16)buffer; + return 0; +} + +static int apply_32_bit_accumulation(struct module *me, void *location, long buffer) +{ + if (buffer > U32_MAX) { + pr_err("%s: value %ld out of range for 32-bit relocation.\n", + me->name, buffer); + return -EINVAL; + } + *(u32 *)location = (u32)buffer; + return 0; +} + +static int apply_64_bit_accumulation(struct module *me, void *location, long buffer) +{ + *(u64 *)location = (u64)buffer; + return 0; +} + +static int apply_uleb128_accumulation(struct module *me, void *location, long buffer) +{ + /* + * ULEB128 is a variable length encoding. Encode the buffer into + * the ULEB128 data format. + */ + u8 *p = location; + + while (buffer != 0) { + u8 value = buffer & 0x7f; + + buffer >>= 7; + value |= (!!buffer) << 7; + + *p++ = value; + } + return 0; +} + +/* + * Relocations defined in the riscv-elf-psabi-doc. + * This handles static linking only. + */ +static const struct relocation_handlers reloc_handlers[] = { + [R_RISCV_32] = { apply_r_riscv_32_rela }, + [R_RISCV_64] = { apply_r_riscv_64_rela }, + [R_RISCV_RELATIVE] = { dynamic_linking_not_supported }, + [R_RISCV_COPY] = { dynamic_linking_not_supported }, + [R_RISCV_JUMP_SLOT] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_DTPMOD32] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_DTPMOD64] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_DTPREL32] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_DTPREL64] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_TPREL32] = { dynamic_linking_not_supported }, + [R_RISCV_TLS_TPREL64] = { dynamic_linking_not_supported }, + /* 12-15 undefined */ + [R_RISCV_BRANCH] = { apply_r_riscv_branch_rela }, + [R_RISCV_JAL] = { apply_r_riscv_jal_rela }, + [R_RISCV_CALL] = { apply_r_riscv_call_rela }, + [R_RISCV_CALL_PLT] = { apply_r_riscv_call_plt_rela }, + [R_RISCV_GOT_HI20] = { apply_r_riscv_got_hi20_rela }, + [R_RISCV_TLS_GOT_HI20] = { tls_not_supported }, + [R_RISCV_TLS_GD_HI20] = { tls_not_supported }, + [R_RISCV_PCREL_HI20] = { apply_r_riscv_pcrel_hi20_rela }, + [R_RISCV_PCREL_LO12_I] = { apply_r_riscv_pcrel_lo12_i_rela }, + [R_RISCV_PCREL_LO12_S] = { apply_r_riscv_pcrel_lo12_s_rela }, + [R_RISCV_HI20] = { apply_r_riscv_hi20_rela }, + [R_RISCV_LO12_I] = { apply_r_riscv_lo12_i_rela }, + [R_RISCV_LO12_S] = { apply_r_riscv_lo12_s_rela }, + [R_RISCV_TPREL_HI20] = { tls_not_supported }, + [R_RISCV_TPREL_LO12_I] = { tls_not_supported }, + [R_RISCV_TPREL_LO12_S] = { tls_not_supported }, + [R_RISCV_TPREL_ADD] = { tls_not_supported }, + [R_RISCV_ADD8] = { apply_r_riscv_add8_rela, apply_8_bit_accumulation }, + [R_RISCV_ADD16] = { apply_r_riscv_add16_rela, + apply_16_bit_accumulation }, + [R_RISCV_ADD32] = { apply_r_riscv_add32_rela, + apply_32_bit_accumulation }, + [R_RISCV_ADD64] = { apply_r_riscv_add64_rela, + apply_64_bit_accumulation }, + [R_RISCV_SUB8] = { apply_r_riscv_sub8_rela, apply_8_bit_accumulation }, + [R_RISCV_SUB16] = { apply_r_riscv_sub16_rela, + apply_16_bit_accumulation }, + [R_RISCV_SUB32] = { apply_r_riscv_sub32_rela, + apply_32_bit_accumulation }, + [R_RISCV_SUB64] = { apply_r_riscv_sub64_rela, + apply_64_bit_accumulation }, + /* 41-42 reserved for future standard use */ + [R_RISCV_ALIGN] = { apply_r_riscv_align_rela }, + [R_RISCV_RVC_BRANCH] = { apply_r_riscv_rvc_branch_rela }, + [R_RISCV_RVC_JUMP] = { apply_r_riscv_rvc_jump_rela }, + /* 46-50 reserved for future standard use */ + [R_RISCV_RELAX] = { apply_r_riscv_relax_rela }, + [R_RISCV_SUB6] = { apply_r_riscv_sub6_rela, apply_6_bit_accumulation }, + [R_RISCV_SET6] = { apply_r_riscv_set6_rela, apply_6_bit_accumulation }, + [R_RISCV_SET8] = { apply_r_riscv_set8_rela, apply_8_bit_accumulation }, + [R_RISCV_SET16] = { apply_r_riscv_set16_rela, + apply_16_bit_accumulation }, + [R_RISCV_SET32] = { apply_r_riscv_set32_rela, + apply_32_bit_accumulation }, + [R_RISCV_32_PCREL] = { apply_r_riscv_32_pcrel_rela }, + [R_RISCV_IRELATIVE] = { dynamic_linking_not_supported }, + [R_RISCV_PLT32] = { apply_r_riscv_plt32_rela }, + [R_RISCV_SET_ULEB128] = { apply_r_riscv_set_uleb128, + apply_uleb128_accumulation }, + [R_RISCV_SUB_ULEB128] = { apply_r_riscv_sub_uleb128, + apply_uleb128_accumulation }, + /* 62-191 reserved for future standard use */ + /* 192-255 nonstandard ABI extensions */ }; +void process_accumulated_relocations(struct module *me) +{ + /* + * Only ADD/SUB/SET/ULEB128 should end up here. + * + * Each bucket may have more than one relocation location. All + * relocations for a location are stored in a list in a bucket. + * + * Relocations are applied to a temp variable before being stored to the + * provided location to check for overflow. This also allows ULEB128 to + * properly decide how many entries are needed before storing to + * location. The final value is stored into location using the handler + * for the last relocation to an address. + * + * Three layers of indexing: + * - Each of the buckets in use + * - Groups of relocations in each bucket by location address + * - Each relocation entry for a location address + */ + struct used_bucket *bucket_iter; + struct relocation_head *rel_head_iter; + struct relocation_entry *rel_entry_iter; + int curr_type; + void *location; + long buffer; + + list_for_each_entry(bucket_iter, &used_buckets_list, head) { + hlist_for_each_entry(rel_head_iter, bucket_iter->bucket, node) { + buffer = 0; + location = rel_head_iter->location; + list_for_each_entry(rel_entry_iter, + rel_head_iter->rel_entry, head) { + curr_type = rel_entry_iter->type; + reloc_handlers[curr_type].reloc_handler( + me, &buffer, rel_entry_iter->value); + kfree(rel_entry_iter); + } + reloc_handlers[curr_type].accumulate_handler( + me, location, buffer); + kfree(rel_head_iter); + } + kfree(bucket_iter); + } + + kfree(relocation_hashtable); +} + +int add_relocation_to_accumulate(struct module *me, int type, void *location, + unsigned int hashtable_bits, Elf_Addr v) +{ + struct relocation_entry *entry; + struct relocation_head *rel_head; + struct hlist_head *current_head; + struct used_bucket *bucket; + unsigned long hash; + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + INIT_LIST_HEAD(&entry->head); + entry->type = type; + entry->value = v; + + hash = hash_min((uintptr_t)location, hashtable_bits); + + current_head = &relocation_hashtable[hash]; + + /* Find matching location (if any) */ + bool found = false; + struct relocation_head *rel_head_iter; + + hlist_for_each_entry(rel_head_iter, current_head, node) { + if (rel_head_iter->location == location) { + found = true; + rel_head = rel_head_iter; + break; + } + } + + if (!found) { + rel_head = kmalloc(sizeof(*rel_head), GFP_KERNEL); + rel_head->rel_entry = + kmalloc(sizeof(struct list_head), GFP_KERNEL); + INIT_LIST_HEAD(rel_head->rel_entry); + rel_head->location = location; + INIT_HLIST_NODE(&rel_head->node); + if (!current_head->first) { + bucket = + kmalloc(sizeof(struct used_bucket), GFP_KERNEL); + INIT_LIST_HEAD(&bucket->head); + bucket->bucket = current_head; + list_add(&bucket->head, &used_buckets_list); + } + hlist_add_head(&rel_head->node, current_head); + } + + /* Add relocation to head of discovered rel_head */ + list_add_tail(&entry->head, rel_head->rel_entry); + + return 0; +} + +unsigned int initialize_relocation_hashtable(unsigned int num_relocations) +{ + /* Can safely assume that bits is not greater than sizeof(long) */ + unsigned long hashtable_size = roundup_pow_of_two(num_relocations); + unsigned int hashtable_bits = ilog2(hashtable_size); + + /* + * Double size of hashtable if num_relocations * 1.25 is greater than + * hashtable_size. + */ + int should_double_size = ((num_relocations + (num_relocations >> 2)) > (hashtable_size)); + + hashtable_bits += should_double_size; + + hashtable_size <<= should_double_size; + + relocation_hashtable = kmalloc_array(hashtable_size, + sizeof(*relocation_hashtable), + GFP_KERNEL); + __hash_init(relocation_hashtable, hashtable_size); + + INIT_LIST_HEAD(&used_buckets_list); + + return hashtable_bits; +} + int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relsec, struct module *me) @@ -353,11 +736,13 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int i, type; Elf_Addr v; int res; + unsigned int num_relocations = sechdrs[relsec].sh_size / sizeof(*rel); + unsigned int hashtable_bits = initialize_relocation_hashtable(num_relocations); pr_debug("Applying relocate section %u to %u\n", relsec, sechdrs[relsec].sh_info); - for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { + for (i = 0; i < num_relocations; i++) { /* This is where to make the change */ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr + rel[i].r_offset; @@ -375,8 +760,8 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, type = ELF_RISCV_R_TYPE(rel[i].r_info); - if (type < ARRAY_SIZE(reloc_handlers_rela)) - handler = reloc_handlers_rela[type]; + if (type < ARRAY_SIZE(reloc_handlers)) + handler = reloc_handlers[type].reloc_handler; else handler = NULL; @@ -432,11 +817,16 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, } } - res = handler(me, location, v); + if (reloc_handlers[type].accumulate_handler) + res = add_relocation_to_accumulate(me, type, location, hashtable_bits, v); + else + res = handler(me, location, v); if (res) return res; } + process_accumulated_relocations(me); + return 0; } From patchwork Wed Nov 1 18:33:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charlie Jenkins X-Patchwork-Id: 13442989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABF7C4167B for ; Wed, 1 Nov 2023 18:33:17 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 67C52900019; Wed, 1 Nov 2023 14:33:17 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 62B8B90000D; Wed, 1 Nov 2023 14:33:17 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 47E97900019; Wed, 1 Nov 2023 14:33:17 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 33BAA90000D for ; Wed, 1 Nov 2023 14:33:17 -0400 (EDT) Received: from smtpin21.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id DB1D5A09C3 for ; Wed, 1 Nov 2023 18:33:16 +0000 (UTC) X-FDA: 81410232792.21.9981DF5 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) by imf12.hostedemail.com (Postfix) with ESMTP id 9B27340020 for ; Wed, 1 Nov 2023 18:33:14 +0000 (UTC) Authentication-Results: imf12.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Y0hOvsin; spf=pass (imf12.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.49 as permitted sender) smtp.mailfrom=charlie@rivosinc.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1698863594; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=kzym5qAuTfM0R7xLqOGuP3tKqEclOj4G4PtzJ407Bo8=; b=SnhryJMINFnYdiipLlnn662aSeoO25Quy1oPOQ1JlbjXA8EAEiP4Ya5inMtF7LCyX78bjq IP6CILYmvRYTKdPKAFefVJdzsOo2sSTREkDFYeRjNUjqHmaxmZsaBivYajXo8+JwgS0wi/ d4zIo4wf9KItJVFQgefEYSOD3xtZv/Q= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1698863594; a=rsa-sha256; cv=none; b=ZPg+ZiuJ9CMy/Rs7vMJGzVF1JtlXtSRBzO5RX3ByAyXM7fXjQfJHVzrNyI7u+t9wWfhTNY LWdfHFVj+Ld/E3unbHLT7KgR3IOJ7c6e/IBPw7Fmt+EF5LRKJ+7/yfsyQ8AiU6wW+BnXIa NZE5eq0e4HFjY0JetJumuOdyutvWN30= ARC-Authentication-Results: i=1; imf12.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Y0hOvsin; spf=pass (imf12.hostedemail.com: domain of charlie@rivosinc.com designates 209.85.161.49 as permitted sender) smtp.mailfrom=charlie@rivosinc.com; dmarc=none Received: by mail-oo1-f49.google.com with SMTP id 006d021491bc7-586753b0ab0so48542eaf.0 for ; Wed, 01 Nov 2023 11:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1698863594; x=1699468394; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kzym5qAuTfM0R7xLqOGuP3tKqEclOj4G4PtzJ407Bo8=; b=Y0hOvsineiyvRylrzLPZ7aRnr/XrTOgFmm9oBdiFazwa9yC0DTyHZ7rmYvOFBSk6vS /O82xzbtRBt6VWg0HupGiA9BW654HgJ+rs7k1ziX4ggA+K8So3GZt6acGyNleN5I8dOV rgx5ltQ03ze4Y5aXvtM2AnZpwiuFi+iKpxcEUkixcB3xFIjj7Gn4v5aHbOfxFhHRYiUZ HQzQx2z6kMp3Bd+KDW57BdYv7dADRJXICIcZ7wgjklSlP8Yd9/m7F5lMazMc+fy22XFm kky4hRXPe620dHLgKDYTyNc2ik75OW+EPsTAjMO/K8BZEXrR9HBo6NTCa6ysLrgi/LSE jQLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698863594; x=1699468394; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kzym5qAuTfM0R7xLqOGuP3tKqEclOj4G4PtzJ407Bo8=; b=LprQSbf2qPswCgcThUpMsq1b1Xwc+ENstBrn3R0fx/W87+YRqWDxNYqJI4Q/Hh7tEp mGKZD05Rgn7wto6MzaN6LdQknTCu5DOSimgWm73K7byU4mExbXICGjxdpDBQ5seHbY7y f53WGIzKu6SQXBHcrJiMOMOp9kok+6oqHm23stKm7VabjK+7Hmg4w42hn/v+IyWj1lRN mJj2Q0XC/0fkDxN7ezrHEF4+f6vPAZ19kI9USmvi0hEXLszxMVKDb7ljC1XaJpXQlWSQ b93tpdLzaBifRuz8ZVnRGZ6H5yGIBv3S7Z92CBT7yUVErqhJAM1Sc/4nxB+GARvsWOiK o/Fg== X-Gm-Message-State: AOJu0Yzl9dIYjBT2mKdpT+G1MbqHOvRpZ8S5zI6rMZrUlOyA4TYuYeCp LbBhLdUS5lZ9BdwlroXIh8jaxA== X-Google-Smtp-Source: AGHT+IGPykU1VAnmKtV6v/xCZ27BmCrY2v2Ca7ppJpDIL7x72MGirnypYyNdK8vfqUeRM7Qf6lLMTA== X-Received: by 2002:a4a:e7d5:0:b0:581:f6d8:5ca2 with SMTP id y21-20020a4ae7d5000000b00581f6d85ca2mr15644287oov.6.1698863591382; Wed, 01 Nov 2023 11:33:11 -0700 (PDT) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id m14-20020a4aab8e000000b00581e090fd1fsm686331oon.8.2023.11.01.11.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 11:33:10 -0700 (PDT) From: Charlie Jenkins Date: Wed, 01 Nov 2023 11:33:01 -0700 Subject: [PATCH v9 3/3] riscv: Add tests for riscv module loading MIME-Version: 1.0 Message-Id: <20231101-module_relocations-v9-3-8dfa3483c400@rivosinc.com> References: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> In-Reply-To: <20231101-module_relocations-v9-0-8dfa3483c400@rivosinc.com> To: linux-riscv@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org Cc: Eric Biederman , Kees Cook , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andreas Schwab , Emil Renner Berthing , Samuel Holland , Nelson Chu , Charlie Jenkins X-Mailer: b4 0.12.3 X-Rspamd-Queue-Id: 9B27340020 X-Rspam-User: X-Stat-Signature: 6redabn7q7u6iqp8cpppf3furcq1xshx X-Rspamd-Server: rspam03 X-HE-Tag: 1698863594-595171 X-HE-Meta: U2FsdGVkX1/DMm7obLhNTvgc0XJEYe+F+l15XI2a5B8uIivEaL34mm6GWMXcqizOodRAzAte7oRCujXmtfiwbSol2Y22ul1ngexx+dkncqzpPVp4t0cRcERMWtBlC2s7lt6GusH5LCFxWMaeUeKZys6p5DIDy/iDxRwpvAH7vLxKItr9CB4JFGotCZL1TVUKvBi3XUsjPyziCpfApghmxz20ICiyZsdN08Sy0bBbp9qi0zvqi5Z2IMpRd/vJ2JhEit3H5HatteghV02KxiOchuTp4+P4UUpCk2ZReLl2PPnY3PDMSlK8BwxO7mNdLqYjD1QfUvzUNBmtE+o/AVQwx/UMlXaKhP+husMPwuNaWJbDLy7Tqhg6Knqcnd6KJaZnWQySbjJrzWZpGS3C/5GWsow71qTIPTrEi0VkruVMLvJJOJ2xlOyZatDp1QbLxdI6jbLYgAySCtNg4B3sF1b7et0OYPcjtPQIHICUFt/VLc8a1QOk4pb50U+a/pRNTnnmNUJ2eEQYbUx/c7sVTq9Uv8hTjFpfeX2VBJjJdsjSLsY9fK9gNj06Aep9lJUWLD10BPGxwedsEEiNdmwcuYfwIqTAvX7fHpaeEoCzPoYN+pjR3YAyROzoQudqynWRcA6g2Xpa35QCsXTIyJhyUSUvlhLcrRqttCxh5A1HVBVix68B0ZRhkY8JdPjv9l9HSxioljXrlrKcTHTJat65KG2of9qGl00lQCGWp1MAQqt9OayV6SiW8UXykrRV/HHLlASbFaJSXDYRgYj5BSFLxy33lmf9CxYB1panuXIkPXl0VbiYjbLyGMXxQpbkSG1pS4qJdQGtm68nEl21/fkgXdGnwv8eDUDXP2uWINLO+tMPq/e0iUWCH6E8Kq0xVuqCnchaQE+B7DY4wOXpalNtv+G9he6BDlolvV6q7vZSO6rLY+9TBa0ynMrkcFS1pCJYZ/wcpFTC5M0QFjfzBrl2NJz 0G9+wjbn eU2HyOwsD8DTVtNBKB1tIwoNDGbuCQRghRb0x0oOfriirH4nlQXcxndBc3bdb7BJLBRYqOmdBJEHBFaQ88CqrRSdsrIP0wv3hU5RBeKRWlqvkDYdcUDpekUSKNNL79RDAKr/RSHszSJluuN1z4GxrvEAFhjp+l25s8lBxZx6WxP2SgH5YQPbqWAsZKsezdj17ZqMpb+L3yPFemxOru58ygNA1CPX0b1gmzrnq9za126kcK4sGIAUxoHSKzL8+WC9so4YfoC+s88ydN/4x2Lv6LWFZ3HREBqPCQQPIDzmfzX52hpaurxMONQU0Dqc0Iv8eh74WP9R3su0NVrqBibGDckrJqBm4c0y30HVL9+LmRNz76P1Kd257nemdD/ViEssMehvwyHQYt8nwIfE6LJ/Np/MPAg0I/7rvSVQDBUNJveHUVxJKEDL2X7csM+ws+Mmnjdp59TSm8/fR12YK0urKjSykaLIq2f1qS2ACHIlS1GO7p/68hpQ8ZtXHu7ckW2wspGzCZy5NE+mRroM= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000104, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add test cases for the two main groups of relocations added: SUB and SET, along with uleb128. Signed-off-by: Charlie Jenkins --- arch/riscv/Kconfig.debug | 1 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/tests/Kconfig.debug | 35 +++++++++ arch/riscv/kernel/tests/Makefile | 1 + arch/riscv/kernel/tests/module_test/Makefile | 15 ++++ .../tests/module_test/test_module_linking_main.c | 88 ++++++++++++++++++++++ arch/riscv/kernel/tests/module_test/test_set16.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set32.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_set6.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_set8.S | 23 ++++++ arch/riscv/kernel/tests/module_test/test_sub16.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_sub32.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_sub6.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_sub64.S | 25 ++++++ arch/riscv/kernel/tests/module_test/test_sub8.S | 20 +++++ arch/riscv/kernel/tests/module_test/test_uleb128.S | 31 ++++++++ 16 files changed, 366 insertions(+) diff --git a/arch/riscv/Kconfig.debug b/arch/riscv/Kconfig.debug index e69de29bb2d1..eafe17ebf710 100644 --- a/arch/riscv/Kconfig.debug +++ b/arch/riscv/Kconfig.debug @@ -0,0 +1 @@ +source "arch/riscv/kernel/tests/Kconfig.debug" diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..bb99657252f4 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -57,6 +57,7 @@ obj-y += stacktrace.o obj-y += cacheinfo.o obj-y += patch.o obj-y += probes/ +obj-y += tests/ obj-$(CONFIG_MMU) += vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o diff --git a/arch/riscv/kernel/tests/Kconfig.debug b/arch/riscv/kernel/tests/Kconfig.debug new file mode 100644 index 000000000000..5dba64e8e977 --- /dev/null +++ b/arch/riscv/kernel/tests/Kconfig.debug @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "arch/riscv/kernel Testing and Coverage" + +config AS_HAS_ULEB128 + def_bool $(as-instr,.reloc label$(comma) R_RISCV_SET_ULEB128$(comma) 127\n.reloc label$(comma) R_RISCV_SUB_ULEB128$(comma) 127\nlabel:\n.word 0) + +menuconfig RUNTIME_KERNEL_TESTING_MENU + bool "arch/riscv/kernel runtime Testing" + def_bool y + help + Enable riscv kernel runtime testing. + +if RUNTIME_KERNEL_TESTING_MENU + +config RISCV_MODULE_LINKING_KUNIT + bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS + depends on KUNIT + default KUNIT_ALL_TESTS + help + Enable this option to test riscv module linking at boot. This will + enable a module called "test_module_linking". + + KUnit tests run during boot and output the results to the debug log + in TAP format (http://testanything.org/). Only useful for kernel devs + running the KUnit test harness, and not intended for inclusion into a + production build. + + For more information on KUnit and unit tests in general please refer + to the KUnit documentation in Documentation/dev-tools/kunit/. + + If unsure, say N. + +endif # RUNTIME_TESTING_MENU + +endmenu # "arch/riscv/kernel runtime Testing" diff --git a/arch/riscv/kernel/tests/Makefile b/arch/riscv/kernel/tests/Makefile new file mode 100644 index 000000000000..7d6c76cffe20 --- /dev/null +++ b/arch/riscv/kernel/tests/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_RISCV_MODULE_LINKING_KUNIT) += module_test/ diff --git a/arch/riscv/kernel/tests/module_test/Makefile b/arch/riscv/kernel/tests/module_test/Makefile new file mode 100644 index 000000000000..d7a6fd8943de --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/Makefile @@ -0,0 +1,15 @@ +obj-m += test_module_linking.o + +test_sub := test_sub6.o test_sub8.o test_sub16.o test_sub32.o test_sub64.o + +test_set := test_set6.o test_set8.o test_set16.o test_set32.o + +test_module_linking-objs += $(test_sub) + +test_module_linking-objs += $(test_set) + +ifeq ($(CONFIG_AS_HAS_ULEB128),y) +test_module_linking-objs += test_uleb128.o +endif + +test_module_linking-objs += test_module_linking_main.o diff --git a/arch/riscv/kernel/tests/module_test/test_module_linking_main.c b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c new file mode 100644 index 000000000000..8df5fa5b834e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_module_linking_main.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Rivos Inc. + */ + +#include +#include +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Test module linking"); + +extern int test_set32(void); +extern int test_set16(void); +extern int test_set8(void); +extern int test_set6(void); +extern long test_sub64(void); +extern int test_sub32(void); +extern int test_sub16(void); +extern int test_sub8(void); +extern int test_sub6(void); + +#ifdef CONFIG_AS_HAS_ULEB128 +extern int test_uleb_basic(void); +extern int test_uleb_large(void); +#endif + +#define CHECK_EQ(lhs, rhs) KUNIT_ASSERT_EQ(test, lhs, rhs) + +void run_test_set(struct kunit *test); +void run_test_sub(struct kunit *test); +void run_test_uleb(struct kunit *test); + +void run_test_set(struct kunit *test) +{ + int val32 = test_set32(); + int val16 = test_set16(); + int val8 = test_set8(); + int val6 = test_set6(); + + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +void run_test_sub(struct kunit *test) +{ + int val64 = test_sub64(); + int val32 = test_sub32(); + int val16 = test_sub16(); + int val8 = test_sub8(); + int val6 = test_sub6(); + + CHECK_EQ(val64, 0); + CHECK_EQ(val32, 0); + CHECK_EQ(val16, 0); + CHECK_EQ(val8, 0); + CHECK_EQ(val6, 0); +} + +#ifdef CONFIG_AS_HAS_ULEB128 +void run_test_uleb(struct kunit *test) +{ + int val_uleb = test_uleb_basic(); + int val_uleb2 = test_uleb_large(); + + CHECK_EQ(val_uleb, 0); + CHECK_EQ(val_uleb2, 0); +} +#endif + +static struct kunit_case __refdata riscv_module_linking_test_cases[] = { + KUNIT_CASE(run_test_set), + KUNIT_CASE(run_test_sub), +#ifdef CONFIG_AS_HAS_ULEB128 + KUNIT_CASE(run_test_uleb), +#endif + {} +}; + +static struct kunit_suite riscv_module_linking_test_suite = { + .name = "riscv_checksum", + .test_cases = riscv_module_linking_test_cases, +}; + +kunit_test_suites(&riscv_module_linking_test_suite); diff --git a/arch/riscv/kernel/tests/module_test/test_set16.S b/arch/riscv/kernel/tests/module_test/test_set16.S new file mode 100644 index 000000000000..2be0e441a12e --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set16.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set16 +test_set16: + lw a0, set16 + la t0, set16 +#ifdef CONFIG_32BIT + slli t0, t0, 16 + srli t0, t0, 16 +#else + slli t0, t0, 48 + srli t0, t0, 48 +#endif + sub a0, a0, t0 + ret +.data +set16: + .reloc set16, R_RISCV_SET16, set16 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set32.S b/arch/riscv/kernel/tests/module_test/test_set32.S new file mode 100644 index 000000000000..de0444537e67 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set32 +test_set32: + lw a0, set32 + la t0, set32 +#ifndef CONFIG_32BIT + slli t0, t0, 32 + srli t0, t0, 32 +#endif + sub a0, a0, t0 + ret +.data +set32: + .reloc set32, R_RISCV_SET32, set32 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set6.S b/arch/riscv/kernel/tests/module_test/test_set6.S new file mode 100644 index 000000000000..c39ce4c219eb --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set6.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set6 +test_set6: + lw a0, set6 + la t0, set6 +#ifdef CONFIG_32BIT + slli t0, t0, 26 + srli t0, t0, 26 +#else + slli t0, t0, 58 + srli t0, t0, 58 +#endif + sub a0, a0, t0 + ret +.data +set6: + .reloc set6, R_RISCV_SET6, set6 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_set8.S b/arch/riscv/kernel/tests/module_test/test_set8.S new file mode 100644 index 000000000000..a656173f6f99 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_set8.S @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_set8 +test_set8: + lw a0, set8 + la t0, set8 +#ifdef CONFIG_32BIT + slli t0, t0, 24 + srli t0, t0, 24 +#else + slli t0, t0, 56 + srli t0, t0, 56 +#endif + sub a0, a0, t0 + ret +.data +set8: + .reloc set8, R_RISCV_SET8, set8 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub16.S b/arch/riscv/kernel/tests/module_test/test_sub16.S new file mode 100644 index 000000000000..80f731d599ba --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub16.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub16 +test_sub16: + lh a0, sub16 + addi a0, a0, -32 + ret +first: + .space 32 +second: + +.data +sub16: + .reloc sub16, R_RISCV_ADD16, second + .reloc sub16, R_RISCV_SUB16, first + .half 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub32.S b/arch/riscv/kernel/tests/module_test/test_sub32.S new file mode 100644 index 000000000000..a341686e12df --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub32.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub32 +test_sub32: + lw a0, sub32 + addi a0, a0, -32 + ret +first: + .space 32 +second: + +.data +sub32: + .reloc sub32, R_RISCV_ADD32, second + .reloc sub32, R_RISCV_SUB32, first + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub6.S b/arch/riscv/kernel/tests/module_test/test_sub6.S new file mode 100644 index 000000000000..e8b61c1ec527 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub6.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub6 +test_sub6: + lb a0, sub6 + addi a0, a0, -32 + ret +first: + .space 32 +second: + +.data +sub6: + .reloc sub6, R_RISCV_SET6, second + .reloc sub6, R_RISCV_SUB6, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub64.S b/arch/riscv/kernel/tests/module_test/test_sub64.S new file mode 100644 index 000000000000..a59e8afa88fd --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub64.S @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub64 +test_sub64: +#ifdef CONFIG_32BIT + lw a0, sub64 +#else + ld a0, sub64 +#endif + addi a0, a0, -32 + ret +first: + .space 32 +second: + +.data +sub64: + .reloc sub64, R_RISCV_ADD64, second + .reloc sub64, R_RISCV_SUB64, first + .word 0 + .word 0 diff --git a/arch/riscv/kernel/tests/module_test/test_sub8.S b/arch/riscv/kernel/tests/module_test/test_sub8.S new file mode 100644 index 000000000000..ac5d0ec98de3 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_sub8.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_sub8 +test_sub8: + lb a0, sub8 + addi a0, a0, -32 + ret +first: + .space 32 +second: + +.data +sub8: + .reloc sub8, R_RISCV_ADD8, second + .reloc sub8, R_RISCV_SUB8, first + .byte 0 diff --git a/arch/riscv/kernel/tests/module_test/test_uleb128.S b/arch/riscv/kernel/tests/module_test/test_uleb128.S new file mode 100644 index 000000000000..90f22049d553 --- /dev/null +++ b/arch/riscv/kernel/tests/module_test/test_uleb128.S @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Rivos Inc. + */ + +.text +.global test_uleb_basic +test_uleb_basic: + ld a0, second + addi a0, a0, -127 + ret + +.global test_uleb_large +test_uleb_large: + ld a0, fourth + addi a0, a0, -0x07e8 + ret + +.data +first: + .space 127 +second: + .reloc second, R_RISCV_SET_ULEB128, second + .reloc second, R_RISCV_SUB_ULEB128, first + .dword 0 +third: + .space 1000 +fourth: + .reloc fourth, R_RISCV_SET_ULEB128, fourth + .reloc fourth, R_RISCV_SUB_ULEB128, third + .dword 0